xref: /llvm-project/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
2
3; Test that buffer_load_format with VGPR resource descriptor is properly
4; legalized.
5
6; Uses the old buffer_load_format intrinsics that don't take pointer
7; arguments.
8
9; CHECK-LABEL: {{^}}test_none:
10; CHECK: buffer_load_format_x v0, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
11define amdgpu_vs float @test_none(ptr addrspace(4) inreg %base, i32 %i) {
12main_body:
13  %ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
14  %tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
15  %tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 0, i32 0)
16  ret float %tmp7
17}
18
19; CHECK-LABEL: {{^}}test_idxen:
20; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen{{$}}
21define amdgpu_vs float @test_idxen(ptr addrspace(4) inreg %base, i32 %i) {
22main_body:
23  %ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
24  %tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
25  %tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0, i32 0)
26  ret float %tmp7
27}
28
29; CHECK-LABEL: {{^}}test_offen:
30; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
31define amdgpu_vs float @test_offen(ptr addrspace(4) inreg %base, i32 %i) {
32main_body:
33  %ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
34  %tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
35  %tmp7 = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i32 0)
36  ret float %tmp7
37}
38
39; CHECK-LABEL: {{^}}test_both:
40; CHECK: buffer_load_format_x v0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen{{$}}
41define amdgpu_vs float @test_both(ptr addrspace(4) inreg %base, i32 %i) {
42main_body:
43  %ptr = getelementptr <4 x i32>, ptr addrspace(4) %base, i32 %i
44  %tmp2 = load <4 x i32>, ptr addrspace(4) %ptr, align 32
45  %tmp7 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i32 0, i32 0)
46  ret float %tmp7
47}
48
49declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) #1
50declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32 immarg) #1
51
52attributes #0 = { nounwind readnone }
53attributes #1 = { nounwind readonly }
54