1; RUN: llc < %s 2target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" 3target triple = "amdgcn-amd-amdhsa" 4 5@_RSENC_gDcd_______________________________ = external protected addrspace(1) externally_initialized global [4096 x i8], align 16 6 7define protected amdgpu_kernel void @_RSENC_PRInit__________________________________(i1 %c0) local_unnamed_addr #0 { 8entry: 9 %runtimeVersionCopy = alloca [128 x i8], align 16, addrspace(5) 10 %licenseVersionCopy = alloca [128 x i8], align 16, addrspace(5) 11 %pD10 = alloca [128 x i8], align 16, addrspace(5) 12 br label %if.end 13 14if.end: ; preds = %entry 15 %0 = load i32, ptr undef, align 4 16 %mul = mul i32 %0, 3 17 %cmp13 = icmp eq i32 %mul, 989619 18 br i1 %cmp13, label %cleanup.cont, label %if.end15 19 20if.end15: ; preds = %if.end 21 br i1 %c0, label %cleanup.cont, label %lor.lhs.false17 22 23lor.lhs.false17: ; preds = %if.end15 24 br label %while.cond.i 25 26while.cond.i: ; preds = %while.cond.i, %lor.lhs.false17 27 switch i32 undef, label %if.end60 [ 28 i32 0, label %while.cond.i 29 i32 3, label %if.end60.loopexit857 30 ] 31 32if.end60.loopexit857: ; preds = %while.cond.i 33 br label %if.end60 34 35if.end60: ; preds = %if.end60.loopexit857, %while.cond.i 36 %1 = load i8, ptr addrspace(1) getelementptr inbounds ([4096 x i8], ptr addrspace(1) @_RSENC_gDcd_______________________________, i64 0, i64 655), align 1 37 %arrayidx144260.5 = getelementptr inbounds [128 x i8], ptr addrspace(5) %runtimeVersionCopy, i32 0, i32 5 38 %arrayidx156258.5 = getelementptr inbounds [128 x i8], ptr addrspace(5) %licenseVersionCopy, i32 0, i32 5 39 switch i8 0, label %if.end5.i [ 40 i8 45, label %if.then.i 41 i8 43, label %if.then3.i 42 ] 43 44if.then.i: ; preds = %if.end60 45 unreachable 46 47if.then3.i: ; preds = %if.end60 48 br label %if.end5.i 49 50if.end5.i: ; preds = %if.then3.i, %if.end60 51 %pS.addr.0.i = phi ptr addrspace(5) [ undef, %if.then3.i ], [ %runtimeVersionCopy, %if.end60 ] 52 %2 = load i8, ptr addrspace(5) %pS.addr.0.i, align 1 53 %conv612.i = sext i8 %2 to i32 54 %sub13.i = add nsw i32 %conv612.i, -48 55 %cmp714.i = icmp ugt i32 %sub13.i, 9 56 switch i8 undef, label %if.end5.i314 [ 57 i8 45, label %if.then.i306 58 i8 43, label %if.then3.i308 59 ] 60 61if.then.i306: ; preds = %if.end5.i 62 unreachable 63 64if.then3.i308: ; preds = %if.end5.i 65 br label %if.end5.i314 66 67if.end5.i314: ; preds = %if.then3.i308, %if.end5.i 68 %pS.addr.0.i309 = phi ptr addrspace(5) [ undef, %if.then3.i308 ], [ %licenseVersionCopy, %if.end5.i ] 69 %3 = load i8, ptr addrspace(5) %pS.addr.0.i309, align 1 70 %conv612.i311 = sext i8 %3 to i32 71 %sub13.i312 = add nsw i32 %conv612.i311, -48 72 %cmp714.i313 = icmp ugt i32 %sub13.i312, 9 73 switch i8 undef, label %if.end5.i338 [ 74 i8 45, label %if.then.i330 75 i8 43, label %if.then3.i332 76 ] 77 78if.then.i330: ; preds = %if.end5.i314 79 unreachable 80 81if.then3.i332: ; preds = %if.end5.i314 82 br label %if.end5.i338 83 84if.end5.i338: ; preds = %if.then3.i332, %if.end5.i314 85 %pS.addr.0.i333 = phi ptr addrspace(5) [ undef, %if.then3.i332 ], [ %arrayidx144260.5, %if.end5.i314 ] 86 %4 = load i8, ptr addrspace(5) %pS.addr.0.i333, align 1 87 %conv612.i335 = sext i8 %4 to i32 88 %sub13.i336 = add nsw i32 %conv612.i335, -48 89 %cmp714.i337 = icmp ugt i32 %sub13.i336, 9 90 switch i8 undef, label %if.end5.i362 [ 91 i8 45, label %if.then.i354 92 i8 43, label %if.then3.i356 93 ] 94 95if.then.i354: ; preds = %if.end5.i338 96 unreachable 97 98if.then3.i356: ; preds = %if.end5.i338 99 br label %if.end5.i362 100 101if.end5.i362: ; preds = %if.then3.i356, %if.end5.i338 102 %pS.addr.0.i357 = phi ptr addrspace(5) [ undef, %if.then3.i356 ], [ %arrayidx156258.5, %if.end5.i338 ] 103 %5 = load i8, ptr addrspace(5) %pS.addr.0.i357, align 1 104 %conv612.i359 = sext i8 %5 to i32 105 %sub13.i360 = add nsw i32 %conv612.i359, -48 106 %cmp714.i361 = icmp ugt i32 %sub13.i360, 9 107 store i8 0, ptr addrspace(5) undef, align 16 108 %6 = load i8, ptr addrspace(1) getelementptr inbounds ([4096 x i8], ptr addrspace(1) @_RSENC_gDcd_______________________________, i64 0, i64 1153), align 1 109 %arrayidx232250.1 = getelementptr inbounds [128 x i8], ptr addrspace(5) %pD10, i32 0, i32 1 110 store i8 %6, ptr addrspace(5) %arrayidx232250.1, align 1 111 switch i8 undef, label %if.end5.i400 [ 112 i8 45, label %if.then.i392 113 i8 43, label %if.then3.i394 114 ] 115 116if.then.i392: ; preds = %if.end5.i362 117 unreachable 118 119if.then3.i394: ; preds = %if.end5.i362 120 br label %if.end5.i400 121 122if.end5.i400: ; preds = %if.then3.i394, %if.end5.i362 123 %pS.addr.0.i395 = phi ptr addrspace(5) [ %arrayidx232250.1, %if.then3.i394 ], [ undef, %if.end5.i362 ] 124 %7 = load i8, ptr addrspace(5) %pS.addr.0.i395, align 1 125 %conv612.i397 = sext i8 %7 to i32 126 %sub13.i398 = add nsw i32 %conv612.i397, -48 127 %cmp714.i399 = icmp ugt i32 %sub13.i398, 9 128 %8 = load i8, ptr undef, align 1 129 %cmp9.not.i500 = icmp eq i8 0, %8 130 br label %land.lhs.true402.critedge 131 132land.lhs.true402.critedge: ; preds = %if.end5.i400 133 br i1 %cmp9.not.i500, label %if.then404, label %if.else407 134 135if.then404: ; preds = %land.lhs.true402.critedge 136 br label %for.body564 137 138if.else407: ; preds = %land.lhs.true402.critedge 139 br label %if.end570 140 141for.body564: ; preds = %for.body564, %if.then404 142 %i560.0801 = phi i32 [ 0, %if.then404 ], [ %inc568.31, %for.body564 ] 143 %inc568.31 = add nuw nsw i32 %i560.0801, 32 144 %exitcond839.not.31 = icmp eq i32 %inc568.31, 4096 145 br i1 %exitcond839.not.31, label %if.end570, label %for.body564 146 147if.end570: ; preds = %for.body564, %if.else407 148 unreachable 149 150cleanup.cont: ; preds = %if.end15, %if.end 151 ret void 152} 153 154attributes #0 = { "uniform-work-group-size"="true" } 155