xref: /llvm-project/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir (revision 2fa7d652d02ae5da0d32d63c4258705eadab1576) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=machine-sink -o -  %s | FileCheck %s
3
4---
5name: machine-sink-temporal-divergence
6tracksRegLiveness: true
7body: |
8  ; CHECK-LABEL: name: machine-sink-temporal-divergence
9  ; CHECK: bb.0:
10  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
11  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1_vgpr2
12  ; CHECK-NEXT: {{  $}}
13  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
14  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
15  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
16  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
17  ; CHECK-NEXT:   [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 1
18  ; CHECK-NEXT: {{  $}}
19  ; CHECK-NEXT: bb.1:
20  ; CHECK-NEXT:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
21  ; CHECK-NEXT: {{  $}}
22  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_1]], %bb.0, %6, %bb.1
23  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %8, %bb.1
24  ; CHECK-NEXT:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[PHI1]], [[S_MOV_B32_2]], implicit-def dead $scc
25  ; CHECK-NEXT:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[S_ADD_I32_]], 0, implicit $exec
26  ; CHECK-NEXT:   [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[S_ADD_I32_]], 0, 0, implicit $mode, implicit $exec
27  ; CHECK-NEXT:   [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_GT_F32_e64 0, killed [[V_CVT_F32_U32_e64_]], 0, [[COPY]], 0, implicit $mode, implicit $exec
28  ; CHECK-NEXT:   [[SI_IF_BREAK:%[0-9]+]]:sreg_32 = SI_IF_BREAK killed [[V_CMP_GT_F32_e64_]], [[PHI]], implicit-def dead $scc
29  ; CHECK-NEXT:   SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
30  ; CHECK-NEXT:   S_BRANCH %bb.2
31  ; CHECK-NEXT: {{  $}}
32  ; CHECK-NEXT: bb.2:
33  ; CHECK-NEXT:   SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
34  ; CHECK-NEXT:   FLAT_STORE_DWORD [[COPY1]], [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
35  ; CHECK-NEXT:   SI_RETURN
36  bb.0:
37    successors: %bb.1(0x80000000)
38    liveins: $vgpr0, $vgpr1_vgpr2
39
40    %0:vgpr_32 = COPY $vgpr0
41    %1:sreg_32 = S_MOV_B32 -1
42    %2:sreg_32 = S_MOV_B32 0
43    %3:vreg_64 = COPY $vgpr1_vgpr2
44    %4:sreg_32 = S_MOV_B32 1
45
46  bb.1:
47    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
48
49    %5:sreg_32 = PHI %2, %bb.0, %6, %bb.1
50    %7:sreg_32 = PHI %1, %bb.0, %8, %bb.1
51    %8:sreg_32 = S_ADD_I32 %7, %4, implicit-def dead $scc
52    %9:vgpr_32 = V_ADD_U32_e64 %8, %8, 0, implicit $exec
53    %10:vgpr_32 = V_CVT_F32_U32_e64 %8, 0, 0, implicit $mode, implicit $exec
54    %11:sreg_32 = nofpexcept V_CMP_GT_F32_e64 0, killed %10, 0, %0, 0, implicit $mode, implicit $exec
55    %6:sreg_32 = SI_IF_BREAK killed %11, %5, implicit-def dead $scc
56    SI_LOOP %6, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
57    S_BRANCH %bb.2
58
59  bb.2:
60    SI_END_CF %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
61    FLAT_STORE_DWORD %3, %9, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
62    SI_RETURN
63...
64
65---
66name: machine-sink-temporal-divergence-multiple-instructions
67tracksRegLiveness: true
68body: |
69  ; CHECK-LABEL: name: machine-sink-temporal-divergence-multiple-instructions
70  ; CHECK: bb.0:
71  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
72  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1_vgpr2
73  ; CHECK-NEXT: {{  $}}
74  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
75  ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
76  ; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
77  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
78  ; CHECK-NEXT:   [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 1
79  ; CHECK-NEXT: {{  $}}
80  ; CHECK-NEXT: bb.1:
81  ; CHECK-NEXT:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
82  ; CHECK-NEXT: {{  $}}
83  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_1]], %bb.0, %6, %bb.1
84  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %8, %bb.1
85  ; CHECK-NEXT:   [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[PHI1]], [[S_MOV_B32_2]], implicit-def dead $scc
86  ; CHECK-NEXT:   [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[S_MOV_B32_2]], implicit-def dead $scc
87  ; CHECK-NEXT:   [[S_ADD_I32_2:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_1]], [[S_MOV_B32_2]], implicit-def dead $scc
88  ; CHECK-NEXT:   [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_2]], [[S_ADD_I32_2]], 0, implicit $exec
89  ; CHECK-NEXT:   [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[S_ADD_I32_]], 0, 0, implicit $mode, implicit $exec
90  ; CHECK-NEXT:   [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_GT_F32_e64 0, killed [[V_CVT_F32_U32_e64_]], 0, [[COPY]], 0, implicit $mode, implicit $exec
91  ; CHECK-NEXT:   [[SI_IF_BREAK:%[0-9]+]]:sreg_32 = SI_IF_BREAK killed [[V_CMP_GT_F32_e64_]], [[PHI]], implicit-def dead $scc
92  ; CHECK-NEXT:   SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
93  ; CHECK-NEXT:   S_BRANCH %bb.2
94  ; CHECK-NEXT: {{  $}}
95  ; CHECK-NEXT: bb.2:
96  ; CHECK-NEXT:   SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
97  ; CHECK-NEXT:   FLAT_STORE_DWORD [[COPY1]], [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
98  ; CHECK-NEXT:   SI_RETURN
99  bb.0:
100    successors: %bb.1(0x80000000)
101    liveins: $vgpr0, $vgpr1_vgpr2
102
103    %0:vgpr_32 = COPY $vgpr0
104    %1:sreg_32 = S_MOV_B32 -1
105    %2:sreg_32 = S_MOV_B32 0
106    %3:vreg_64 = COPY $vgpr1_vgpr2
107    %4:sreg_32 = S_MOV_B32 1
108
109  bb.1:
110    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
111
112    %5:sreg_32 = PHI %2, %bb.0, %6, %bb.1
113    %7:sreg_32 = PHI %1, %bb.0, %8, %bb.1
114    %8:sreg_32 = S_ADD_I32 %7, %4, implicit-def dead $scc
115    %9:sreg_32 = S_ADD_I32 %8, %4, implicit-def dead $scc
116    %10:sreg_32 = S_ADD_I32 %9, %4, implicit-def dead $scc
117    %11:vgpr_32 = V_ADD_U32_e64 %10, %10, 0, implicit $exec
118    %12:vgpr_32 = V_CVT_F32_U32_e64 %8, 0, 0, implicit $mode, implicit $exec
119    %13:sreg_32 = nofpexcept V_CMP_GT_F32_e64 0, killed %12, 0, %0, 0, implicit $mode, implicit $exec
120    %6:sreg_32 = SI_IF_BREAK killed %13, %5, implicit-def dead $scc
121    SI_LOOP %6, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
122    S_BRANCH %bb.2
123
124  bb.2:
125    SI_END_CF %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
126    FLAT_STORE_DWORD %3, %11, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32))
127    SI_RETURN
128...
129