1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O3 < %s | FileCheck -check-prefix=GCN %s 2; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s 3; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s 4 5@a = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4 6@b = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4 7@c = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4 8 9; FIXME: Should combine the DS instructions into ds_write2 and ds_read2. This 10; does not happen because when SILoadStoreOptimizer is run, the reads and writes 11; are not adjacent. They are only moved later by MachineScheduler. 12 13define amdgpu_kernel void @no_clobber_ds_load_stores_x2(ptr addrspace(1) %arg, i32 %i) { 14; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x2( 15; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] { 16; CHECK-NEXT: bb: 17; CHECK-NEXT: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, align 16, !alias.scope !1, !noalias !4 18; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 [[I]] 19; CHECK-NEXT: [[VAL_A:%.*]] = load i32, ptr addrspace(3) [[GEP_A]], align 4, !alias.scope !1, !noalias !4 20; CHECK-NEXT: store i32 2, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 1), align 16, !alias.scope !4, !noalias !1 21; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 1), i32 0, i32 [[I]] 22; CHECK-NEXT: [[VAL_B:%.*]] = load i32, ptr addrspace(3) [[GEP_B]], align 4, !alias.scope !4, !noalias !1 23; CHECK-NEXT: [[VAL:%.*]] = add i32 [[VAL_A]], [[VAL_B]] 24; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4 25; CHECK-NEXT: ret void 26; 27; GCN-LABEL: no_clobber_ds_load_stores_x2: 28; GCN: ; %bb.0: ; %bb 29; GCN-NEXT: s_load_dword s0, s[4:5], 0x2c 30; GCN-NEXT: v_mov_b32_e32 v0, 1 31; GCN-NEXT: v_mov_b32_e32 v1, 0 32; GCN-NEXT: v_mov_b32_e32 v2, 2 33; GCN-NEXT: ds_write_b32 v1, v0 34; GCN-NEXT: s_waitcnt lgkmcnt(0) 35; GCN-NEXT: s_lshl_b32 s0, s0, 2 36; GCN-NEXT: v_mov_b32_e32 v0, s0 37; GCN-NEXT: ds_write_b32 v1, v2 offset:256 38; GCN-NEXT: ds_read_b32 v2, v0 39; GCN-NEXT: ds_read_b32 v0, v0 offset:256 40; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 41; GCN-NEXT: s_waitcnt lgkmcnt(0) 42; GCN-NEXT: v_add_u32_e32 v0, v2, v0 43; GCN-NEXT: global_store_dword v1, v0, s[0:1] 44; GCN-NEXT: s_endpgm 45bb: 46 store i32 1, ptr addrspace(3) @a, align 4 47 %gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i 48 %val.a = load i32, ptr addrspace(3) %gep.a, align 4 49 store i32 2, ptr addrspace(3) @b, align 4 50 %gep.b = getelementptr inbounds [64 x i32], ptr addrspace(3) @b, i32 0, i32 %i 51 %val.b = load i32, ptr addrspace(3) %gep.b, align 4 52 %val = add i32 %val.a, %val.b 53 store i32 %val, ptr addrspace(1) %arg, align 4 54 ret void 55} 56 57define amdgpu_kernel void @no_clobber_ds_load_stores_x3(ptr addrspace(1) %arg, i32 %i) { 58; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x3( 59; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]) #[[ATTR1:[0-9]+]] { 60; CHECK-NEXT: bb: 61; CHECK-NEXT: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, align 16, !alias.scope !6, !noalias !9 62; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 [[I]] 63; CHECK-NEXT: [[VAL_A:%.*]] = load i32, ptr addrspace(3) [[GEP_A]], align 4, !alias.scope !6, !noalias !9 64; CHECK-NEXT: store i32 2, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 1), align 16, !alias.scope !12, !noalias !13 65; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 1), i32 0, i32 [[I]] 66; CHECK-NEXT: [[VAL_B:%.*]] = load i32, ptr addrspace(3) [[GEP_B]], align 4, !alias.scope !12, !noalias !13 67; CHECK-NEXT: store i32 3, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 2), align 16, !alias.scope !14, !noalias !15 68; CHECK-NEXT: [[GEP_C:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 2), i32 0, i32 [[I]] 69; CHECK-NEXT: [[VAL_C:%.*]] = load i32, ptr addrspace(3) [[GEP_C]], align 4, !alias.scope !14, !noalias !15 70; CHECK-NEXT: [[VAL_1:%.*]] = add i32 [[VAL_A]], [[VAL_B]] 71; CHECK-NEXT: [[VAL:%.*]] = add i32 [[VAL_1]], [[VAL_C]] 72; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4 73; CHECK-NEXT: ret void 74; 75; GCN-LABEL: no_clobber_ds_load_stores_x3: 76; GCN: ; %bb.0: ; %bb 77; GCN-NEXT: s_load_dword s0, s[4:5], 0x2c 78; GCN-NEXT: v_mov_b32_e32 v1, 0 79; GCN-NEXT: v_mov_b32_e32 v2, 2 80; GCN-NEXT: v_mov_b32_e32 v0, 1 81; GCN-NEXT: ds_write_b32 v1, v2 offset:256 82; GCN-NEXT: s_waitcnt lgkmcnt(0) 83; GCN-NEXT: s_lshl_b32 s0, s0, 2 84; GCN-NEXT: v_mov_b32_e32 v2, 3 85; GCN-NEXT: ds_write_b32 v1, v0 86; GCN-NEXT: v_mov_b32_e32 v0, s0 87; GCN-NEXT: ds_write_b32 v1, v2 offset:512 88; GCN-NEXT: ds_read_b32 v2, v0 89; GCN-NEXT: ds_read_b32 v3, v0 offset:256 90; GCN-NEXT: ds_read_b32 v0, v0 offset:512 91; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 92; GCN-NEXT: s_waitcnt lgkmcnt(0) 93; GCN-NEXT: v_add_u32_e32 v2, v2, v3 94; GCN-NEXT: v_add_u32_e32 v0, v2, v0 95; GCN-NEXT: global_store_dword v1, v0, s[0:1] 96; GCN-NEXT: s_endpgm 97bb: 98 store i32 1, ptr addrspace(3) @a, align 4 99 %gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i 100 %val.a = load i32, ptr addrspace(3) %gep.a, align 4 101 store i32 2, ptr addrspace(3) @b, align 4 102 %gep.b = getelementptr inbounds [64 x i32], ptr addrspace(3) @b, i32 0, i32 %i 103 %val.b = load i32, ptr addrspace(3) %gep.b, align 4 104 store i32 3, ptr addrspace(3) @c, align 4 105 %gep.c = getelementptr inbounds [64 x i32], ptr addrspace(3) @c, i32 0, i32 %i 106 %val.c = load i32, ptr addrspace(3) %gep.c, align 4 107 %val.1 = add i32 %val.a, %val.b 108 %val = add i32 %val.1, %val.c 109 store i32 %val, ptr addrspace(1) %arg, align 4 110 ret void 111} 112 113; CHECK: !0 = !{i32 0, i32 1} 114; CHECK: !1 = !{!2} 115; CHECK: !2 = distinct !{!2, !3} 116; CHECK: !3 = distinct !{!3} 117; CHECK: !4 = !{!5} 118; CHECK: !5 = distinct !{!5, !3} 119; CHECK: !6 = !{!7} 120; CHECK: !7 = distinct !{!7, !8} 121; CHECK: !8 = distinct !{!8} 122; CHECK: !9 = !{!10, !11} 123; CHECK: !10 = distinct !{!10, !8} 124; CHECK: !11 = distinct !{!11, !8} 125; CHECK: !12 = !{!10} 126; CHECK: !13 = !{!7, !11} 127; CHECK: !14 = !{!11} 128; CHECK: !15 = !{!7, !10} 129