1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 2# RUN: llc -run-pass=liveintervals -run-pass=si-lower-control-flow -mtriple=amdgcn--amdpal -mcpu=gfx1030 -verify-machineinstrs -o - %s | FileCheck %s 3# RUN: llc -passes='require<live-intervals>,si-lower-control-flow' -mtriple=amdgcn--amdpal -mcpu=gfx1030 -o - %s | FileCheck %s 4 5# Check that verifier passes for the following. 6 7# Caused: Live segment doesn't end at a valid instruction 8--- 9name: _amdgpu_cs_main1 10tracksRegLiveness: true 11body: | 12 ; CHECK-LABEL: name: _amdgpu_cs_main1 13 ; CHECK: bb.0: 14 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) 15 ; CHECK-NEXT: liveins: $vgpr0 16 ; CHECK-NEXT: {{ $}} 17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 18 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec 19 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo 20 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc 21 ; CHECK-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_]], [[COPY1]], implicit-def dead $scc 22 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]] 23 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec 24 ; CHECK-NEXT: S_BRANCH %bb.2 25 ; CHECK-NEXT: {{ $}} 26 ; CHECK-NEXT: bb.1: 27 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, %3, implicit-def $scc 28 ; CHECK-NEXT: S_ENDPGM 0 29 ; CHECK-NEXT: {{ $}} 30 ; CHECK-NEXT: bb.2: 31 ; CHECK-NEXT: successors: %bb.3(0x80000000) 32 ; CHECK-NEXT: {{ $}} 33 ; CHECK-NEXT: bb.3: 34 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000) 35 ; CHECK-NEXT: {{ $}} 36 ; CHECK-NEXT: [[S_OR_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_OR_SAVEEXEC_B32 [[S_XOR_B32_]], implicit-def $exec, implicit-def $scc, implicit $exec 37 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[S_OR_SAVEEXEC_B32_]], implicit-def $scc 38 ; CHECK-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_B32_1]], implicit-def $scc 39 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec 40 ; CHECK-NEXT: S_BRANCH %bb.4 41 ; CHECK-NEXT: {{ $}} 42 ; CHECK-NEXT: bb.4: 43 ; CHECK-NEXT: successors: %bb.1(0x80000000) 44 ; CHECK-NEXT: {{ $}} 45 ; CHECK-NEXT: S_BRANCH %bb.1 46 bb.0: 47 successors: %bb.2(0x40000000), %bb.3(0x40000000) 48 liveins: $vgpr0 49 50 %2:vgpr_32 = COPY killed $vgpr0 51 %6:sreg_32 = V_CMP_NE_U32_e64 0, killed %2, implicit $exec 52 %0:sreg_32 = SI_IF killed %6, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 53 S_BRANCH %bb.2 54 55 bb.1: 56 SI_END_CF killed %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 57 S_ENDPGM 0 58 59 bb.2: 60 successors: %bb.3(0x80000000) 61 62 63 bb.3: 64 successors: %bb.4(0x40000000), %bb.1(0x40000000) 65 66 %1:sreg_32 = SI_ELSE killed %0, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 67 S_BRANCH %bb.4 68 69 bb.4: 70 successors: %bb.1(0x80000000) 71 72 S_BRANCH %bb.1 73 74... 75 76# Caused: Assertion `itr != mi2iMap.end() && "Instruction not in maps."' failed. 77--- 78name: _amdgpu_cs_main2 79tracksRegLiveness: true 80body: | 81 ; CHECK-LABEL: name: _amdgpu_cs_main2 82 ; CHECK: bb.0: 83 ; CHECK-NEXT: successors: %bb.1(0x80000000) 84 ; CHECK-NEXT: liveins: $vgpr0 85 ; CHECK-NEXT: {{ $}} 86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 87 ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 1, [[COPY]], implicit $exec 88 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 89 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]] 90 ; CHECK-NEXT: {{ $}} 91 ; CHECK-NEXT: bb.1: 92 ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) 93 ; CHECK-NEXT: {{ $}} 94 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY1]] 95 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[V_CMP_GT_I32_e64_]], implicit-def $scc 96 ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 97 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[S_OR_B32_]] 98 ; CHECK-NEXT: $exec_lo = S_ANDN2_B32_term $exec_lo, [[S_OR_B32_]], implicit-def $scc 99 ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec 100 ; CHECK-NEXT: S_BRANCH %bb.2 101 ; CHECK-NEXT: {{ $}} 102 ; CHECK-NEXT: bb.2: 103 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[S_OR_B32_]], implicit-def $scc 104 ; CHECK-NEXT: S_ENDPGM 0 105 bb.0: 106 successors: %bb.1(0x80000000) 107 liveins: $vgpr0 108 109 %4:vgpr_32 = COPY killed $vgpr0 110 %8:sreg_32 = V_CMP_GT_I32_e64 1, killed %4, implicit $exec 111 %6:sreg_32 = S_MOV_B32 0 112 %10:sreg_32 = COPY killed %6 113 114 bb.1: 115 successors: %bb.2(0x04000000), %bb.1(0x7c000000) 116 117 %1:sreg_32 = COPY killed %10 118 %2:sreg_32 = SI_IF_BREAK %8, killed %1, implicit-def dead $scc 119 %10:sreg_32 = COPY %2 120 SI_LOOP %2, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 121 S_BRANCH %bb.2 122 123 bb.2: 124 SI_END_CF killed %2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 125 S_ENDPGM 0 126 127... 128 129# Caused: Live range continues after kill flag 130--- 131name: _amdgpu_cs_main3 132tracksRegLiveness: true 133body: | 134 ; CHECK-LABEL: name: _amdgpu_cs_main3 135 ; CHECK: bb.0: 136 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000) 137 ; CHECK-NEXT: liveins: $vgpr0 138 ; CHECK-NEXT: {{ $}} 139 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 140 ; CHECK-NEXT: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_NGT_F32_e64 0, 0, 0, [[COPY]], 0, implicit $mode, implicit $exec 141 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo 142 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[V_CMP_NGT_F32_e64_]], implicit-def dead $scc 143 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]] 144 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec 145 ; CHECK-NEXT: S_BRANCH %bb.1 146 ; CHECK-NEXT: {{ $}} 147 ; CHECK-NEXT: bb.1: 148 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) 149 ; CHECK-NEXT: {{ $}} 150 ; CHECK-NEXT: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_NLT_F32_e64 0, 0, 0, [[COPY]], 0, implicit $mode, implicit $exec 151 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo 152 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[V_CMP_NLT_F32_e64_]], implicit-def dead $scc 153 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_1]] 154 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec 155 ; CHECK-NEXT: S_BRANCH %bb.2 156 ; CHECK-NEXT: {{ $}} 157 ; CHECK-NEXT: bb.2: 158 ; CHECK-NEXT: successors: %bb.4(0x80000000) 159 ; CHECK-NEXT: {{ $}} 160 ; CHECK-NEXT: bb.4: 161 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[COPY1]], implicit-def $scc 162 ; CHECK-NEXT: S_ENDPGM 0 163 bb.0: 164 successors: %bb.1(0x40000000), %bb.4(0x40000000) 165 liveins: $vgpr0 166 167 %2:vgpr_32 = COPY killed $vgpr0 168 %5:sreg_32 = nofpexcept V_CMP_NGT_F32_e64 0, 0, 0, %2, 0, implicit $mode, implicit $exec 169 %0:sreg_32 = SI_IF killed %5, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 170 S_BRANCH %bb.1 171 172 bb.1: 173 successors: %bb.2(0x40000000), %bb.3(0x40000000) 174 175 %7:sreg_32 = nofpexcept V_CMP_NLT_F32_e64 0, 0, 0, killed %2, 0, implicit $mode, implicit $exec 176 %1:sreg_32 = SI_IF killed %7, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 177 S_BRANCH %bb.2 178 179 bb.2: 180 successors: %bb.3(0x80000000) 181 182 183 bb.3: 184 successors: %bb.4(0x80000000) 185 186 SI_END_CF killed %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 187 188 bb.4: 189 SI_END_CF killed %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 190 S_ENDPGM 0 191 192... 193 194# Caused: Live range continues after dead def flag 195--- 196name: _amdgpu_cs_main4 197tracksRegLiveness: true 198body: | 199 ; CHECK-LABEL: name: _amdgpu_cs_main4 200 ; CHECK: bb.0: 201 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000) 202 ; CHECK-NEXT: liveins: $vgpr0 203 ; CHECK-NEXT: {{ $}} 204 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 205 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 206 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec 207 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo 208 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc 209 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]] 210 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec 211 ; CHECK-NEXT: S_BRANCH %bb.1 212 ; CHECK-NEXT: {{ $}} 213 ; CHECK-NEXT: bb.1: 214 ; CHECK-NEXT: successors: %bb.6(0x80000000) 215 ; CHECK-NEXT: {{ $}} 216 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $exec_lo 217 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY2]] 218 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]] 219 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY3]] 220 ; CHECK-NEXT: S_BRANCH %bb.6 221 ; CHECK-NEXT: {{ $}} 222 ; CHECK-NEXT: bb.2: 223 ; CHECK-NEXT: successors: %bb.5(0x80000000) 224 ; CHECK-NEXT: {{ $}} 225 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE %9, %subreg.sub0, %9, %subreg.sub1, %9, %subreg.sub2, %9, %subreg.sub3 226 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY %11 227 ; CHECK-NEXT: BUFFER_ATOMIC_ADD_OFFSET [[COPY6]], [[REG_SEQUENCE]], 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), align 1, addrspace 8) 228 ; CHECK-NEXT: S_BRANCH %bb.5 229 ; CHECK-NEXT: {{ $}} 230 ; CHECK-NEXT: bb.4: 231 ; CHECK-NEXT: S_ENDPGM 0 232 ; CHECK-NEXT: {{ $}} 233 ; CHECK-NEXT: bb.5: 234 ; CHECK-NEXT: successors: %bb.4(0x80000000) 235 ; CHECK-NEXT: {{ $}} 236 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[COPY1]], implicit-def $scc 237 ; CHECK-NEXT: S_BRANCH %bb.4 238 ; CHECK-NEXT: {{ $}} 239 ; CHECK-NEXT: bb.6: 240 ; CHECK-NEXT: successors: %bb.7(0x04000000), %bb.6(0x7c000000) 241 ; CHECK-NEXT: {{ $}} 242 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY4]] 243 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY5]] 244 ; CHECK-NEXT: [[S_FF1_I32_B32_:%[0-9]+]]:sreg_32 = S_FF1_I32_B32 [[COPY8]] 245 ; CHECK-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32 = V_READLANE_B32 [[COPY]], [[S_FF1_I32_B32_]] 246 ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY7]], [[V_READLANE_B32_]], implicit-def dead $scc 247 ; CHECK-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 1, [[S_FF1_I32_B32_]], implicit-def dead $scc 248 ; CHECK-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[COPY8]], [[S_LSHL_B32_]], implicit-def dead $scc 249 ; CHECK-NEXT: S_CMP_LG_U32 [[S_ANDN2_B32_]], 0, implicit-def $scc 250 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_ADD_I32_]] 251 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_ANDN2_B32_]] 252 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.6, implicit killed $scc 253 ; CHECK-NEXT: S_BRANCH %bb.7 254 ; CHECK-NEXT: {{ $}} 255 ; CHECK-NEXT: bb.7: 256 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000) 257 ; CHECK-NEXT: {{ $}} 258 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 259 ; CHECK-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY2]], 0, implicit $exec 260 ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 0, [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec 261 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo 262 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY9]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc 263 ; CHECK-NEXT: dead [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_1]], [[COPY9]], implicit-def dead $scc 264 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_1]] 265 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec 266 ; CHECK-NEXT: S_BRANCH %bb.2 267 bb.0: 268 successors: %bb.1(0x40000000), %bb.5(0x40000000) 269 liveins: $vgpr0 270 271 %8:vgpr_32 = COPY killed $vgpr0 272 %10:sreg_32 = S_MOV_B32 0 273 %11:sreg_32 = V_CMP_NE_U32_e64 0, %8, implicit $exec 274 %0:sreg_32 = SI_IF killed %11, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 275 S_BRANCH %bb.1 276 277 bb.1: 278 successors: %bb.6(0x80000000) 279 280 %13:sreg_32 = COPY $exec_lo 281 %1:sreg_32 = COPY %13 282 %25:sreg_32 = COPY killed %10 283 %26:sreg_32 = COPY killed %1 284 S_BRANCH %bb.6 285 286 bb.2: 287 successors: %bb.3(0x80000000) 288 289 %23:sgpr_128 = REG_SEQUENCE killed %19, %subreg.sub0, %19, %subreg.sub1, %19, %subreg.sub2, %19, %subreg.sub3 290 %24:vgpr_32 = COPY killed %4 291 BUFFER_ATOMIC_ADD_OFFSET killed %24, killed %23, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), align 1, addrspace 8) 292 293 bb.3: 294 successors: %bb.5(0x80000000) 295 296 SI_END_CF killed %7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 297 S_BRANCH %bb.5 298 299 bb.4: 300 S_ENDPGM 0 301 302 bb.5: 303 successors: %bb.4(0x80000000) 304 305 SI_END_CF killed %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 306 S_BRANCH %bb.4 307 308 bb.6: 309 successors: %bb.7(0x04000000), %bb.6(0x7c000000) 310 311 %2:sreg_32 = COPY killed %25 312 %3:sreg_32 = COPY killed %26 313 %14:sreg_32 = S_FF1_I32_B32 %3 314 %15:sreg_32 = V_READLANE_B32 %8, %14 315 %4:sreg_32 = S_ADD_I32 killed %2, killed %15, implicit-def dead $scc 316 %17:sreg_32 = S_LSHL_B32 1, killed %14, implicit-def dead $scc 317 %5:sreg_32 = S_ANDN2_B32 killed %3, killed %17, implicit-def dead $scc 318 S_CMP_LG_U32 %5, 0, implicit-def $scc 319 %25:sreg_32 = COPY %4 320 %26:sreg_32 = COPY killed %5 321 S_CBRANCH_SCC1 %bb.6, implicit killed $scc 322 S_BRANCH %bb.7 323 324 bb.7: 325 successors: %bb.2(0x40000000), %bb.3(0x40000000) 326 327 %19:sreg_32 = S_MOV_B32 0 328 %20:vgpr_32 = V_MBCNT_LO_U32_B32_e64 killed %13, 0, implicit $exec 329 %21:sreg_32 = V_CMP_EQ_U32_e64 0, killed %20, implicit $exec 330 %7:sreg_32 = SI_IF killed %21, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 331 S_BRANCH %bb.2 332 333... 334