1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s 3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s 4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s 5 6declare half @llvm.sqrt.f16(half %a) 7declare <2 x half> @llvm.sqrt.v2f16(<2 x half> %a) 8 9define amdgpu_kernel void @sqrt_f16( 10; SI-LABEL: sqrt_f16: 11; SI: ; %bb.0: ; %entry 12; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 13; SI-NEXT: s_mov_b32 s7, 0xf000 14; SI-NEXT: s_mov_b32 s6, -1 15; SI-NEXT: s_mov_b32 s10, s6 16; SI-NEXT: s_mov_b32 s11, s7 17; SI-NEXT: s_waitcnt lgkmcnt(0) 18; SI-NEXT: s_mov_b32 s8, s2 19; SI-NEXT: s_mov_b32 s9, s3 20; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 21; SI-NEXT: s_mov_b32 s4, s0 22; SI-NEXT: s_mov_b32 s5, s1 23; SI-NEXT: s_waitcnt vmcnt(0) 24; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 25; SI-NEXT: v_sqrt_f32_e32 v0, v0 26; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 27; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 28; SI-NEXT: s_endpgm 29; 30; VI-LABEL: sqrt_f16: 31; VI: ; %bb.0: ; %entry 32; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 33; VI-NEXT: s_mov_b32 s7, 0xf000 34; VI-NEXT: s_mov_b32 s6, -1 35; VI-NEXT: s_mov_b32 s10, s6 36; VI-NEXT: s_mov_b32 s11, s7 37; VI-NEXT: s_waitcnt lgkmcnt(0) 38; VI-NEXT: s_mov_b32 s8, s2 39; VI-NEXT: s_mov_b32 s9, s3 40; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 41; VI-NEXT: s_mov_b32 s4, s0 42; VI-NEXT: s_mov_b32 s5, s1 43; VI-NEXT: s_waitcnt vmcnt(0) 44; VI-NEXT: v_sqrt_f16_e32 v0, v0 45; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 46; VI-NEXT: s_endpgm 47; 48; GFX11-LABEL: sqrt_f16: 49; GFX11: ; %bb.0: ; %entry 50; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 51; GFX11-NEXT: s_mov_b32 s6, -1 52; GFX11-NEXT: s_mov_b32 s7, 0x31016000 53; GFX11-NEXT: s_mov_b32 s10, s6 54; GFX11-NEXT: s_mov_b32 s11, s7 55; GFX11-NEXT: s_waitcnt lgkmcnt(0) 56; GFX11-NEXT: s_mov_b32 s8, s2 57; GFX11-NEXT: s_mov_b32 s9, s3 58; GFX11-NEXT: s_mov_b32 s4, s0 59; GFX11-NEXT: buffer_load_u16 v0, off, s[8:11], 0 60; GFX11-NEXT: s_mov_b32 s5, s1 61; GFX11-NEXT: s_waitcnt vmcnt(0) 62; GFX11-NEXT: v_sqrt_f16_e32 v0, v0 63; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0 64; GFX11-NEXT: s_endpgm 65 ptr addrspace(1) %r, 66 ptr addrspace(1) %a) { 67entry: 68 %a.val = load half, ptr addrspace(1) %a 69 %r.val = call half @llvm.sqrt.f16(half %a.val) 70 store half %r.val, ptr addrspace(1) %r 71 ret void 72} 73 74; The original test with manual checks also had these NOT directives: 75; COM: SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 76; COM: SI-NOT: v_and_b32 77; COM: SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] 78; COM: VI-DAG: v_sqrt_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 79; COM: VI-NOT: v_and_b32 80; COM: VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] 81define amdgpu_kernel void @sqrt_v2f16( 82; SI-LABEL: sqrt_v2f16: 83; SI: ; %bb.0: ; %entry 84; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 85; SI-NEXT: s_mov_b32 s7, 0xf000 86; SI-NEXT: s_mov_b32 s6, -1 87; SI-NEXT: s_mov_b32 s10, s6 88; SI-NEXT: s_mov_b32 s11, s7 89; SI-NEXT: s_waitcnt lgkmcnt(0) 90; SI-NEXT: s_mov_b32 s8, s2 91; SI-NEXT: s_mov_b32 s9, s3 92; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0 93; SI-NEXT: s_mov_b32 s4, s0 94; SI-NEXT: s_mov_b32 s5, s1 95; SI-NEXT: s_waitcnt vmcnt(0) 96; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 97; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 98; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 99; SI-NEXT: v_sqrt_f32_e32 v1, v1 100; SI-NEXT: v_sqrt_f32_e32 v0, v0 101; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 102; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 103; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 104; SI-NEXT: v_or_b32_e32 v0, v0, v1 105; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 106; SI-NEXT: s_endpgm 107; 108; VI-LABEL: sqrt_v2f16: 109; VI: ; %bb.0: ; %entry 110; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 111; VI-NEXT: s_mov_b32 s7, 0xf000 112; VI-NEXT: s_mov_b32 s6, -1 113; VI-NEXT: s_mov_b32 s10, s6 114; VI-NEXT: s_mov_b32 s11, s7 115; VI-NEXT: s_waitcnt lgkmcnt(0) 116; VI-NEXT: s_mov_b32 s8, s2 117; VI-NEXT: s_mov_b32 s9, s3 118; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0 119; VI-NEXT: s_mov_b32 s4, s0 120; VI-NEXT: s_mov_b32 s5, s1 121; VI-NEXT: s_waitcnt vmcnt(0) 122; VI-NEXT: v_sqrt_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 123; VI-NEXT: v_sqrt_f16_e32 v0, v0 124; VI-NEXT: v_or_b32_e32 v0, v0, v1 125; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 126; VI-NEXT: s_endpgm 127; 128; GFX11-LABEL: sqrt_v2f16: 129; GFX11: ; %bb.0: ; %entry 130; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 131; GFX11-NEXT: s_mov_b32 s6, -1 132; GFX11-NEXT: s_mov_b32 s7, 0x31016000 133; GFX11-NEXT: s_mov_b32 s10, s6 134; GFX11-NEXT: s_mov_b32 s11, s7 135; GFX11-NEXT: s_waitcnt lgkmcnt(0) 136; GFX11-NEXT: s_mov_b32 s8, s2 137; GFX11-NEXT: s_mov_b32 s9, s3 138; GFX11-NEXT: s_mov_b32 s4, s0 139; GFX11-NEXT: buffer_load_b32 v0, off, s[8:11], 0 140; GFX11-NEXT: s_mov_b32 s5, s1 141; GFX11-NEXT: s_waitcnt vmcnt(0) 142; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 143; GFX11-NEXT: v_sqrt_f16_e32 v0, v0 144; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 145; GFX11-NEXT: v_sqrt_f16_e32 v1, v1 146; GFX11-NEXT: s_waitcnt_depctr 0xfff 147; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 148; GFX11-NEXT: buffer_store_b32 v0, off, s[4:7], 0 149; GFX11-NEXT: s_endpgm 150 ptr addrspace(1) %r, 151 ptr addrspace(1) %a) { 152entry: 153 %a.val = load <2 x half>, ptr addrspace(1) %a 154 %r.val = call <2 x half> @llvm.sqrt.v2f16(<2 x half> %a.val) 155 store <2 x half> %r.val, ptr addrspace(1) %r 156 ret void 157} 158