1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,VI,VI-SDAG %s 3; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,VI,VI-GISEL %s 4; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-SDAG,GFX900,GFX900-SDAG %s 5; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GCN-GISEL,GFX900,GFX900-GISEL %s 6; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-SDAG %s 7; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI,SI-GISEL %s 8 9; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s 10; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s 11 12; FIXME: Fallback enabled due to bfloat extensions 13 14define amdgpu_kernel void @s_exp10_f32(ptr addrspace(1) %out, float %in) { 15; VI-SDAG-LABEL: s_exp10_f32: 16; VI-SDAG: ; %bb.0: 17; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c 18; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549000 19; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 20; VI-SDAG-NEXT: s_and_b32 s0, s2, 0xfffff000 21; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0 22; VI-SDAG-NEXT: v_sub_f32_e32 v1, s2, v1 23; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1 24; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v1 25; VI-SDAG-NEXT: v_mul_f32_e32 v0, s0, v0 26; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v3 27; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x3a2784bc 28; VI-SDAG-NEXT: v_rndne_f32_e32 v2, v0 29; VI-SDAG-NEXT: v_mul_f32_e32 v3, s0, v3 30; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v2 31; VI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 32; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 33; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 34; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v2 35; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 36; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 37; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 38; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc23369f4 39; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v1 40; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x421a209b 41; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 42; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v1 43; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc 44; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 45; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0 46; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1 47; VI-SDAG-NEXT: flat_store_dword v[0:1], v2 48; VI-SDAG-NEXT: s_endpgm 49; 50; VI-GISEL-LABEL: s_exp10_f32: 51; VI-GISEL: ; %bb.0: 52; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c 53; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549000 54; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3a2784bc 55; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 56; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000 57; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0 58; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2 59; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v2 60; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 61; VI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 62; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 63; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v1 64; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 65; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v0 66; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2 67; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 68; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2 69; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 70; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 71; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 72; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 73; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4 74; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1 75; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b 76; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 77; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1 78; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc 79; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 80; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 81; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 82; VI-GISEL-NEXT: flat_store_dword v[0:1], v2 83; VI-GISEL-NEXT: s_endpgm 84; 85; GFX900-SDAG-LABEL: s_exp10_f32: 86; GFX900-SDAG: ; %bb.0: 87; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c 88; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 89; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 90; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 91; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) 92; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s2, v0 93; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v2 94; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v2 95; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 96; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v1, v0 97; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v2, v0 98; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v3 99; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 100; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x7f800000 101; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0 102; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 103; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc23369f4 104; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v1 105; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x421a209b 106; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 107; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v1 108; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc 109; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1] 110; GFX900-SDAG-NEXT: s_endpgm 111; 112; GFX900-GISEL-LABEL: s_exp10_f32: 113; GFX900-GISEL: ; %bb.0: 114; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c 115; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 116; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78 117; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37 118; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) 119; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0 120; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2 121; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 122; GFX900-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0 123; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3 124; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0 125; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3 126; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 127; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 128; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2 129; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 130; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 131; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b 132; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 133; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1 134; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 135; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 136; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] 137; GFX900-GISEL-NEXT: s_endpgm 138; 139; SI-SDAG-LABEL: s_exp10_f32: 140; SI-SDAG: ; %bb.0: 141; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb 142; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 143; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 144; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 145; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000 146; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 147; SI-SDAG-NEXT: v_mul_f32_e32 v2, s6, v0 148; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 149; SI-SDAG-NEXT: v_fma_f32 v0, s6, v0, -v2 150; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 151; SI-SDAG-NEXT: v_fma_f32 v0, s6, v1, v0 152; SI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0 153; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 154; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v3 155; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 156; SI-SDAG-NEXT: s_mov_b32 s2, -1 157; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 158; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc23369f4 159; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s6, v1 160; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x421a209b 161; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 162; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s6, v1 163; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 164; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0 165; SI-SDAG-NEXT: s_endpgm 166; 167; SI-GISEL-LABEL: s_exp10_f32: 168; SI-GISEL: ; %bb.0: 169; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb 170; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 171; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78 172; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37 173; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 174; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 175; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0 176; SI-GISEL-NEXT: v_fma_f32 v0, s2, v0, -v2 177; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 178; SI-GISEL-NEXT: v_fma_f32 v0, s2, v1, v0 179; SI-GISEL-NEXT: v_sub_f32_e32 v1, v2, v3 180; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0 181; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v3 182; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 183; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 184; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2 185; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 186; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 187; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b 188; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 189; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v1 190; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 191; SI-GISEL-NEXT: s_mov_b32 s2, -1 192; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0 193; SI-GISEL-NEXT: s_endpgm 194; 195; R600-LABEL: s_exp10_f32: 196; R600: ; %bb.0: 197; R600-NEXT: ALU 59, @4, KC0[CB0:0-32], KC1[] 198; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 199; R600-NEXT: CF_END 200; R600-NEXT: PAD 201; R600-NEXT: ALU clause starting at 4: 202; R600-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x, 203; R600-NEXT: -4096(nan), 0(0.000000e+00) 204; R600-NEXT: ADD T1.W, KC0[2].Z, -PV.W, 205; R600-NEXT: MUL_IEEE * T2.W, PV.W, literal.x, 206; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 207; R600-NEXT: RNDNE T3.W, PS, 208; R600-NEXT: MUL_IEEE * T4.W, PV.W, literal.x, 209; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 210; R600-NEXT: MULADD_IEEE T1.W, T1.W, literal.x, PS, 211; R600-NEXT: TRUNC * T4.W, PV.W, 212; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 213; R600-NEXT: FLT_TO_INT T0.Z, PS, 214; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PV.W, 215; R600-NEXT: ADD * T1.W, T2.W, -T3.W, 216; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 217; R600-NEXT: ADD T1.Z, PS, PV.W, 218; R600-NEXT: MAX_INT T0.W, PV.Z, literal.x, 219; R600-NEXT: MIN_INT * T1.W, PV.Z, literal.y, 220; R600-NEXT: -330(nan), 381(5.338947e-43) 221; R600-NEXT: ADD_INT T0.X, PS, literal.x, 222; R600-NEXT: ADD_INT T0.Y, PV.W, literal.y, 223; R600-NEXT: ADD_INT T2.Z, T0.Z, literal.z, 224; R600-NEXT: SETGT_UINT T0.W, T0.Z, literal.w, 225; R600-NEXT: EXP_IEEE * T1.X, PV.Z, 226; R600-NEXT: -254(nan), 204(2.858649e-43) 227; R600-NEXT: 102(1.429324e-43), -229(nan) 228; R600-NEXT: ADD_INT T2.X, T0.Z, literal.x, 229; R600-NEXT: SETGT_UINT T1.Y, T0.Z, literal.y, 230; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z, 231; R600-NEXT: SETGT_INT T1.W, T0.Z, literal.x, 232; R600-NEXT: MUL_IEEE * T2.W, PS, literal.z, 233; R600-NEXT: -127(nan), 254(3.559298e-43) 234; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 235; R600-NEXT: MUL_IEEE T3.X, PS, literal.x, 236; R600-NEXT: MUL_IEEE T0.Y, T1.X, literal.y, 237; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Z, T0.Z, 238; R600-NEXT: CNDE_INT T3.W, PV.Y, PV.X, T0.X, 239; R600-NEXT: SETGT_INT * T4.W, T0.Z, literal.z, 240; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38) 241; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00) 242; R600-NEXT: CNDE_INT T0.Z, PS, PV.Z, PV.W, 243; R600-NEXT: MUL_IEEE T3.W, PV.Y, literal.x, 244; R600-NEXT: CNDE_INT * T0.W, T0.W, PV.X, T2.W, 245; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 246; R600-NEXT: CNDE_INT T1.Z, T1.W, PS, T1.X, 247; R600-NEXT: CNDE_INT T0.W, T1.Y, T0.Y, PV.W, 248; R600-NEXT: LSHL * T1.W, PV.Z, literal.x, 249; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00) 250; R600-NEXT: ADD_INT T1.W, PS, literal.x, 251; R600-NEXT: CNDE_INT * T0.W, T4.W, PV.Z, PV.W, 252; R600-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00) 253; R600-NEXT: MUL_IEEE T0.W, PS, PV.W, 254; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].Z, 255; R600-NEXT: -1036817932(-4.485347e+01), 0(0.000000e+00) 256; R600-NEXT: CNDE T0.W, PS, PV.W, 0.0, 257; R600-NEXT: SETGT * T1.W, KC0[2].Z, literal.x, 258; R600-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00) 259; R600-NEXT: CNDE T0.X, PS, PV.W, literal.x, 260; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 261; R600-NEXT: 2139095040(INF), 2(2.802597e-45) 262; 263; CM-LABEL: s_exp10_f32: 264; CM: ; %bb.0: 265; CM-NEXT: ALU 62, @4, KC0[CB0:0-32], KC1[] 266; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X 267; CM-NEXT: CF_END 268; CM-NEXT: PAD 269; CM-NEXT: ALU clause starting at 4: 270; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x, 271; CM-NEXT: -4096(nan), 0(0.000000e+00) 272; CM-NEXT: ADD * T1.W, KC0[2].Z, -PV.W, 273; CM-NEXT: MUL_IEEE T0.Z, PV.W, literal.x, 274; CM-NEXT: MUL_IEEE * T2.W, T0.W, literal.y, 275; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 276; CM-NEXT: RNDNE T1.Z, PV.W, 277; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Z, 278; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 279; CM-NEXT: MULADD_IEEE T0.Z, T0.W, literal.x, PV.W, 280; CM-NEXT: ADD * T0.W, T2.W, -PV.Z, BS:VEC_120/SCL_212 281; CM-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 282; CM-NEXT: TRUNC T1.Z, T1.Z, 283; CM-NEXT: ADD * T0.W, PV.W, PV.Z, 284; CM-NEXT: EXP_IEEE T0.X, T0.W, 285; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W, 286; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W, 287; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W, 288; CM-NEXT: FLT_TO_INT T0.Z, T1.Z, 289; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x, 290; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 291; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, 292; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.y, 293; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z, 294; CM-NEXT: 209715200(1.972152e-31), -330(nan) 295; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00) 296; CM-NEXT: ADD_INT T1.X, PV.W, literal.x, 297; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.y, 298; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z, 299; CM-NEXT: SETGT_UINT * T1.W, T0.Z, literal.w, 300; CM-NEXT: -254(nan), 204(2.858649e-43) 301; CM-NEXT: 102(1.429324e-43), -229(nan) 302; CM-NEXT: ADD_INT T2.X, T0.Z, literal.x, 303; CM-NEXT: SETGT_UINT T2.Y, T0.Z, literal.y, 304; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z, 305; CM-NEXT: SETGT_INT * T2.W, T0.Z, literal.x, 306; CM-NEXT: -127(nan), 254(3.559298e-43) 307; CM-NEXT: MUL_IEEE T3.X, T0.X, literal.x, 308; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, T0.Z, 309; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.X, 310; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.y, 311; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43) 312; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Y, PV.Z, 313; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.x, 314; CM-NEXT: CNDE_INT * T0.W, T1.W, T0.Y, T0.W, 315; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 316; CM-NEXT: CNDE_INT T0.Y, T2.W, PV.W, T0.X, 317; CM-NEXT: CNDE_INT T0.Z, T2.Y, T3.X, PV.Z, 318; CM-NEXT: LSHL * T0.W, PV.Y, literal.x, 319; CM-NEXT: 23(3.222986e-44), 0(0.000000e+00) 320; CM-NEXT: ADD_INT T1.Z, PV.W, literal.x, 321; CM-NEXT: CNDE_INT * T0.W, T3.W, PV.Y, PV.Z, 322; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00) 323; CM-NEXT: MUL_IEEE T0.Z, PV.W, PV.Z, 324; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z, 325; CM-NEXT: -1036817932(-4.485347e+01), 0(0.000000e+00) 326; CM-NEXT: CNDE T0.Z, PV.W, PV.Z, 0.0, 327; CM-NEXT: SETGT * T0.W, KC0[2].Z, literal.x, 328; CM-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00) 329; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x, 330; CM-NEXT: 2139095040(INF), 0(0.000000e+00) 331; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 332; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 333 %result = call float @llvm.exp10.f32(float %in) 334 store float %result, ptr addrspace(1) %out 335 ret void 336} 337 338; FIXME: We should be able to merge these packets together on Cayman so we 339; have a maximum of 4 instructions. 340define amdgpu_kernel void @s_exp10_v2f32(ptr addrspace(1) %out, <2 x float> %in) { 341; VI-SDAG-LABEL: s_exp10_v2f32: 342; VI-SDAG: ; %bb.0: 343; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 344; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549000 345; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 346; VI-SDAG-NEXT: s_and_b32 s4, s3, 0xfffff000 347; VI-SDAG-NEXT: v_mov_b32_e32 v2, s4 348; VI-SDAG-NEXT: v_sub_f32_e32 v2, s3, v2 349; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 350; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 351; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 352; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x3a2784bc 353; VI-SDAG-NEXT: v_mul_f32_e32 v1, s4, v0 354; VI-SDAG-NEXT: v_mul_f32_e32 v5, s4, v4 355; VI-SDAG-NEXT: s_and_b32 s4, s2, 0xfffff000 356; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 357; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4 358; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 359; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v2 360; VI-SDAG-NEXT: v_sub_f32_e32 v6, s2, v6 361; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 362; VI-SDAG-NEXT: v_mul_f32_e32 v0, s4, v0 363; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v6 364; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x40549000, v6 365; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 366; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 367; VI-SDAG-NEXT: v_rndne_f32_e32 v5, v0 368; VI-SDAG-NEXT: v_add_f32_e32 v6, v6, v7 369; VI-SDAG-NEXT: v_mul_f32_e32 v4, s4, v4 370; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v5 371; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v6 372; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v4 373; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 374; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v5 375; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 376; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0xc23369f4 377; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v2 378; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x421a209b 379; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 380; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x7f800000 381; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v3 382; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 383; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v4 384; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v2 385; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 386; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3 387; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1 388; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc 389; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0 390; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1] 391; VI-SDAG-NEXT: s_endpgm 392; 393; VI-GISEL-LABEL: s_exp10_v2f32: 394; VI-GISEL: ; %bb.0: 395; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 396; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549000 397; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3a2784bc 398; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 399; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000 400; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4 401; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2 402; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 403; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 404; VI-GISEL-NEXT: v_mul_f32_e32 v3, s4, v0 405; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 406; VI-GISEL-NEXT: v_mul_f32_e32 v4, s4, v1 407; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000 408; VI-GISEL-NEXT: v_mov_b32_e32 v5, s4 409; VI-GISEL-NEXT: v_add_f32_e32 v2, v4, v2 410; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3 411; VI-GISEL-NEXT: v_sub_f32_e32 v5, s3, v5 412; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 413; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3a2784bc, v5 414; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x40549000, v5 415; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 416; VI-GISEL-NEXT: v_mul_f32_e32 v0, s4, v0 417; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 418; VI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v1 419; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 420; VI-GISEL-NEXT: v_exp_f32_e32 v2, v2 421; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5 422; VI-GISEL-NEXT: v_rndne_f32_e32 v5, v0 423; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 424; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 425; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v5 426; VI-GISEL-NEXT: v_exp_f32_e32 v5, v0 427; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3 428; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4 429; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3 430; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b 431; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc 432; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000 433; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4 434; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc 435; VI-GISEL-NEXT: v_ldexp_f32 v1, v5, v1 436; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v3 437; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 438; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v4 439; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1 440; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc 441; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0 442; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] 443; VI-GISEL-NEXT: s_endpgm 444; 445; GFX900-SDAG-LABEL: s_exp10_v2f32: 446; GFX900-SDAG: ; %bb.0: 447; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 448; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 449; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 450; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0xc23369f4 451; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) 452; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0 453; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v2 454; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v2 455; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 456; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v1, v4 457; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s2, v0 458; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 459; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v6 460; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v6 461; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3 462; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2 463; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v6, v7 464; GFX900-SDAG-NEXT: v_fma_f32 v0, s2, v1, v0 465; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v8, v0 466; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 467; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v7 468; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v3 469; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v5 470; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x421a209b 471; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 472; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x7f800000 473; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v3 474; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc 475; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v6 476; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v5 477; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 478; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v3 479; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 480; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc 481; GFX900-SDAG-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] 482; GFX900-SDAG-NEXT: s_endpgm 483; 484; GFX900-GISEL-LABEL: s_exp10_v2f32: 485; GFX900-GISEL: ; %bb.0: 486; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 487; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78 488; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37 489; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000 490; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) 491; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0 492; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2 493; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v2 494; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0 495; GFX900-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3 496; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4 497; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5 498; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 499; GFX900-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0 500; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v5 501; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 502; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2 503; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1 504; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v5, v0 505; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 506; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v0 507; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4 508; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3 509; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4 510; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b 511; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc 512; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3 513; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc 514; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v5, v1 515; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4 516; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 517; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3 518; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc 519; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 520; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] 521; GFX900-GISEL-NEXT: s_endpgm 522; 523; SI-SDAG-LABEL: s_exp10_v2f32: 524; SI-SDAG: ; %bb.0: 525; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 526; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 527; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 528; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000 529; SI-SDAG-NEXT: s_mov_b32 s6, -1 530; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 531; SI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0 532; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 533; SI-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v2 534; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 535; SI-SDAG-NEXT: v_fma_f32 v4, s3, v1, v4 536; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 537; SI-SDAG-NEXT: v_mul_f32_e32 v5, s2, v0 538; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 539; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3 540; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v5 541; SI-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v5 542; SI-SDAG-NEXT: v_sub_f32_e32 v7, v5, v6 543; SI-SDAG-NEXT: v_fma_f32 v0, s2, v1, v0 544; SI-SDAG-NEXT: v_add_f32_e32 v0, v7, v0 545; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 546; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v5, v6 547; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v3 548; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f4 549; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v3 550; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x421a209b 551; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 552; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x7f800000 553; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v4 554; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc 555; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v5 556; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v3 557; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 558; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v4 559; SI-SDAG-NEXT: s_mov_b32 s4, s0 560; SI-SDAG-NEXT: s_mov_b32 s5, s1 561; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc 562; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 563; SI-SDAG-NEXT: s_endpgm 564; 565; SI-GISEL-LABEL: s_exp10_v2f32: 566; SI-GISEL: ; %bb.0: 567; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 568; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78 569; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x33979a37 570; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000 571; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 572; SI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v0 573; SI-GISEL-NEXT: v_fma_f32 v3, s2, v0, -v2 574; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v2 575; SI-GISEL-NEXT: v_mul_f32_e32 v5, s3, v0 576; SI-GISEL-NEXT: v_fma_f32 v3, s2, v1, v3 577; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4 578; SI-GISEL-NEXT: v_fma_f32 v0, s3, v0, -v5 579; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 580; SI-GISEL-NEXT: v_fma_f32 v0, s3, v1, v0 581; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v5 582; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 583; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2 584; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v1 585; SI-GISEL-NEXT: v_add_f32_e32 v0, v5, v0 586; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 587; SI-GISEL-NEXT: v_exp_f32_e32 v5, v0 588; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4 589; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3 590; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4 591; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b 592; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc 593; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3 594; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc 595; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v5, v1 596; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4 597; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 598; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v3 599; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc 600; SI-GISEL-NEXT: s_mov_b32 s2, -1 601; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 602; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 603; SI-GISEL-NEXT: s_endpgm 604; 605; R600-LABEL: s_exp10_v2f32: 606; R600: ; %bb.0: 607; R600-NEXT: ALU 96, @4, KC0[CB0:0-32], KC1[] 608; R600-NEXT: ALU 12, @101, KC0[CB0:0-32], KC1[] 609; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1 610; R600-NEXT: CF_END 611; R600-NEXT: ALU clause starting at 4: 612; R600-NEXT: AND_INT * T0.W, KC0[3].X, literal.x, 613; R600-NEXT: -4096(nan), 0(0.000000e+00) 614; R600-NEXT: ADD * T1.W, KC0[3].X, -PV.W, 615; R600-NEXT: MUL_IEEE T2.W, PV.W, literal.x, 616; R600-NEXT: MUL_IEEE * T3.W, T0.W, literal.y, 617; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 618; R600-NEXT: RNDNE T0.Z, PS, 619; R600-NEXT: MULADD_IEEE T1.W, T1.W, literal.x, PV.W, 620; R600-NEXT: AND_INT * T2.W, KC0[2].W, literal.y, 621; R600-NEXT: 1079283712(3.321289e+00), -4096(nan) 622; R600-NEXT: ADD T1.Z, KC0[2].W, -PS, 623; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PV.W, 624; R600-NEXT: ADD * T1.W, T3.W, -PV.Z, 625; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 626; R600-NEXT: ADD T2.Z, PS, PV.W, 627; R600-NEXT: MUL_IEEE T0.W, PV.Z, literal.x, 628; R600-NEXT: MUL_IEEE * T1.W, T2.W, literal.y, 629; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 630; R600-NEXT: RNDNE T0.Y, PS, 631; R600-NEXT: MULADD_IEEE T1.Z, T1.Z, literal.x, PV.W, 632; R600-NEXT: TRUNC T0.W, T0.Z, BS:VEC_120/SCL_212 633; R600-NEXT: EXP_IEEE * T0.X, PV.Z, 634; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 635; R600-NEXT: FLT_TO_INT T1.Y, PV.W, 636; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x, 637; R600-NEXT: MULADD_IEEE T0.W, T2.W, literal.y, PV.Z, 638; R600-NEXT: ADD * T1.W, T1.W, -PV.Y, 639; R600-NEXT: 209715200(1.972152e-31), 975668412(6.390323e-04) 640; R600-NEXT: ADD T1.Z, PS, PV.W, 641; R600-NEXT: MUL_IEEE T0.W, PV.Z, literal.x, 642; R600-NEXT: SETGT_UINT * T1.W, PV.Y, literal.y, 643; R600-NEXT: 209715200(1.972152e-31), -229(nan) 644; R600-NEXT: CNDE_INT T0.Z, PS, PV.W, T0.Z, 645; R600-NEXT: SETGT_INT T0.W, T1.Y, literal.x, 646; R600-NEXT: EXP_IEEE * T1.X, PV.Z, 647; R600-NEXT: -127(nan), 0(0.000000e+00) 648; R600-NEXT: CNDE_INT T0.Z, PV.W, PV.Z, T0.X, 649; R600-NEXT: MAX_INT T2.W, T1.Y, literal.x, 650; R600-NEXT: MUL_IEEE * T3.W, PS, literal.y, 651; R600-NEXT: -330(nan), 209715200(1.972152e-31) 652; R600-NEXT: MUL_IEEE T2.X, PS, literal.x, 653; R600-NEXT: ADD_INT T2.Y, PV.W, literal.y, 654; R600-NEXT: ADD_INT T1.Z, T1.Y, literal.z, 655; R600-NEXT: MIN_INT T2.W, T1.Y, literal.w, 656; R600-NEXT: TRUNC * T4.W, T0.Y, 657; R600-NEXT: 209715200(1.972152e-31), 204(2.858649e-43) 658; R600-NEXT: 102(1.429324e-43), 381(5.338947e-43) 659; R600-NEXT: FLT_TO_INT T3.X, PS, 660; R600-NEXT: ADD_INT T0.Y, PV.W, literal.x, 661; R600-NEXT: ADD_INT T2.Z, T1.Y, literal.y, 662; R600-NEXT: SETGT_UINT T2.W, T1.Y, literal.z, 663; R600-NEXT: CNDE_INT * T1.W, T1.W, PV.Y, PV.Z, 664; R600-NEXT: -254(nan), -127(nan) 665; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00) 666; R600-NEXT: MUL_IEEE T4.X, T1.X, literal.x, 667; R600-NEXT: MUL_IEEE T2.Y, T0.X, literal.x, BS:VEC_120/SCL_212 668; R600-NEXT: CNDE_INT T1.Z, T0.W, PS, T1.Y, 669; R600-NEXT: CNDE_INT T0.W, PV.W, PV.Z, PV.Y, 670; R600-NEXT: MAX_INT * T1.W, PV.X, literal.y, 671; R600-NEXT: 2130706432(1.701412e+38), -330(nan) 672; R600-NEXT: SETGT_INT T0.X, T1.Y, literal.x, 673; R600-NEXT: ADD_INT T0.Y, PS, literal.y, 674; R600-NEXT: ADD_INT T2.Z, T3.X, literal.z, 675; R600-NEXT: SETGT_UINT * T1.W, T3.X, literal.w, 676; R600-NEXT: 127(1.779649e-43), 204(2.858649e-43) 677; R600-NEXT: 102(1.429324e-43), -229(nan) 678; R600-NEXT: MIN_INT * T4.W, T3.X, literal.x, 679; R600-NEXT: 381(5.338947e-43), 0(0.000000e+00) 680; R600-NEXT: ADD_INT T5.X, PV.W, literal.x, 681; R600-NEXT: ADD_INT T1.Y, T3.X, literal.y, 682; R600-NEXT: SETGT_UINT T3.Z, T3.X, literal.z, 683; R600-NEXT: CNDE_INT T4.W, T1.W, T0.Y, T2.Z, 684; R600-NEXT: SETGT_INT * T5.W, T3.X, literal.y, 685; R600-NEXT: -254(nan), -127(nan) 686; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00) 687; R600-NEXT: CNDE_INT T6.X, PS, PV.W, T3.X, 688; R600-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, PV.X, 689; R600-NEXT: SETGT_INT T2.Z, T3.X, literal.x, 690; R600-NEXT: CNDE_INT T0.W, T0.X, T1.Z, T0.W, BS:VEC_120/SCL_212 691; R600-NEXT: MUL_IEEE * T4.W, T2.Y, literal.y, 692; R600-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38) 693; R600-NEXT: CNDE_INT T3.X, T2.W, T2.Y, PS, BS:VEC_120/SCL_212 694; R600-NEXT: LSHL T1.Y, PV.W, literal.x, 695; R600-NEXT: CNDE_INT T1.Z, PV.Z, PV.X, PV.Y, 696; R600-NEXT: MUL_IEEE T0.W, T4.X, literal.y, 697; R600-NEXT: CNDE_INT * T1.W, T1.W, T2.X, T3.W, 698; R600-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38) 699; R600-NEXT: CNDE_INT T1.X, T5.W, PS, T1.X, BS:VEC_021/SCL_122 700; R600-NEXT: CNDE_INT T0.Y, T3.Z, T4.X, PV.W, BS:VEC_201 701; R600-NEXT: LSHL T1.Z, PV.Z, literal.x, 702; R600-NEXT: ADD_INT T0.W, PV.Y, literal.y, 703; R600-NEXT: CNDE_INT * T1.W, T0.X, T0.Z, PV.X, 704; R600-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00) 705; R600-NEXT: MUL_IEEE T1.Y, PS, PV.W, 706; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].X, 707; R600-NEXT: ADD_INT * T0.W, PV.Z, literal.y, 708; R600-NEXT: -1036817932(-4.485347e+01), 1065353216(1.000000e+00) 709; R600-NEXT: ALU clause starting at 101: 710; R600-NEXT: CNDE_INT * T1.W, T2.Z, T1.X, T0.Y, 711; R600-NEXT: MUL_IEEE T0.Y, PV.W, T0.W, 712; R600-NEXT: SETGT T1.Z, literal.x, KC0[2].W, 713; R600-NEXT: CNDE T0.W, T0.Z, T1.Y, 0.0, 714; R600-NEXT: SETGT * T1.W, KC0[3].X, literal.y, 715; R600-NEXT: -1036817932(-4.485347e+01), 1109008539(3.853184e+01) 716; R600-NEXT: CNDE T1.Y, PS, PV.W, literal.x, 717; R600-NEXT: CNDE T0.W, PV.Z, PV.Y, 0.0, 718; R600-NEXT: SETGT * T1.W, KC0[2].W, literal.y, 719; R600-NEXT: 2139095040(INF), 1109008539(3.853184e+01) 720; R600-NEXT: CNDE T1.X, PS, PV.W, literal.x, 721; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.y, 722; R600-NEXT: 2139095040(INF), 2(2.802597e-45) 723; 724; CM-LABEL: s_exp10_v2f32: 725; CM: ; %bb.0: 726; CM-NEXT: ALU 98, @4, KC0[CB0:0-32], KC1[] 727; CM-NEXT: ALU 18, @103, KC0[CB0:0-32], KC1[] 728; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X 729; CM-NEXT: CF_END 730; CM-NEXT: ALU clause starting at 4: 731; CM-NEXT: AND_INT * T0.W, KC0[2].W, literal.x, 732; CM-NEXT: -4096(nan), 0(0.000000e+00) 733; CM-NEXT: ADD * T1.W, KC0[2].W, -PV.W, 734; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, 735; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y, 736; CM-NEXT: AND_INT * T2.W, KC0[3].X, literal.z, 737; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 738; CM-NEXT: -4096(nan), 0(0.000000e+00) 739; CM-NEXT: ADD T1.Y, KC0[3].X, -PV.W, 740; CM-NEXT: RNDNE T1.Z, PV.Z, 741; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Y, 742; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 743; CM-NEXT: MULADD_IEEE T0.X, T0.W, literal.x, PV.W, 744; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z, 745; CM-NEXT: MUL_IEEE T0.Z, PV.Y, literal.x, 746; CM-NEXT: MUL_IEEE * T0.W, T2.W, literal.y, BS:VEC_120/SCL_212 747; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 748; CM-NEXT: TRUNC T1.X, T1.Z, 749; CM-NEXT: RNDNE T2.Y, PV.W, 750; CM-NEXT: MULADD_IEEE T0.Z, T1.Y, literal.x, PV.Z, 751; CM-NEXT: ADD * T1.W, PV.Y, PV.X, 752; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 753; CM-NEXT: EXP_IEEE T0.X, T1.W, 754; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W, 755; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W, 756; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W, 757; CM-NEXT: MULADD_IEEE T2.X, T2.W, literal.x, T0.Z, 758; CM-NEXT: ADD T0.Y, T0.W, -T2.Y, BS:VEC_120/SCL_212 759; CM-NEXT: FLT_TO_INT T0.Z, T1.X, 760; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y, 761; CM-NEXT: 975668412(6.390323e-04), 209715200(1.972152e-31) 762; CM-NEXT: MUL_IEEE T1.X, PV.W, literal.x, 763; CM-NEXT: SETGT_UINT T1.Y, PV.Z, literal.y, 764; CM-NEXT: TRUNC T1.Z, T2.Y, 765; CM-NEXT: ADD * T1.W, PV.Y, PV.X, 766; CM-NEXT: 209715200(1.972152e-31), -229(nan) 767; CM-NEXT: EXP_IEEE T0.X (MASKED), T1.W, 768; CM-NEXT: EXP_IEEE T0.Y, T1.W, 769; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W, 770; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W, 771; CM-NEXT: FLT_TO_INT T2.X, T1.Z, 772; CM-NEXT: MUL_IEEE T2.Y, PV.Y, literal.x, 773; CM-NEXT: CNDE_INT T1.Z, T1.Y, T1.X, T0.W, 774; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y, BS:VEC_120/SCL_212 775; CM-NEXT: 209715200(1.972152e-31), -127(nan) 776; CM-NEXT: CNDE_INT T1.X, PV.W, PV.Z, T0.X, 777; CM-NEXT: MUL_IEEE T3.Y, PV.Y, literal.x, 778; CM-NEXT: SETGT_UINT T1.Z, PV.X, literal.y, 779; CM-NEXT: MAX_INT * T1.W, T0.Z, literal.z, 780; CM-NEXT: 209715200(1.972152e-31), -229(nan) 781; CM-NEXT: -330(nan), 0(0.000000e+00) 782; CM-NEXT: ADD_INT T3.X, PV.W, literal.x, 783; CM-NEXT: ADD_INT T4.Y, T0.Z, literal.y, 784; CM-NEXT: CNDE_INT T2.Z, PV.Z, PV.Y, T2.Y, 785; CM-NEXT: SETGT_INT * T1.W, T2.X, literal.z, 786; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43) 787; CM-NEXT: -127(nan), 0(0.000000e+00) 788; CM-NEXT: CNDE_INT T4.X, PV.W, PV.Z, T0.Y, 789; CM-NEXT: MUL_IEEE T2.Y, T0.X, literal.x, 790; CM-NEXT: MAX_INT T2.Z, T2.X, literal.y, BS:VEC_120/SCL_212 791; CM-NEXT: CNDE_INT * T2.W, T1.Y, PV.X, PV.Y, 792; CM-NEXT: 2130706432(1.701412e+38), -330(nan) 793; CM-NEXT: CNDE_INT T0.X, T0.W, PV.W, T0.Z, 794; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.x, 795; CM-NEXT: ADD_INT T2.Z, T2.X, literal.y, 796; CM-NEXT: MIN_INT * T0.W, T2.X, literal.z, 797; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43) 798; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00) 799; CM-NEXT: ADD_INT T3.X, PV.W, literal.x, 800; CM-NEXT: ADD_INT T3.Y, T2.X, literal.y, 801; CM-NEXT: SETGT_UINT T3.Z, T2.X, literal.z, 802; CM-NEXT: CNDE_INT * T0.W, T1.Z, PV.Y, PV.Z, 803; CM-NEXT: -254(nan), -127(nan) 804; CM-NEXT: 254(3.559298e-43), 0(0.000000e+00) 805; CM-NEXT: MUL_IEEE T5.X, T0.Y, literal.x, 806; CM-NEXT: CNDE_INT T0.Y, T1.W, PV.W, T2.X, 807; CM-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, PV.X, 808; CM-NEXT: MIN_INT * T0.W, T0.Z, literal.y, 809; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43) 810; CM-NEXT: SETGT_INT T2.X, T2.X, literal.x, 811; CM-NEXT: ADD_INT T1.Y, PV.W, literal.y, 812; CM-NEXT: ADD_INT T2.Z, T0.Z, literal.z, 813; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.w, 814; CM-NEXT: 127(1.779649e-43), -254(nan) 815; CM-NEXT: -127(nan), 254(3.559298e-43) 816; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, PV.Y, 817; CM-NEXT: SETGT_INT T1.Y, T0.Z, literal.x, 818; CM-NEXT: CNDE_INT T0.Z, PV.X, T0.Y, T1.Z, 819; CM-NEXT: MUL_IEEE * T1.W, T5.X, literal.y, 820; CM-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38) 821; CM-NEXT: CNDE_INT T5.X, T3.Z, T5.X, PV.W, 822; CM-NEXT: LSHL T0.Y, PV.Z, literal.x, 823; CM-NEXT: CNDE_INT T0.Z, PV.Y, T0.X, PV.X, BS:VEC_021/SCL_122 824; CM-NEXT: MUL_IEEE * T1.W, T2.Y, literal.y, 825; CM-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38) 826; CM-NEXT: CNDE_INT T0.X, T0.W, T2.Y, PV.W, 827; CM-NEXT: LSHL T2.Y, PV.Z, literal.x, 828; CM-NEXT: ADD_INT * T0.Z, PV.Y, literal.y, 829; CM-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00) 830; CM-NEXT: ALU clause starting at 103: 831; CM-NEXT: CNDE_INT * T0.W, T2.X, T4.X, T5.X, 832; CM-NEXT: MUL_IEEE T2.X, PV.W, T0.Z, 833; CM-NEXT: SETGT T0.Y, literal.x, KC0[3].X, 834; CM-NEXT: ADD_INT T0.Z, T2.Y, literal.y, 835; CM-NEXT: CNDE_INT * T0.W, T1.Y, T1.X, T0.X, BS:VEC_120/SCL_212 836; CM-NEXT: -1036817932(-4.485347e+01), 1065353216(1.000000e+00) 837; CM-NEXT: MUL_IEEE T0.X, PV.W, PV.Z, 838; CM-NEXT: SETGT T1.Y, literal.x, KC0[2].W, 839; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0, 840; CM-NEXT: SETGT * T0.W, KC0[3].X, literal.y, 841; CM-NEXT: -1036817932(-4.485347e+01), 1109008539(3.853184e+01) 842; CM-NEXT: CNDE T0.Y, PV.W, PV.Z, literal.x, 843; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0, 844; CM-NEXT: SETGT * T0.W, KC0[2].W, literal.y, 845; CM-NEXT: 2139095040(INF), 1109008539(3.853184e+01) 846; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x, 847; CM-NEXT: 2139095040(INF), 0(0.000000e+00) 848; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 849; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 850 %result = call <2 x float> @llvm.exp10.v2f32(<2 x float> %in) 851 store <2 x float> %result, ptr addrspace(1) %out 852 ret void 853} 854 855define amdgpu_kernel void @s_exp10_v3f32(ptr addrspace(1) %out, <3 x float> %in) { 856; VI-SDAG-LABEL: s_exp10_v3f32: 857; VI-SDAG: ; %bb.0: 858; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 859; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549000 860; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 861; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 862; VI-SDAG-NEXT: s_and_b32 s3, s2, 0xfffff000 863; VI-SDAG-NEXT: v_mov_b32_e32 v2, s3 864; VI-SDAG-NEXT: v_sub_f32_e32 v2, s2, v2 865; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 866; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 867; VI-SDAG-NEXT: v_mul_f32_e32 v1, s3, v0 868; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 869; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x3a2784bc 870; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 871; VI-SDAG-NEXT: v_mul_f32_e32 v5, s3, v4 872; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 873; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v2 874; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 875; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 876; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 877; VI-SDAG-NEXT: s_and_b32 s3, s1, 0xfffff000 878; VI-SDAG-NEXT: v_mov_b32_e32 v7, s3 879; VI-SDAG-NEXT: v_sub_f32_e32 v7, s1, v7 880; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 881; VI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0 882; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3a2784bc, v7 883; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x40549000, v7 884; VI-SDAG-NEXT: v_rndne_f32_e32 v6, v2 885; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v8 886; VI-SDAG-NEXT: v_mul_f32_e32 v8, s3, v4 887; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6 888; VI-SDAG-NEXT: v_add_f32_e32 v7, v8, v7 889; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v7 890; VI-SDAG-NEXT: v_exp_f32_e32 v7, v2 891; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v6 892; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f4 893; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v3 894; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x421a209b 895; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 896; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f800000 897; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v5 898; VI-SDAG-NEXT: s_and_b32 s2, s0, 0xfffff000 899; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc 900; VI-SDAG-NEXT: v_ldexp_f32 v1, v7, v6 901; VI-SDAG-NEXT: v_mov_b32_e32 v7, s2 902; VI-SDAG-NEXT: v_sub_f32_e32 v7, s0, v7 903; VI-SDAG-NEXT: v_mul_f32_e32 v0, s2, v0 904; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v7 905; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x40549000, v7 906; VI-SDAG-NEXT: v_rndne_f32_e32 v6, v0 907; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v9 908; VI-SDAG-NEXT: v_mul_f32_e32 v4, s2, v4 909; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v6 910; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v7 911; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v4 912; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 913; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v6 914; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v3 915; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 916; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v5 917; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 918; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v4 919; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v3 920; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 921; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v5 922; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4 923; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 924; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5 925; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2] 926; VI-SDAG-NEXT: s_endpgm 927; 928; VI-GISEL-LABEL: s_exp10_v3f32: 929; VI-GISEL: ; %bb.0: 930; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 931; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549000 932; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3a2784bc 933; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 934; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 935; VI-GISEL-NEXT: s_and_b32 s3, s0, 0xfffff000 936; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3 937; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0 938; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0 939; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 940; VI-GISEL-NEXT: v_mul_f32_e32 v3, s3, v1 941; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4 942; VI-GISEL-NEXT: v_mul_f32_e32 v4, s3, v2 943; VI-GISEL-NEXT: s_and_b32 s3, s1, 0xfffff000 944; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3 945; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0 946; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v3 947; VI-GISEL-NEXT: v_sub_f32_e32 v5, s1, v5 948; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 949; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v5 950; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x40549000, v5 951; VI-GISEL-NEXT: v_add_f32_e32 v0, v3, v0 952; VI-GISEL-NEXT: v_mul_f32_e32 v6, s3, v1 953; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7 954; VI-GISEL-NEXT: v_mul_f32_e32 v7, s3, v2 955; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 956; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 957; VI-GISEL-NEXT: v_add_f32_e32 v5, v7, v5 958; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6 959; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7 960; VI-GISEL-NEXT: v_add_f32_e32 v5, v6, v5 961; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7 962; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5 963; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v3 964; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4 965; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v3 966; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b 967; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 968; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v4 969; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000 970; VI-GISEL-NEXT: v_ldexp_f32 v5, v5, v6 971; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0 972; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6 973; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3a2784bc, v6 974; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x40549000, v6 975; VI-GISEL-NEXT: v_mul_f32_e32 v1, s0, v1 976; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8 977; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2 978; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6 979; VI-GISEL-NEXT: v_rndne_f32_e32 v6, v1 980; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6 981; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 982; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v6 983; VI-GISEL-NEXT: v_exp_f32_e32 v6, v1 984; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000 985; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc 986; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v3 987; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc 988; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v4 989; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc 990; VI-GISEL-NEXT: v_ldexp_f32 v2, v6, v2 991; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v3 992; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc 993; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v4 994; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4 995; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc 996; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 997; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2] 998; VI-GISEL-NEXT: s_endpgm 999; 1000; GFX900-SDAG-LABEL: s_exp10_v3f32: 1001; GFX900-SDAG: ; %bb.0: 1002; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 1003; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 1004; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 1005; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 1006; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0x421a209b 1007; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) 1008; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, s1, v0 1009; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v6 1010; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v6, v7 1011; GFX900-SDAG-NEXT: v_fma_f32 v6, s1, v0, -v6 1012; GFX900-SDAG-NEXT: v_fma_f32 v6, s1, v1, v6 1013; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s2, v0 1014; GFX900-SDAG-NEXT: v_add_f32_e32 v6, v8, v6 1015; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v2 1016; GFX900-SDAG-NEXT: v_fma_f32 v4, s2, v0, -v2 1017; GFX900-SDAG-NEXT: v_exp_f32_e32 v6, v6 1018; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v7 1019; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 1020; GFX900-SDAG-NEXT: v_fma_f32 v4, s2, v1, v4 1021; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 1022; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3 1023; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2 1024; GFX900-SDAG-NEXT: v_ldexp_f32 v6, v6, v7 1025; GFX900-SDAG-NEXT: v_mul_f32_e32 v7, s0, v0 1026; GFX900-SDAG-NEXT: v_rndne_f32_e32 v9, v7 1027; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v7 1028; GFX900-SDAG-NEXT: v_sub_f32_e32 v10, v7, v9 1029; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v1, v0 1030; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v3 1031; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f4 1032; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v10, v0 1033; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v3 1034; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 1035; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v9 1036; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 1037; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f800000 1038; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v5 1039; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc 1040; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v3 1041; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc 1042; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v5 1043; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 1044; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v7 1045; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v3 1046; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 1047; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v5 1048; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 1049; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 1050; GFX900-SDAG-NEXT: global_store_dwordx3 v4, v[0:2], s[6:7] 1051; GFX900-SDAG-NEXT: s_endpgm 1052; 1053; GFX900-GISEL-LABEL: s_exp10_v3f32: 1054; GFX900-GISEL: ; %bb.0: 1055; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 1056; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 1057; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 1058; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 1059; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) 1060; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s1, v1 1061; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v5 1062; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v5 1063; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, v6 1064; GFX900-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7 1065; GFX900-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 1066; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7 1067; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5 1068; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v1 1069; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v0 1070; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v0 1071; GFX900-GISEL-NEXT: v_fma_f32 v3, s0, v2, v3 1072; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 1073; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v3 1074; GFX900-GISEL-NEXT: v_ldexp_f32 v5, v5, v6 1075; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1 1076; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 1077; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 1078; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v6 1079; GFX900-GISEL-NEXT: v_fma_f32 v1, s2, v2, v1 1080; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v6 1081; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2 1082; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4 1083; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v6, v1 1084; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v3 1085; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4 1086; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b 1087; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 1088; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v1 1089; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1090; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000 1091; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3 1092; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc 1093; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4 1094; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc 1095; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3 1096; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc 1097; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v6, v2 1098; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4 1099; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc 1100; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3 1101; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc 1102; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 1103; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7] 1104; GFX900-GISEL-NEXT: s_endpgm 1105; 1106; SI-SDAG-LABEL: s_exp10_v3f32: 1107; SI-SDAG: ; %bb.0: 1108; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd 1109; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 1110; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x33979a37 1111; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 1112; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000 1113; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 1114; SI-SDAG-NEXT: v_mul_f32_e32 v5, s0, v0 1115; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v5 1116; SI-SDAG-NEXT: v_sub_f32_e32 v7, v5, v6 1117; SI-SDAG-NEXT: v_fma_f32 v5, s0, v0, -v5 1118; SI-SDAG-NEXT: v_fma_f32 v5, s0, v2, v5 1119; SI-SDAG-NEXT: v_mul_f32_e32 v1, s1, v0 1120; SI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5 1121; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 1122; SI-SDAG-NEXT: v_fma_f32 v4, s1, v0, -v1 1123; SI-SDAG-NEXT: v_exp_f32_e32 v5, v5 1124; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v6 1125; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 1126; SI-SDAG-NEXT: v_fma_f32 v4, s1, v2, v4 1127; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 1128; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 1129; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3 1130; SI-SDAG-NEXT: v_ldexp_f32_e32 v5, v5, v6 1131; SI-SDAG-NEXT: v_mul_f32_e32 v6, s2, v0 1132; SI-SDAG-NEXT: v_rndne_f32_e32 v8, v6 1133; SI-SDAG-NEXT: v_fma_f32 v0, s2, v0, -v6 1134; SI-SDAG-NEXT: v_sub_f32_e32 v9, v6, v8 1135; SI-SDAG-NEXT: v_fma_f32 v0, s2, v2, v0 1136; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v3 1137; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0xc23369f4 1138; SI-SDAG-NEXT: v_add_f32_e32 v0, v9, v0 1139; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v3 1140; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x421a209b 1141; SI-SDAG-NEXT: v_exp_f32_e32 v2, v0 1142; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v8 1143; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 1144; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x7f800000 1145; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v4 1146; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc 1147; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v3 1148; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc 1149; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v4 1150; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc 1151; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v6 1152; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v3 1153; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 1154; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v4 1155; SI-SDAG-NEXT: s_mov_b32 s6, -1 1156; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc 1157; SI-SDAG-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8 1158; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1159; SI-SDAG-NEXT: s_endpgm 1160; 1161; SI-GISEL-LABEL: s_exp10_v3f32: 1162; SI-GISEL: ; %bb.0: 1163; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd 1164; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 1165; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 1166; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 1167; SI-GISEL-NEXT: s_mov_b32 s6, -1 1168; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 1169; SI-GISEL-NEXT: v_mul_f32_e32 v5, s1, v1 1170; SI-GISEL-NEXT: v_fma_f32 v6, s1, v1, -v5 1171; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v5 1172; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, v6 1173; SI-GISEL-NEXT: v_sub_f32_e32 v5, v5, v7 1174; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 1175; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7 1176; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5 1177; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v1 1178; SI-GISEL-NEXT: v_fma_f32 v3, s0, v1, -v0 1179; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v0 1180; SI-GISEL-NEXT: v_fma_f32 v3, s0, v2, v3 1181; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 1182; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3 1183; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, v5, v6 1184; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v1 1185; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 1186; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 1187; SI-GISEL-NEXT: v_fma_f32 v1, s2, v1, -v6 1188; SI-GISEL-NEXT: v_fma_f32 v1, s2, v2, v1 1189; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v6 1190; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v2 1191; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4 1192; SI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1 1193; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v3 1194; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4 1195; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x421a209b 1196; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 1197; SI-GISEL-NEXT: v_exp_f32_e32 v6, v1 1198; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1199; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000 1200; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v3 1201; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc 1202; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4 1203; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, 0, vcc 1204; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v3 1205; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc 1206; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v6, v2 1207; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4 1208; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc 1209; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v3 1210; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 1211; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc 1212; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1213; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8 1214; SI-GISEL-NEXT: s_endpgm 1215; 1216; R600-LABEL: s_exp10_v3f32: 1217; R600: ; %bb.0: 1218; R600-NEXT: ALU 99, @6, KC0[CB0:0-32], KC1[] 1219; R600-NEXT: ALU 69, @106, KC0[CB0:0-32], KC1[] 1220; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0 1221; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1222; R600-NEXT: CF_END 1223; R600-NEXT: PAD 1224; R600-NEXT: ALU clause starting at 6: 1225; R600-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x, 1226; R600-NEXT: -4096(nan), 0(0.000000e+00) 1227; R600-NEXT: MUL_IEEE T1.W, PV.W, literal.x, 1228; R600-NEXT: ADD * T2.W, KC0[3].Y, -PV.W, 1229; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 1230; R600-NEXT: RNDNE * T3.W, PV.W, 1231; R600-NEXT: TRUNC T4.W, PV.W, 1232; R600-NEXT: MUL_IEEE * T5.W, T2.W, literal.x, 1233; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 1234; R600-NEXT: MULADD_IEEE T2.W, T2.W, literal.x, PS, 1235; R600-NEXT: FLT_TO_INT * T4.W, PV.W, 1236; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 1237; R600-NEXT: MAX_INT T0.Z, PS, literal.x, 1238; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.y, PV.W, 1239; R600-NEXT: ADD * T1.W, T1.W, -T3.W, 1240; R600-NEXT: -330(nan), 975668412(6.390323e-04) 1241; R600-NEXT: ADD T0.Y, PS, PV.W, 1242; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.x, 1243; R600-NEXT: ADD_INT T0.W, T4.W, literal.y, 1244; R600-NEXT: SETGT_UINT * T1.W, T4.W, literal.z, 1245; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43) 1246; R600-NEXT: -229(nan), 0(0.000000e+00) 1247; R600-NEXT: CNDE_INT T0.Z, PS, PV.Z, PV.W, 1248; R600-NEXT: SETGT_INT T0.W, T4.W, literal.x, 1249; R600-NEXT: EXP_IEEE * T0.X, PV.Y, 1250; R600-NEXT: -127(nan), 0(0.000000e+00) 1251; R600-NEXT: MUL_IEEE T1.X, PS, literal.x, 1252; R600-NEXT: CNDE_INT T0.Y, PV.W, PV.Z, T4.W, 1253; R600-NEXT: MIN_INT T0.Z, T4.W, literal.y, 1254; R600-NEXT: AND_INT T2.W, KC0[3].W, literal.z, 1255; R600-NEXT: MUL_IEEE * T3.W, PS, literal.w, 1256; R600-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43) 1257; R600-NEXT: -4096(nan), 209715200(1.972152e-31) 1258; R600-NEXT: MUL_IEEE T2.X, PS, literal.x, 1259; R600-NEXT: ADD T1.Y, KC0[3].W, -PV.W, 1260; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y, 1261; R600-NEXT: ADD_INT T5.W, T4.W, literal.z, 1262; R600-NEXT: SETGT_UINT * T6.W, T4.W, literal.w, 1263; R600-NEXT: 209715200(1.972152e-31), -254(nan) 1264; R600-NEXT: -127(nan), 254(3.559298e-43) 1265; R600-NEXT: CNDE_INT T3.X, PS, PV.W, PV.Z, 1266; R600-NEXT: SETGT_INT T2.Y, T4.W, literal.x, 1267; R600-NEXT: MUL_IEEE T0.Z, PV.Y, literal.y, 1268; R600-NEXT: MUL_IEEE * T4.W, T2.W, literal.z, BS:VEC_120/SCL_212 1269; R600-NEXT: 127(1.779649e-43), 975668412(6.390323e-04) 1270; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 1271; R600-NEXT: CNDE_INT * T1.W, T1.W, T2.X, T3.W, 1272; R600-NEXT: CNDE_INT T0.X, T0.W, PV.W, T0.X, BS:VEC_021/SCL_122 1273; R600-NEXT: RNDNE T3.Y, T4.W, BS:VEC_120/SCL_212 1274; R600-NEXT: MULADD_IEEE T0.Z, T1.Y, literal.x, T0.Z, 1275; R600-NEXT: CNDE_INT T0.W, T2.Y, T0.Y, T3.X, BS:VEC_120/SCL_212 1276; R600-NEXT: MUL_IEEE * T1.W, T1.X, literal.y, 1277; R600-NEXT: 1079283712(3.321289e+00), 2130706432(1.701412e+38) 1278; R600-NEXT: CNDE_INT T1.X, T6.W, T1.X, PS, 1279; R600-NEXT: LSHL T0.Y, PV.W, literal.x, 1280; R600-NEXT: AND_INT T1.Z, KC0[3].Z, literal.y, 1281; R600-NEXT: MULADD_IEEE T0.W, T2.W, literal.z, PV.Z, BS:VEC_120/SCL_212 1282; R600-NEXT: ADD * T1.W, T4.W, -PV.Y, 1283; R600-NEXT: 23(3.222986e-44), -4096(nan) 1284; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 1285; R600-NEXT: ADD T1.Y, PS, PV.W, 1286; R600-NEXT: MUL_IEEE T0.Z, PV.Z, literal.x, 1287; R600-NEXT: ADD_INT T0.W, PV.Y, literal.y, 1288; R600-NEXT: CNDE_INT * T1.W, T2.Y, T0.X, PV.X, 1289; R600-NEXT: 1079283712(3.321289e+00), 1065353216(1.000000e+00) 1290; R600-NEXT: MUL_IEEE T0.X, PS, PV.W, 1291; R600-NEXT: ADD T0.Y, KC0[3].Z, -T1.Z, 1292; R600-NEXT: RNDNE T2.Z, PV.Z, 1293; R600-NEXT: TRUNC T0.W, T3.Y, 1294; R600-NEXT: EXP_IEEE * T1.X, PV.Y, 1295; R600-NEXT: SETGT T2.X, literal.x, KC0[3].Y, 1296; R600-NEXT: FLT_TO_INT T1.Y, PV.W, 1297; R600-NEXT: TRUNC T3.Z, PV.Z, 1298; R600-NEXT: MUL_IEEE T0.W, PV.Y, literal.y, 1299; R600-NEXT: MUL_IEEE * T1.W, PS, literal.z, 1300; R600-NEXT: -1036817932(-4.485347e+01), 975668412(6.390323e-04) 1301; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 1302; R600-NEXT: MUL_IEEE T3.X, PS, literal.x, 1303; R600-NEXT: MUL_IEEE T2.Y, T1.X, literal.y, 1304; R600-NEXT: MULADD_IEEE T4.Z, T0.Y, literal.z, PV.W, 1305; R600-NEXT: FLT_TO_INT T0.W, PV.Z, 1306; R600-NEXT: MIN_INT * T2.W, PV.Y, literal.w, 1307; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38) 1308; R600-NEXT: 1079283712(3.321289e+00), 381(5.338947e-43) 1309; R600-NEXT: ADD_INT T4.X, PS, literal.x, 1310; R600-NEXT: MAX_INT T0.Y, PV.W, literal.y, 1311; R600-NEXT: MULADD_IEEE T1.Z, T1.Z, literal.z, PV.Z, 1312; R600-NEXT: ADD T2.W, T0.Z, -T2.Z, BS:VEC_120/SCL_212 1313; R600-NEXT: MIN_INT * T3.W, PV.W, literal.w, 1314; R600-NEXT: -254(nan), -330(nan) 1315; R600-NEXT: 975668412(6.390323e-04), 381(5.338947e-43) 1316; R600-NEXT: ADD_INT T5.X, PS, literal.x, 1317; R600-NEXT: ADD T3.Y, PV.W, PV.Z, 1318; R600-NEXT: ADD_INT T0.Z, PV.Y, literal.y, 1319; R600-NEXT: ADD_INT T2.W, T0.W, literal.z, 1320; R600-NEXT: SETGT_UINT * T3.W, T0.W, literal.w, 1321; R600-NEXT: -254(nan), 204(2.858649e-43) 1322; R600-NEXT: 102(1.429324e-43), -229(nan) 1323; R600-NEXT: ADD_INT * T6.X, T0.W, literal.x, 1324; R600-NEXT: -127(nan), 0(0.000000e+00) 1325; R600-NEXT: ALU clause starting at 106: 1326; R600-NEXT: SETGT_UINT T0.Y, T0.W, literal.x, 1327; R600-NEXT: CNDE_INT T0.Z, T3.W, T0.Z, T2.W, BS:VEC_102/SCL_221 1328; R600-NEXT: SETGT_INT T2.W, T0.W, literal.y, 1329; R600-NEXT: EXP_IEEE * T1.Z, T3.Y, 1330; R600-NEXT: 254(3.559298e-43), -127(nan) 1331; R600-NEXT: ADD_INT T7.X, T1.Y, literal.x, 1332; R600-NEXT: MUL_IEEE T3.Y, PS, literal.y, 1333; R600-NEXT: CNDE_INT T0.Z, PV.W, PV.Z, T0.W, 1334; R600-NEXT: CNDE_INT T4.W, PV.Y, T6.X, T5.X, 1335; R600-NEXT: SETGT_INT * T0.W, T0.W, literal.z, 1336; R600-NEXT: -127(nan), 209715200(1.972152e-31) 1337; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00) 1338; R600-NEXT: SETGT_UINT T5.X, T1.Y, literal.x, 1339; R600-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W, 1340; R600-NEXT: MAX_INT T0.Z, T1.Y, literal.y, 1341; R600-NEXT: MUL_IEEE T4.W, PV.Y, literal.z, 1342; R600-NEXT: MUL_IEEE * T5.W, T1.Z, literal.w, 1343; R600-NEXT: 254(3.559298e-43), -330(nan) 1344; R600-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38) 1345; R600-NEXT: MUL_IEEE T6.X, PS, literal.x, 1346; R600-NEXT: CNDE_INT T3.Y, T3.W, PV.W, T3.Y, BS:VEC_021/SCL_122 1347; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y, 1348; R600-NEXT: ADD_INT T3.W, T1.Y, literal.z, 1349; R600-NEXT: SETGT_UINT * T4.W, T1.Y, literal.w, 1350; R600-NEXT: 2130706432(1.701412e+38), 204(2.858649e-43) 1351; R600-NEXT: 102(1.429324e-43), -229(nan) 1352; R600-NEXT: CNDE_INT T8.X, PS, PV.Z, PV.W, 1353; R600-NEXT: SETGT_INT T5.Y, T1.Y, literal.x, 1354; R600-NEXT: CNDE_INT T0.Z, T2.W, PV.Y, T1.Z, 1355; R600-NEXT: CNDE_INT T2.W, T0.Y, T5.W, PV.X, BS:VEC_120/SCL_212 1356; R600-NEXT: LSHL * T3.W, T4.Y, literal.y, 1357; R600-NEXT: -127(nan), 23(3.222986e-44) 1358; R600-NEXT: ADD_INT T6.X, PS, literal.x, 1359; R600-NEXT: CNDE_INT T0.Y, T0.W, PV.Z, PV.W, 1360; R600-NEXT: CNDE_INT T0.Z, PV.Y, PV.X, T1.Y, 1361; R600-NEXT: CNDE_INT T0.W, T5.X, T7.X, T4.X, 1362; R600-NEXT: SETGT_INT * T2.W, T1.Y, literal.y, 1363; R600-NEXT: 1065353216(1.000000e+00), 127(1.779649e-43) 1364; R600-NEXT: CNDE_INT T4.X, PS, PV.Z, PV.W, 1365; R600-NEXT: MUL_IEEE T0.Y, PV.Y, PV.X, 1366; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].Z, 1367; R600-NEXT: MUL_IEEE T0.W, T2.Y, literal.y, 1368; R600-NEXT: CNDE_INT * T1.W, T4.W, T3.X, T1.W, 1369; R600-NEXT: -1036817932(-4.485347e+01), 2130706432(1.701412e+38) 1370; R600-NEXT: CNDE_INT T1.X, T5.Y, PS, T1.X, 1371; R600-NEXT: CNDE_INT T1.Y, T5.X, T2.Y, PV.W, 1372; R600-NEXT: CNDE T0.Z, PV.Z, PV.Y, 0.0, 1373; R600-NEXT: SETGT T0.W, KC0[3].Z, literal.x, 1374; R600-NEXT: LSHL * T1.W, PV.X, literal.y, 1375; R600-NEXT: 1109008539(3.853184e+01), 23(3.222986e-44) 1376; R600-NEXT: ADD_INT T3.X, PS, literal.x, 1377; R600-NEXT: CNDE T0.Y, PV.W, PV.Z, literal.y, 1378; R600-NEXT: CNDE_INT T0.Z, T2.W, PV.X, PV.Y, 1379; R600-NEXT: CNDE T0.W, T2.X, T0.X, 0.0, 1380; R600-NEXT: SETGT * T1.W, KC0[3].Y, literal.z, 1381; R600-NEXT: 1065353216(1.000000e+00), 2139095040(INF) 1382; R600-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00) 1383; R600-NEXT: CNDE T0.X, PS, PV.W, literal.x, 1384; R600-NEXT: MUL_IEEE T0.W, PV.Z, PV.X, 1385; R600-NEXT: SETGT * T1.W, literal.y, KC0[3].W, 1386; R600-NEXT: 2139095040(INF), -1036817932(-4.485347e+01) 1387; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x, 1388; R600-NEXT: CNDE T0.W, PS, PV.W, 0.0, 1389; R600-NEXT: SETGT * T1.W, KC0[3].W, literal.y, 1390; R600-NEXT: 2(2.802597e-45), 1109008539(3.853184e+01) 1391; R600-NEXT: CNDE T2.X, PS, PV.W, literal.x, 1392; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y, 1393; R600-NEXT: 2139095040(INF), 8(1.121039e-44) 1394; R600-NEXT: LSHR * T3.X, PV.W, literal.x, 1395; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1396; 1397; CM-LABEL: s_exp10_v3f32: 1398; CM: ; %bb.0: 1399; CM-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[] 1400; CM-NEXT: ALU 77, @108, KC0[CB0:0-32], KC1[] 1401; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X 1402; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T3.X 1403; CM-NEXT: CF_END 1404; CM-NEXT: PAD 1405; CM-NEXT: ALU clause starting at 6: 1406; CM-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x, 1407; CM-NEXT: -4096(nan), 0(0.000000e+00) 1408; CM-NEXT: ADD * T1.W, KC0[3].Y, -PV.W, 1409; CM-NEXT: MUL_IEEE T0.Z, PV.W, literal.x, 1410; CM-NEXT: MUL_IEEE * T2.W, T0.W, literal.y, 1411; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 1412; CM-NEXT: RNDNE T1.Z, PV.W, 1413; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Z, 1414; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 1415; CM-NEXT: MULADD_IEEE T0.Z, T0.W, literal.x, PV.W, 1416; CM-NEXT: ADD * T0.W, T2.W, -PV.Z, BS:VEC_120/SCL_212 1417; CM-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 1418; CM-NEXT: TRUNC T1.Z, T1.Z, 1419; CM-NEXT: ADD * T0.W, PV.W, PV.Z, 1420; CM-NEXT: EXP_IEEE T0.X, T0.W, 1421; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W, 1422; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W, 1423; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W, 1424; CM-NEXT: FLT_TO_INT T0.Z, T1.Z, 1425; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.x, 1426; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 1427; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, 1428; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.y, 1429; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z, 1430; CM-NEXT: 209715200(1.972152e-31), -330(nan) 1431; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00) 1432; CM-NEXT: ADD_INT T1.X, PV.W, literal.x, 1433; CM-NEXT: ADD_INT T1.Y, PV.Z, literal.y, 1434; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z, 1435; CM-NEXT: SETGT_UINT * T1.W, T0.Z, literal.w, 1436; CM-NEXT: -254(nan), 204(2.858649e-43) 1437; CM-NEXT: 102(1.429324e-43), -229(nan) 1438; CM-NEXT: ADD_INT T2.X, T0.Z, literal.x, 1439; CM-NEXT: SETGT_UINT T2.Y, T0.Z, literal.y, 1440; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z, 1441; CM-NEXT: SETGT_INT * T2.W, T0.Z, literal.x, 1442; CM-NEXT: -127(nan), 254(3.559298e-43) 1443; CM-NEXT: MUL_IEEE T3.X, T0.X, literal.x, 1444; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, T0.Z, 1445; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.X, 1446; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.y, 1447; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43) 1448; CM-NEXT: CNDE_INT T1.Y, PV.W, PV.Y, PV.Z, 1449; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.x, 1450; CM-NEXT: CNDE_INT * T0.W, T1.W, T0.Y, T0.W, 1451; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 1452; CM-NEXT: CNDE_INT T0.X, T2.W, PV.W, T0.X, 1453; CM-NEXT: CNDE_INT T0.Y, T2.Y, T3.X, PV.Z, 1454; CM-NEXT: LSHL T0.Z, PV.Y, literal.x, 1455; CM-NEXT: AND_INT * T0.W, KC0[3].Z, literal.y, 1456; CM-NEXT: 23(3.222986e-44), -4096(nan) 1457; CM-NEXT: ADD T1.Y, KC0[3].Z, -PV.W, 1458; CM-NEXT: ADD_INT T0.Z, PV.Z, literal.x, 1459; CM-NEXT: CNDE_INT * T1.W, T3.W, PV.X, PV.Y, 1460; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00) 1461; CM-NEXT: MUL_IEEE T0.X, PV.W, PV.Z, 1462; CM-NEXT: MUL_IEEE T0.Y, PV.Y, literal.x, 1463; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y, 1464; CM-NEXT: AND_INT * T1.W, KC0[3].W, literal.z, 1465; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 1466; CM-NEXT: -4096(nan), 0(0.000000e+00) 1467; CM-NEXT: SETGT T1.X, literal.x, KC0[3].Y, 1468; CM-NEXT: ADD T2.Y, KC0[3].W, -PV.W, 1469; CM-NEXT: RNDNE T1.Z, PV.Z, 1470; CM-NEXT: MULADD_IEEE * T2.W, T1.Y, literal.y, PV.Y, 1471; CM-NEXT: -1036817932(-4.485347e+01), 1079283712(3.321289e+00) 1472; CM-NEXT: MULADD_IEEE T2.X, T0.W, literal.x, PV.W, 1473; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z, 1474; CM-NEXT: MUL_IEEE T0.Z, PV.Y, literal.x, 1475; CM-NEXT: MUL_IEEE * T0.W, T1.W, literal.y, BS:VEC_120/SCL_212 1476; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 1477; CM-NEXT: TRUNC T3.X, T1.Z, 1478; CM-NEXT: RNDNE T1.Y, PV.W, 1479; CM-NEXT: MULADD_IEEE T0.Z, T2.Y, literal.x, PV.Z, 1480; CM-NEXT: ADD * T2.W, PV.Y, PV.X, 1481; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 1482; CM-NEXT: EXP_IEEE T0.X (MASKED), T2.W, 1483; CM-NEXT: EXP_IEEE T0.Y, T2.W, 1484; CM-NEXT: EXP_IEEE T0.Z (MASKED), T2.W, 1485; CM-NEXT: EXP_IEEE * T0.W (MASKED), T2.W, 1486; CM-NEXT: MULADD_IEEE T2.X, T1.W, literal.x, T0.Z, 1487; CM-NEXT: ADD T2.Y, T0.W, -T1.Y, BS:VEC_120/SCL_212 1488; CM-NEXT: FLT_TO_INT T0.Z, T3.X, 1489; CM-NEXT: MUL_IEEE * T0.W, PV.Y, literal.y, 1490; CM-NEXT: 975668412(6.390323e-04), 209715200(1.972152e-31) 1491; CM-NEXT: MUL_IEEE T3.X, PV.W, literal.x, 1492; CM-NEXT: SETGT_UINT T3.Y, PV.Z, literal.y, 1493; CM-NEXT: TRUNC T1.Z, T1.Y, 1494; CM-NEXT: ADD * T1.W, PV.Y, PV.X, 1495; CM-NEXT: 209715200(1.972152e-31), -229(nan) 1496; CM-NEXT: EXP_IEEE T1.X (MASKED), T1.W, 1497; CM-NEXT: EXP_IEEE T1.Y, T1.W, 1498; CM-NEXT: EXP_IEEE T1.Z (MASKED), T1.W, 1499; CM-NEXT: EXP_IEEE * T1.W (MASKED), T1.W, 1500; CM-NEXT: FLT_TO_INT T2.X, T1.Z, 1501; CM-NEXT: MUL_IEEE T2.Y, PV.Y, literal.x, 1502; CM-NEXT: CNDE_INT T1.Z, T3.Y, T3.X, T0.W, 1503; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y, BS:VEC_120/SCL_212 1504; CM-NEXT: 209715200(1.972152e-31), -127(nan) 1505; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, T0.Y, 1506; CM-NEXT: MUL_IEEE * T4.Y, PV.Y, literal.x, 1507; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 1508; CM-NEXT: ALU clause starting at 108: 1509; CM-NEXT: SETGT_UINT T1.Z, T2.X, literal.x, 1510; CM-NEXT: MAX_INT * T1.W, T0.Z, literal.y, 1511; CM-NEXT: -229(nan), -330(nan) 1512; CM-NEXT: ADD_INT T4.X, PV.W, literal.x, 1513; CM-NEXT: ADD_INT T5.Y, T0.Z, literal.y, 1514; CM-NEXT: CNDE_INT T2.Z, PV.Z, T4.Y, T2.Y, 1515; CM-NEXT: SETGT_INT * T1.W, T2.X, literal.z, 1516; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43) 1517; CM-NEXT: -127(nan), 0(0.000000e+00) 1518; CM-NEXT: CNDE_INT T5.X, PV.W, PV.Z, T1.Y, 1519; CM-NEXT: MUL_IEEE T0.Y, T0.Y, literal.x, 1520; CM-NEXT: MAX_INT T2.Z, T2.X, literal.y, 1521; CM-NEXT: CNDE_INT * T2.W, T3.Y, PV.X, PV.Y, BS:VEC_120/SCL_212 1522; CM-NEXT: 2130706432(1.701412e+38), -330(nan) 1523; CM-NEXT: CNDE_INT T4.X, T0.W, PV.W, T0.Z, 1524; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.x, 1525; CM-NEXT: ADD_INT T2.Z, T2.X, literal.y, 1526; CM-NEXT: MIN_INT * T0.W, T2.X, literal.z, 1527; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43) 1528; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00) 1529; CM-NEXT: ADD_INT T6.X, PV.W, literal.x, 1530; CM-NEXT: ADD_INT T3.Y, T2.X, literal.y, 1531; CM-NEXT: SETGT_UINT T3.Z, T2.X, literal.z, 1532; CM-NEXT: CNDE_INT * T0.W, T1.Z, PV.Y, PV.Z, 1533; CM-NEXT: -254(nan), -127(nan) 1534; CM-NEXT: 254(3.559298e-43), 0(0.000000e+00) 1535; CM-NEXT: MUL_IEEE T7.X, T1.Y, literal.x, 1536; CM-NEXT: CNDE_INT T1.Y, T1.W, PV.W, T2.X, 1537; CM-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, PV.X, 1538; CM-NEXT: MIN_INT * T0.W, T0.Z, literal.y, 1539; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43) 1540; CM-NEXT: SETGT_INT T2.X, T2.X, literal.x, 1541; CM-NEXT: ADD_INT T2.Y, PV.W, literal.y, 1542; CM-NEXT: ADD_INT T2.Z, T0.Z, literal.z, 1543; CM-NEXT: SETGT_UINT * T0.W, T0.Z, literal.w, 1544; CM-NEXT: 127(1.779649e-43), -254(nan) 1545; CM-NEXT: -127(nan), 254(3.559298e-43) 1546; CM-NEXT: CNDE_INT T6.X, PV.W, PV.Z, PV.Y, 1547; CM-NEXT: SETGT_INT T2.Y, T0.Z, literal.x, 1548; CM-NEXT: CNDE_INT T0.Z, PV.X, T1.Y, T1.Z, 1549; CM-NEXT: MUL_IEEE * T1.W, T7.X, literal.y, 1550; CM-NEXT: 127(1.779649e-43), 2130706432(1.701412e+38) 1551; CM-NEXT: CNDE_INT T7.X, T3.Z, T7.X, PV.W, 1552; CM-NEXT: LSHL T1.Y, PV.Z, literal.x, 1553; CM-NEXT: CNDE_INT T0.Z, PV.Y, T4.X, PV.X, BS:VEC_021/SCL_122 1554; CM-NEXT: MUL_IEEE * T1.W, T0.Y, literal.y, 1555; CM-NEXT: 23(3.222986e-44), 2130706432(1.701412e+38) 1556; CM-NEXT: CNDE_INT T4.X, T0.W, T0.Y, PV.W, 1557; CM-NEXT: LSHL T0.Y, PV.Z, literal.x, 1558; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y, 1559; CM-NEXT: CNDE_INT * T0.W, T2.X, T5.X, PV.X, 1560; CM-NEXT: 23(3.222986e-44), 1065353216(1.000000e+00) 1561; CM-NEXT: MUL_IEEE T2.X, PV.W, PV.Z, 1562; CM-NEXT: SETGT T1.Y, literal.x, KC0[3].W, 1563; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y, 1564; CM-NEXT: CNDE_INT * T0.W, T2.Y, T3.X, PV.X, 1565; CM-NEXT: -1036817932(-4.485347e+01), 1065353216(1.000000e+00) 1566; CM-NEXT: MUL_IEEE T3.X, PV.W, PV.Z, 1567; CM-NEXT: SETGT T0.Y, literal.x, KC0[3].Z, 1568; CM-NEXT: CNDE T0.Z, PV.Y, PV.X, 0.0, 1569; CM-NEXT: SETGT * T0.W, KC0[3].W, literal.y, 1570; CM-NEXT: -1036817932(-4.485347e+01), 1109008539(3.853184e+01) 1571; CM-NEXT: CNDE T2.X, PV.W, PV.Z, literal.x, 1572; CM-NEXT: CNDE T0.Y, PV.Y, PV.X, 0.0, 1573; CM-NEXT: SETGT T0.Z, KC0[3].Z, literal.y, 1574; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z, 1575; CM-NEXT: 2139095040(INF), 1109008539(3.853184e+01) 1576; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) 1577; CM-NEXT: LSHR T3.X, PV.W, literal.x, 1578; CM-NEXT: CNDE T0.Y, PV.Z, PV.Y, literal.y, 1579; CM-NEXT: CNDE T0.Z, T1.X, T0.X, 0.0, 1580; CM-NEXT: SETGT * T0.W, KC0[3].Y, literal.z, 1581; CM-NEXT: 2(2.802597e-45), 2139095040(INF) 1582; CM-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00) 1583; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x, 1584; CM-NEXT: 2139095040(INF), 0(0.000000e+00) 1585; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1586; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1587 %result = call <3 x float> @llvm.exp10.v3f32(<3 x float> %in) 1588 store <3 x float> %result, ptr addrspace(1) %out 1589 ret void 1590} 1591 1592; FIXME: We should be able to merge these packets together on Cayman so we 1593; have a maximum of 4 instructions. 1594define amdgpu_kernel void @s_exp10_v4f32(ptr addrspace(1) %out, <4 x float> %in) { 1595; VI-SDAG-LABEL: s_exp10_v4f32: 1596; VI-SDAG: ; %bb.0: 1597; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 1598; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549000 1599; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0x421a209b 1600; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 1601; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 1602; VI-SDAG-NEXT: s_and_b32 s6, s3, 0xfffff000 1603; VI-SDAG-NEXT: v_mov_b32_e32 v2, s6 1604; VI-SDAG-NEXT: v_sub_f32_e32 v2, s3, v2 1605; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 1606; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 1607; VI-SDAG-NEXT: v_mul_f32_e32 v1, s6, v0 1608; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 1609; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x3a2784bc 1610; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 1611; VI-SDAG-NEXT: v_mul_f32_e32 v5, s6, v4 1612; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 1613; VI-SDAG-NEXT: v_add_f32_e32 v2, v5, v2 1614; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 1615; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 1616; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 1617; VI-SDAG-NEXT: s_and_b32 s6, s2, 0xfffff000 1618; VI-SDAG-NEXT: v_mov_b32_e32 v7, s6 1619; VI-SDAG-NEXT: v_sub_f32_e32 v7, s2, v7 1620; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 1621; VI-SDAG-NEXT: v_mul_f32_e32 v2, s6, v0 1622; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3a2784bc, v7 1623; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x40549000, v7 1624; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 1625; VI-SDAG-NEXT: v_add_f32_e32 v7, v7, v8 1626; VI-SDAG-NEXT: v_mul_f32_e32 v8, s6, v4 1627; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 1628; VI-SDAG-NEXT: v_add_f32_e32 v7, v8, v7 1629; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0xc23369f4 1630; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v7 1631; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v5 1632; VI-SDAG-NEXT: v_exp_f32_e32 v2, v2 1633; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v3 1634; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 1635; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v6 1636; VI-SDAG-NEXT: s_and_b32 s3, s1, 0xfffff000 1637; VI-SDAG-NEXT: v_mov_b32_e32 v9, s3 1638; VI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f800000 1639; VI-SDAG-NEXT: v_sub_f32_e32 v9, s1, v9 1640; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v8, v1, vcc 1641; VI-SDAG-NEXT: v_ldexp_f32 v1, v2, v7 1642; VI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0 1643; VI-SDAG-NEXT: v_mul_f32_e32 v10, 0x3a2784bc, v9 1644; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x40549000, v9 1645; VI-SDAG-NEXT: v_rndne_f32_e32 v7, v2 1646; VI-SDAG-NEXT: v_add_f32_e32 v9, v9, v10 1647; VI-SDAG-NEXT: v_mul_f32_e32 v10, s3, v4 1648; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v7 1649; VI-SDAG-NEXT: v_add_f32_e32 v9, v10, v9 1650; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v9 1651; VI-SDAG-NEXT: v_exp_f32_e32 v9, v2 1652; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v7 1653; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v5 1654; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 1655; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v6 1656; VI-SDAG-NEXT: s_and_b32 s2, s0, 0xfffff000 1657; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc 1658; VI-SDAG-NEXT: v_ldexp_f32 v1, v9, v7 1659; VI-SDAG-NEXT: v_mov_b32_e32 v9, s2 1660; VI-SDAG-NEXT: v_sub_f32_e32 v9, s0, v9 1661; VI-SDAG-NEXT: v_mul_f32_e32 v0, s2, v0 1662; VI-SDAG-NEXT: v_mul_f32_e32 v10, 0x3a2784bc, v9 1663; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x40549000, v9 1664; VI-SDAG-NEXT: v_rndne_f32_e32 v7, v0 1665; VI-SDAG-NEXT: v_add_f32_e32 v9, v9, v10 1666; VI-SDAG-NEXT: v_mul_f32_e32 v4, s2, v4 1667; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v7 1668; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v9 1669; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v4 1670; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 1671; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v4, v7 1672; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v5 1673; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 1674; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v6 1675; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 1676; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v4 1677; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v5 1678; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 1679; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v6 1680; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4 1681; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 1682; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5 1683; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3] 1684; VI-SDAG-NEXT: s_endpgm 1685; 1686; VI-GISEL-LABEL: s_exp10_v4f32: 1687; VI-GISEL: ; %bb.0: 1688; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 1689; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549000 1690; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3a2784bc 1691; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b 1692; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 1693; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 1694; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000 1695; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6 1696; VI-GISEL-NEXT: v_sub_f32_e32 v0, s0, v0 1697; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0 1698; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 1699; VI-GISEL-NEXT: v_mul_f32_e32 v1, s6, v2 1700; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v4 1701; VI-GISEL-NEXT: v_mul_f32_e32 v4, s6, v3 1702; VI-GISEL-NEXT: v_add_f32_e32 v0, v4, v0 1703; VI-GISEL-NEXT: v_rndne_f32_e32 v4, v1 1704; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4 1705; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0 1706; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4 1707; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 1708; VI-GISEL-NEXT: s_and_b32 s6, s1, 0xfffff000 1709; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v2 1710; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4 1711; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 1712; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6 1713; VI-GISEL-NEXT: v_sub_f32_e32 v1, s1, v1 1714; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3a2784bc, v1 1715; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x40549000, v1 1716; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7 1717; VI-GISEL-NEXT: v_mul_f32_e32 v7, s6, v3 1718; VI-GISEL-NEXT: v_add_f32_e32 v1, v7, v1 1719; VI-GISEL-NEXT: v_rndne_f32_e32 v7, v6 1720; VI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v7 1721; VI-GISEL-NEXT: v_add_f32_e32 v1, v6, v1 1722; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7 1723; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 1724; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4 1725; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1726; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5 1727; VI-GISEL-NEXT: s_and_b32 s0, s2, 0xfffff000 1728; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v6 1729; VI-GISEL-NEXT: v_mov_b32_e32 v6, s0 1730; VI-GISEL-NEXT: v_sub_f32_e32 v6, s2, v6 1731; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v6 1732; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x40549000, v6 1733; VI-GISEL-NEXT: v_mul_f32_e32 v8, s0, v2 1734; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v9 1735; VI-GISEL-NEXT: v_mul_f32_e32 v9, s0, v3 1736; VI-GISEL-NEXT: v_add_f32_e32 v6, v9, v6 1737; VI-GISEL-NEXT: v_rndne_f32_e32 v9, v8 1738; VI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v9 1739; VI-GISEL-NEXT: v_add_f32_e32 v6, v8, v6 1740; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9 1741; VI-GISEL-NEXT: v_exp_f32_e32 v6, v6 1742; VI-GISEL-NEXT: s_and_b32 s0, s3, 0xfffff000 1743; VI-GISEL-NEXT: v_mul_f32_e32 v2, s0, v2 1744; VI-GISEL-NEXT: v_mul_f32_e32 v3, s0, v3 1745; VI-GISEL-NEXT: v_ldexp_f32 v6, v6, v8 1746; VI-GISEL-NEXT: v_mov_b32_e32 v8, s0 1747; VI-GISEL-NEXT: v_sub_f32_e32 v8, s3, v8 1748; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3a2784bc, v8 1749; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x40549000, v8 1750; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 1751; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8 1752; VI-GISEL-NEXT: v_rndne_f32_e32 v8, v2 1753; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8 1754; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000 1755; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 1756; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc 1757; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4 1758; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v8 1759; VI-GISEL-NEXT: v_exp_f32_e32 v8, v2 1760; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 1761; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5 1762; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc 1763; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4 1764; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc 1765; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5 1766; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc 1767; VI-GISEL-NEXT: v_ldexp_f32 v3, v8, v3 1768; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4 1769; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc 1770; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5 1771; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4 1772; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 1773; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5 1774; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3] 1775; VI-GISEL-NEXT: s_endpgm 1776; 1777; GFX900-SDAG-LABEL: s_exp10_v4f32: 1778; GFX900-SDAG: ; %bb.0: 1779; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 1780; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 1781; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 1782; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 1783; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0xc23369f4 1784; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0) 1785; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0 1786; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v2 1787; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v2 1788; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 1789; GFX900-SDAG-NEXT: v_fma_f32 v4, s3, v1, v4 1790; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 1791; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3 1792; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2 1793; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v5 1794; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0x421a209b 1795; GFX900-SDAG-NEXT: v_mov_b32_e32 v9, 0x7f800000 1796; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, v3 1797; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, s2, v0 1798; GFX900-SDAG-NEXT: v_rndne_f32_e32 v7, v3 1799; GFX900-SDAG-NEXT: v_sub_f32_e32 v8, v3, v7 1800; GFX900-SDAG-NEXT: v_fma_f32 v3, s2, v0, -v3 1801; GFX900-SDAG-NEXT: v_fma_f32 v3, s2, v1, v3 1802; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v8, v3 1803; GFX900-SDAG-NEXT: v_exp_f32_e32 v8, v3 1804; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v7 1805; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 1806; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v6 1807; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v9, v2, vcc 1808; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v8, v7 1809; GFX900-SDAG-NEXT: v_mul_f32_e32 v7, s1, v0 1810; GFX900-SDAG-NEXT: v_rndne_f32_e32 v8, v7 1811; GFX900-SDAG-NEXT: v_sub_f32_e32 v10, v7, v8 1812; GFX900-SDAG-NEXT: v_fma_f32 v7, s1, v0, -v7 1813; GFX900-SDAG-NEXT: v_fma_f32 v7, s1, v1, v7 1814; GFX900-SDAG-NEXT: v_add_f32_e32 v7, v10, v7 1815; GFX900-SDAG-NEXT: v_exp_f32_e32 v7, v7 1816; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v8, v8 1817; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v5 1818; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 1819; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v6 1820; GFX900-SDAG-NEXT: v_ldexp_f32 v7, v7, v8 1821; GFX900-SDAG-NEXT: v_mul_f32_e32 v8, s0, v0 1822; GFX900-SDAG-NEXT: v_rndne_f32_e32 v10, v8 1823; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v8 1824; GFX900-SDAG-NEXT: v_sub_f32_e32 v11, v8, v10 1825; GFX900-SDAG-NEXT: v_fma_f32 v0, s0, v1, v0 1826; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v11, v0 1827; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 1828; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v8, v10 1829; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc 1830; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v5 1831; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc 1832; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v6 1833; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc 1834; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v8 1835; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v5 1836; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 1837; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v6 1838; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0 1839; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc 1840; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] 1841; GFX900-SDAG-NEXT: s_endpgm 1842; 1843; GFX900-GISEL-LABEL: s_exp10_v4f32: 1844; GFX900-GISEL: ; %bb.0: 1845; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 1846; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 1847; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549a78 1848; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 1849; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b 1850; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) 1851; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v2 1852; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v0 1853; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v0 1854; GFX900-GISEL-NEXT: v_fma_f32 v1, s0, v3, v1 1855; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 1856; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 1857; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4 1858; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 1859; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4 1860; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4 1861; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 1862; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s1, v2 1863; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v1 1864; GFX900-GISEL-NEXT: v_rndne_f32_e32 v7, v1 1865; GFX900-GISEL-NEXT: v_fma_f32 v6, s1, v3, v6 1866; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7 1867; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v6 1868; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7 1869; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 1870; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1871; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000 1872; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5 1873; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v6 1874; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s2, v2 1875; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v6 1876; GFX900-GISEL-NEXT: v_rndne_f32_e32 v9, v6 1877; GFX900-GISEL-NEXT: v_fma_f32 v8, s2, v3, v8 1878; GFX900-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9 1879; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v8 1880; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9 1881; GFX900-GISEL-NEXT: v_exp_f32_e32 v6, v6 1882; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc 1883; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4 1884; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 1885; GFX900-GISEL-NEXT: v_ldexp_f32 v6, v6, v8 1886; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, s3, v2 1887; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v8 1888; GFX900-GISEL-NEXT: v_fma_f32 v2, s3, v3, v2 1889; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v8 1890; GFX900-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3 1891; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v8, v2 1892; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3 1893; GFX900-GISEL-NEXT: v_exp_f32_e32 v8, v2 1894; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5 1895; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc 1896; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4 1897; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc 1898; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5 1899; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc 1900; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v8, v3 1901; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4 1902; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc 1903; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5 1904; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 1905; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 1906; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] 1907; GFX900-GISEL-NEXT: s_endpgm 1908; 1909; SI-SDAG-LABEL: s_exp10_v4f32: 1910; SI-SDAG: ; %bb.0: 1911; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd 1912; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 1913; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 1914; SI-SDAG-NEXT: v_mov_b32_e32 v5, 0x421a209b 1915; SI-SDAG-NEXT: v_mov_b32_e32 v8, 0x7f800000 1916; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 1917; SI-SDAG-NEXT: v_mul_f32_e32 v2, s3, v0 1918; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 1919; SI-SDAG-NEXT: v_fma_f32 v4, s3, v0, -v2 1920; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 1921; SI-SDAG-NEXT: v_fma_f32 v4, s3, v1, v4 1922; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 1923; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 1924; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v3, v3 1925; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0xc23369f4 1926; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s3, v4 1927; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 1928; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v2, v3 1929; SI-SDAG-NEXT: v_mul_f32_e32 v3, s2, v0 1930; SI-SDAG-NEXT: v_rndne_f32_e32 v6, v3 1931; SI-SDAG-NEXT: v_sub_f32_e32 v7, v3, v6 1932; SI-SDAG-NEXT: v_fma_f32 v3, s2, v0, -v3 1933; SI-SDAG-NEXT: v_fma_f32 v3, s2, v1, v3 1934; SI-SDAG-NEXT: v_add_f32_e32 v3, v7, v3 1935; SI-SDAG-NEXT: v_exp_f32_e32 v7, v3 1936; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v6, v6 1937; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 1938; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s3, v5 1939; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v8, v2, vcc 1940; SI-SDAG-NEXT: v_ldexp_f32_e32 v2, v7, v6 1941; SI-SDAG-NEXT: v_mul_f32_e32 v6, s1, v0 1942; SI-SDAG-NEXT: v_rndne_f32_e32 v7, v6 1943; SI-SDAG-NEXT: v_sub_f32_e32 v9, v6, v7 1944; SI-SDAG-NEXT: v_fma_f32 v6, s1, v0, -v6 1945; SI-SDAG-NEXT: v_fma_f32 v6, s1, v1, v6 1946; SI-SDAG-NEXT: v_add_f32_e32 v6, v9, v6 1947; SI-SDAG-NEXT: v_exp_f32_e32 v6, v6 1948; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v7 1949; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s2, v4 1950; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 1951; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s2, v5 1952; SI-SDAG-NEXT: v_ldexp_f32_e32 v6, v6, v7 1953; SI-SDAG-NEXT: v_mul_f32_e32 v7, s0, v0 1954; SI-SDAG-NEXT: v_rndne_f32_e32 v9, v7 1955; SI-SDAG-NEXT: v_fma_f32 v0, s0, v0, -v7 1956; SI-SDAG-NEXT: v_sub_f32_e32 v10, v7, v9 1957; SI-SDAG-NEXT: v_fma_f32 v0, s0, v1, v0 1958; SI-SDAG-NEXT: v_add_f32_e32 v0, v10, v0 1959; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 1960; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v7, v9 1961; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc 1962; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s1, v4 1963; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc 1964; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s1, v5 1965; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 1966; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v7 1967; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s0, v4 1968; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 1969; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v5 1970; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000 1971; SI-SDAG-NEXT: s_mov_b32 s6, -1 1972; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 1973; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0) 1974; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 1975; SI-SDAG-NEXT: s_endpgm 1976; 1977; SI-GISEL-LABEL: s_exp10_v4f32: 1978; SI-GISEL: ; %bb.0: 1979; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd 1980; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x40549a78 1981; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 1982; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x421a209b 1983; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 1984; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) 1985; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v2 1986; SI-GISEL-NEXT: v_fma_f32 v1, s0, v2, -v0 1987; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v0 1988; SI-GISEL-NEXT: v_fma_f32 v1, s0, v3, v1 1989; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 1990; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 1991; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v4 1992; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 1993; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xc23369f4 1994; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v4 1995; SI-GISEL-NEXT: s_mov_b32 s6, -1 1996; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 1997; SI-GISEL-NEXT: v_mul_f32_e32 v1, s1, v2 1998; SI-GISEL-NEXT: v_fma_f32 v6, s1, v2, -v1 1999; SI-GISEL-NEXT: v_rndne_f32_e32 v7, v1 2000; SI-GISEL-NEXT: v_fma_f32 v6, s1, v3, v6 2001; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7 2002; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6 2003; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v6, v7 2004; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 2005; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 2006; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x7f800000 2007; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v5 2008; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v6 2009; SI-GISEL-NEXT: v_mul_f32_e32 v6, s2, v2 2010; SI-GISEL-NEXT: v_fma_f32 v8, s2, v2, -v6 2011; SI-GISEL-NEXT: v_rndne_f32_e32 v9, v6 2012; SI-GISEL-NEXT: v_fma_f32 v8, s2, v3, v8 2013; SI-GISEL-NEXT: v_sub_f32_e32 v6, v6, v9 2014; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8 2015; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v8, v9 2016; SI-GISEL-NEXT: v_exp_f32_e32 v6, v6 2017; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc 2018; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v4 2019; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 2020; SI-GISEL-NEXT: v_ldexp_f32_e32 v6, v6, v8 2021; SI-GISEL-NEXT: v_mul_f32_e32 v8, s3, v2 2022; SI-GISEL-NEXT: v_fma_f32 v2, s3, v2, -v8 2023; SI-GISEL-NEXT: v_fma_f32 v2, s3, v3, v2 2024; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v8 2025; SI-GISEL-NEXT: v_sub_f32_e32 v8, v8, v3 2026; SI-GISEL-NEXT: v_add_f32_e32 v2, v8, v2 2027; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v3 2028; SI-GISEL-NEXT: v_exp_f32_e32 v8, v2 2029; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s1, v5 2030; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc 2031; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v4 2032; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, vcc 2033; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s2, v5 2034; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc 2035; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v8, v3 2036; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v4 2037; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc 2038; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s3, v5 2039; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 2040; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 2041; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 2042; SI-GISEL-NEXT: s_endpgm 2043; 2044; R600-LABEL: s_exp10_v4f32: 2045; R600: ; %bb.0: 2046; R600-NEXT: ALU 98, @6, KC0[CB0:0-32], KC1[] 2047; R600-NEXT: ALU 95, @105, KC0[CB0:0-32], KC1[] 2048; R600-NEXT: ALU 24, @201, KC0[CB0:0-32], KC1[] 2049; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 2050; R600-NEXT: CF_END 2051; R600-NEXT: PAD 2052; R600-NEXT: ALU clause starting at 6: 2053; R600-NEXT: AND_INT * T0.W, KC0[3].Z, literal.x, 2054; R600-NEXT: -4096(nan), 0(0.000000e+00) 2055; R600-NEXT: ADD * T1.W, KC0[3].Z, -PV.W, 2056; R600-NEXT: MUL_IEEE T2.W, PV.W, literal.x, 2057; R600-NEXT: MUL_IEEE * T3.W, T0.W, literal.y, 2058; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 2059; R600-NEXT: RNDNE T4.W, PS, 2060; R600-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.W, BS:VEC_021/SCL_122 2061; R600-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 2062; R600-NEXT: MULADD_IEEE T0.W, T0.W, literal.x, PS, 2063; R600-NEXT: ADD * T1.W, T3.W, -PV.W, 2064; R600-NEXT: 975668412(6.390323e-04), 0(0.000000e+00) 2065; R600-NEXT: ADD T0.W, PS, PV.W, 2066; R600-NEXT: TRUNC * T1.W, T4.W, 2067; R600-NEXT: FLT_TO_INT T1.W, PS, 2068; R600-NEXT: EXP_IEEE * T0.X, PV.W, 2069; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x, 2070; R600-NEXT: MAX_INT T0.W, PV.W, literal.y, 2071; R600-NEXT: MIN_INT * T2.W, PV.W, literal.z, 2072; R600-NEXT: 209715200(1.972152e-31), -330(nan) 2073; R600-NEXT: 381(5.338947e-43), 0(0.000000e+00) 2074; R600-NEXT: ADD_INT T1.X, PS, literal.x, 2075; R600-NEXT: AND_INT T0.Y, KC0[4].X, literal.y, 2076; R600-NEXT: ADD_INT T1.Z, PV.W, literal.z, 2077; R600-NEXT: ADD_INT * T0.W, T1.W, literal.w, 2078; R600-NEXT: -254(nan), -4096(nan) 2079; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43) 2080; R600-NEXT: SETGT_UINT * T2.W, T1.W, literal.x, 2081; R600-NEXT: -229(nan), 0(0.000000e+00) 2082; R600-NEXT: ADD_INT T2.X, T1.W, literal.x, 2083; R600-NEXT: SETGT_UINT T1.Y, T1.W, literal.y, 2084; R600-NEXT: CNDE_INT T1.Z, PV.W, T1.Z, T0.W, 2085; R600-NEXT: SETGT_INT T0.W, T1.W, literal.x, 2086; R600-NEXT: ADD * T3.W, KC0[4].X, -T0.Y, 2087; R600-NEXT: -127(nan), 254(3.559298e-43) 2088; R600-NEXT: MUL_IEEE T3.X, PS, literal.x, 2089; R600-NEXT: MUL_IEEE T2.Y, T0.Y, literal.y, 2090; R600-NEXT: CNDE_INT T1.Z, PV.W, PV.Z, T1.W, 2091; R600-NEXT: CNDE_INT T4.W, PV.Y, PV.X, T1.X, 2092; R600-NEXT: SETGT_INT * T1.W, T1.W, literal.z, 2093; R600-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 2094; R600-NEXT: 127(1.779649e-43), 0(0.000000e+00) 2095; R600-NEXT: CNDE_INT T1.X, PS, PV.Z, PV.W, 2096; R600-NEXT: RNDNE T3.Y, PV.Y, 2097; R600-NEXT: MULADD_IEEE T1.Z, T3.W, literal.x, PV.X, 2098; R600-NEXT: MUL_IEEE T3.W, T0.Z, literal.y, 2099; R600-NEXT: MUL_IEEE * T4.W, T0.X, literal.z, 2100; R600-NEXT: 1079283712(3.321289e+00), 209715200(1.972152e-31) 2101; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 2102; R600-NEXT: MUL_IEEE T2.X, PS, literal.x, 2103; R600-NEXT: CNDE_INT T4.Y, T2.W, PV.W, T0.Z, 2104; R600-NEXT: MULADD_IEEE T0.Z, T0.Y, literal.y, PV.Z, 2105; R600-NEXT: ADD T2.W, T2.Y, -PV.Y, BS:VEC_120/SCL_212 2106; R600-NEXT: AND_INT * T3.W, KC0[3].Y, literal.z, 2107; R600-NEXT: 2130706432(1.701412e+38), 975668412(6.390323e-04) 2108; R600-NEXT: -4096(nan), 0(0.000000e+00) 2109; R600-NEXT: MUL_IEEE T3.X, PS, literal.x, 2110; R600-NEXT: ADD T0.Y, PV.W, PV.Z, 2111; R600-NEXT: CNDE_INT T0.Z, T0.W, PV.Y, T0.X, BS:VEC_021/SCL_122 2112; R600-NEXT: CNDE_INT T0.W, T1.Y, T4.W, PV.X, 2113; R600-NEXT: LSHL * T2.W, T1.X, literal.y, 2114; R600-NEXT: 1079283712(3.321289e+00), 23(3.222986e-44) 2115; R600-NEXT: AND_INT T0.X, KC0[3].W, literal.x, 2116; R600-NEXT: TRUNC T1.Y, T3.Y, 2117; R600-NEXT: ADD_INT T1.Z, PS, literal.y, 2118; R600-NEXT: CNDE_INT T0.W, T1.W, PV.Z, PV.W, 2119; R600-NEXT: EXP_IEEE * T0.Y, PV.Y, 2120; R600-NEXT: -4096(nan), 1065353216(1.000000e+00) 2121; R600-NEXT: MUL_IEEE T1.X, PV.W, PV.Z, 2122; R600-NEXT: FLT_TO_INT T1.Y, PV.Y, 2123; R600-NEXT: MUL_IEEE T0.Z, PS, literal.x, 2124; R600-NEXT: ADD T0.W, KC0[3].W, -PV.X, 2125; R600-NEXT: RNDNE * T1.W, T3.X, 2126; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 2127; R600-NEXT: SETGT T2.X, literal.x, KC0[3].Z, 2128; R600-NEXT: TRUNC T2.Y, PS, 2129; R600-NEXT: MUL_IEEE T1.Z, PV.W, literal.y, 2130; R600-NEXT: MUL_IEEE T2.W, PV.Z, literal.z, 2131; R600-NEXT: MAX_INT * T4.W, PV.Y, literal.w, 2132; R600-NEXT: -1036817932(-4.485347e+01), 975668412(6.390323e-04) 2133; R600-NEXT: 209715200(1.972152e-31), -330(nan) 2134; R600-NEXT: ADD T4.X, KC0[3].Y, -T3.W, 2135; R600-NEXT: ADD_INT T3.Y, PS, literal.x, 2136; R600-NEXT: ADD_INT T2.Z, T1.Y, literal.y, 2137; R600-NEXT: SETGT_UINT T4.W, T1.Y, literal.z, 2138; R600-NEXT: MIN_INT * T5.W, T1.Y, literal.w, 2139; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43) 2140; R600-NEXT: -229(nan), 381(5.338947e-43) 2141; R600-NEXT: ADD_INT T5.X, PS, literal.x, 2142; R600-NEXT: ADD_INT T4.Y, T1.Y, literal.y, 2143; R600-NEXT: SETGT_UINT T3.Z, T1.Y, literal.z, 2144; R600-NEXT: CNDE_INT T5.W, PV.W, PV.Y, PV.Z, 2145; R600-NEXT: SETGT_INT * T6.W, T1.Y, literal.y, 2146; R600-NEXT: -254(nan), -127(nan) 2147; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00) 2148; R600-NEXT: MUL_IEEE T6.X, T0.Y, literal.x, 2149; R600-NEXT: CNDE_INT T3.Y, PS, PV.W, T1.Y, 2150; R600-NEXT: CNDE_INT * T2.Z, PV.Z, PV.Y, PV.X, 2151; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 2152; R600-NEXT: ALU clause starting at 105: 2153; R600-NEXT: SETGT_INT T5.W, T1.Y, literal.x, 2154; R600-NEXT: MUL_IEEE * T7.W, T4.X, literal.y, 2155; R600-NEXT: 127(1.779649e-43), 975668412(6.390323e-04) 2156; R600-NEXT: MUL_IEEE T5.X, T0.X, literal.x, 2157; R600-NEXT: MULADD_IEEE T1.Y, T4.X, literal.x, PS, BS:VEC_120/SCL_212 2158; R600-NEXT: CNDE_INT T2.Z, PV.W, T3.Y, T2.Z, 2159; R600-NEXT: MUL_IEEE T7.W, T6.X, literal.y, BS:VEC_201 2160; R600-NEXT: CNDE_INT * T2.W, T4.W, T2.W, T0.Z, 2161; R600-NEXT: 1079283712(3.321289e+00), 2130706432(1.701412e+38) 2162; R600-NEXT: CNDE_INT T4.X, T6.W, PS, T0.Y, 2163; R600-NEXT: CNDE_INT T0.Y, T3.Z, T6.X, PV.W, 2164; R600-NEXT: LSHL T0.Z, PV.Z, literal.x, 2165; R600-NEXT: MULADD_IEEE T2.W, T3.W, literal.y, PV.Y, BS:VEC_201 2166; R600-NEXT: ADD * T1.W, T3.X, -T1.W, 2167; R600-NEXT: 23(3.222986e-44), 975668412(6.390323e-04) 2168; R600-NEXT: ADD T3.X, PS, PV.W, 2169; R600-NEXT: ADD_INT T1.Y, PV.Z, literal.x, 2170; R600-NEXT: CNDE_INT T0.Z, T5.W, PV.X, PV.Y, 2171; R600-NEXT: RNDNE T1.W, T5.X, 2172; R600-NEXT: MULADD_IEEE * T0.W, T0.W, literal.y, T1.Z, BS:VEC_021/SCL_122 2173; R600-NEXT: 1065353216(1.000000e+00), 1079283712(3.321289e+00) 2174; R600-NEXT: MULADD_IEEE T0.X, T0.X, literal.x, PS, 2175; R600-NEXT: ADD T0.Y, T5.X, -PV.W, BS:VEC_120/SCL_212 2176; R600-NEXT: MUL_IEEE T0.Z, PV.Z, PV.Y, 2177; R600-NEXT: SETGT T0.W, literal.y, KC0[4].X, 2178; R600-NEXT: EXP_IEEE * T1.Y, PV.X, 2179; R600-NEXT: 975668412(6.390323e-04), -1036817932(-4.485347e+01) 2180; R600-NEXT: CNDE T3.X, PV.W, PV.Z, 0.0, 2181; R600-NEXT: ADD T0.Y, PV.Y, PV.X, 2182; R600-NEXT: FLT_TO_INT T0.Z, T2.Y, 2183; R600-NEXT: TRUNC T0.W, T1.W, 2184; R600-NEXT: MUL_IEEE * T1.W, PS, literal.x, 2185; R600-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 2186; R600-NEXT: SETGT T0.X, KC0[4].X, literal.x, 2187; R600-NEXT: MUL_IEEE T2.Y, PS, literal.y, 2188; R600-NEXT: FLT_TO_INT T1.Z, PV.W, 2189; R600-NEXT: MAX_INT T0.W, PV.Z, literal.z, 2190; R600-NEXT: EXP_IEEE * T0.Y, PV.Y, 2191; R600-NEXT: 1109008539(3.853184e+01), 209715200(1.972152e-31) 2192; R600-NEXT: -330(nan), 0(0.000000e+00) 2193; R600-NEXT: MUL_IEEE T4.X, T1.Y, literal.x, 2194; R600-NEXT: MUL_IEEE T3.Y, PS, literal.y, 2195; R600-NEXT: ADD_INT T2.Z, PV.W, literal.z, 2196; R600-NEXT: ADD_INT * T0.W, T0.Z, literal.w, 2197; R600-NEXT: 2130706432(1.701412e+38), 209715200(1.972152e-31) 2198; R600-NEXT: 204(2.858649e-43), 102(1.429324e-43) 2199; R600-NEXT: MAX_INT * T2.W, T1.Z, literal.x, 2200; R600-NEXT: -330(nan), 0(0.000000e+00) 2201; R600-NEXT: SETGT_UINT T5.X, T0.Z, literal.x, 2202; R600-NEXT: ADD_INT T4.Y, PV.W, literal.y, 2203; R600-NEXT: ADD_INT T3.Z, T1.Z, literal.z, BS:VEC_120/SCL_212 2204; R600-NEXT: SETGT_UINT T2.W, T1.Z, literal.x, BS:VEC_120/SCL_212 2205; R600-NEXT: MIN_INT * T3.W, T1.Z, literal.w, 2206; R600-NEXT: -229(nan), 204(2.858649e-43) 2207; R600-NEXT: 102(1.429324e-43), 381(5.338947e-43) 2208; R600-NEXT: ADD_INT T6.X, PS, literal.x, 2209; R600-NEXT: ADD_INT T5.Y, T1.Z, literal.y, 2210; R600-NEXT: SETGT_UINT T4.Z, T1.Z, literal.z, 2211; R600-NEXT: CNDE_INT T3.W, PV.W, PV.Y, PV.Z, 2212; R600-NEXT: SETGT_INT * T4.W, T1.Z, literal.y, 2213; R600-NEXT: -254(nan), -127(nan) 2214; R600-NEXT: 254(3.559298e-43), 0(0.000000e+00) 2215; R600-NEXT: CNDE_INT T7.X, PS, PV.W, T1.Z, BS:VEC_021/SCL_122 2216; R600-NEXT: CNDE_INT T4.Y, PV.Z, PV.Y, PV.X, 2217; R600-NEXT: SETGT_INT T1.Z, T1.Z, literal.x, BS:VEC_120/SCL_212 2218; R600-NEXT: CNDE_INT T0.W, T5.X, T2.Z, T0.W, BS:VEC_102/SCL_221 2219; R600-NEXT: SETGT_INT * T3.W, T0.Z, literal.y, 2220; R600-NEXT: 127(1.779649e-43), -127(nan) 2221; R600-NEXT: CNDE_INT T6.X, PS, PV.W, T0.Z, 2222; R600-NEXT: CNDE_INT T4.Y, PV.Z, PV.X, PV.Y, 2223; R600-NEXT: MIN_INT T2.Z, T0.Z, literal.x, 2224; R600-NEXT: MUL_IEEE T0.W, T3.Y, literal.y, 2225; R600-NEXT: MUL_IEEE * T5.W, T0.Y, literal.z, 2226; R600-NEXT: 381(5.338947e-43), 209715200(1.972152e-31) 2227; R600-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 2228; R600-NEXT: MUL_IEEE T7.X, PS, literal.x, 2229; R600-NEXT: CNDE_INT T3.Y, T2.W, PV.W, T3.Y, 2230; R600-NEXT: ADD_INT T2.Z, PV.Z, literal.y, 2231; R600-NEXT: ADD_INT T0.W, T0.Z, literal.z, 2232; R600-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w, 2233; R600-NEXT: 2130706432(1.701412e+38), -254(nan) 2234; R600-NEXT: -127(nan), 254(3.559298e-43) 2235; R600-NEXT: CNDE_INT T8.X, PS, PV.W, PV.Z, 2236; R600-NEXT: SETGT_INT T5.Y, T0.Z, literal.x, 2237; R600-NEXT: CNDE_INT T0.Z, T4.W, PV.Y, T0.Y, BS:VEC_021/SCL_122 2238; R600-NEXT: CNDE_INT T0.W, T4.Z, T5.W, PV.X, BS:VEC_120/SCL_212 2239; R600-NEXT: LSHL * T4.W, T4.Y, literal.y, 2240; R600-NEXT: 127(1.779649e-43), 23(3.222986e-44) 2241; R600-NEXT: ADD_INT T7.X, PS, literal.x, 2242; R600-NEXT: CNDE_INT T0.Y, T1.Z, PV.Z, PV.W, 2243; R600-NEXT: CNDE_INT T0.Z, PV.Y, T6.X, PV.X, 2244; R600-NEXT: MUL_IEEE T0.W, T4.X, literal.y, 2245; R600-NEXT: CNDE_INT * T1.W, T5.X, T2.Y, T1.W, 2246; R600-NEXT: 1065353216(1.000000e+00), 2130706432(1.701412e+38) 2247; R600-NEXT: CNDE_INT T5.X, T3.W, PS, T1.Y, 2248; R600-NEXT: CNDE_INT * T1.Y, T2.W, T4.X, PV.W, BS:VEC_120/SCL_212 2249; R600-NEXT: ALU clause starting at 201: 2250; R600-NEXT: LSHL T0.Z, T0.Z, literal.x, 2251; R600-NEXT: MUL_IEEE T0.W, T0.Y, T7.X, 2252; R600-NEXT: SETGT * T1.W, literal.y, KC0[3].W, 2253; R600-NEXT: 23(3.222986e-44), -1036817932(-4.485347e+01) 2254; R600-NEXT: CNDE T4.X, PS, PV.W, 0.0, 2255; R600-NEXT: SETGT T0.Y, KC0[3].W, literal.x, 2256; R600-NEXT: ADD_INT T0.Z, PV.Z, literal.y, 2257; R600-NEXT: CNDE_INT T0.W, T5.Y, T5.X, T1.Y, BS:VEC_102/SCL_221 2258; R600-NEXT: CNDE * T1.W, T0.X, T3.X, literal.z, 2259; R600-NEXT: 1109008539(3.853184e+01), 1065353216(1.000000e+00) 2260; R600-NEXT: 2139095040(INF), 0(0.000000e+00) 2261; R600-NEXT: MUL_IEEE T0.X, PV.W, PV.Z, 2262; R600-NEXT: SETGT T2.Y, literal.x, KC0[3].Y, 2263; R600-NEXT: CNDE T1.Z, PV.Y, PV.X, literal.y, 2264; R600-NEXT: CNDE T0.W, T2.X, T1.X, 0.0, 2265; R600-NEXT: SETGT * T2.W, KC0[3].Z, literal.z, 2266; R600-NEXT: -1036817932(-4.485347e+01), 2139095040(INF) 2267; R600-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00) 2268; R600-NEXT: CNDE T1.Y, PS, PV.W, literal.x, 2269; R600-NEXT: CNDE T0.W, PV.Y, PV.X, 0.0, 2270; R600-NEXT: SETGT * T2.W, KC0[3].Y, literal.y, 2271; R600-NEXT: 2139095040(INF), 1109008539(3.853184e+01) 2272; R600-NEXT: CNDE T1.X, PS, PV.W, literal.x, 2273; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.y, 2274; R600-NEXT: 2139095040(INF), 2(2.802597e-45) 2275; 2276; CM-LABEL: s_exp10_v4f32: 2277; CM: ; %bb.0: 2278; CM-NEXT: ALU 97, @6, KC0[CB0:0-32], KC1[] 2279; CM-NEXT: ALU 97, @104, KC0[CB0:0-32], KC1[] 2280; CM-NEXT: ALU 35, @202, KC0[CB0:0-32], KC1[] 2281; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X 2282; CM-NEXT: CF_END 2283; CM-NEXT: PAD 2284; CM-NEXT: ALU clause starting at 6: 2285; CM-NEXT: AND_INT * T0.W, KC0[3].Y, literal.x, 2286; CM-NEXT: -4096(nan), 0(0.000000e+00) 2287; CM-NEXT: ADD * T1.W, KC0[3].Y, -PV.W, 2288; CM-NEXT: MUL_IEEE T0.Y, PV.W, literal.x, 2289; CM-NEXT: MUL_IEEE T0.Z, T0.W, literal.y, 2290; CM-NEXT: AND_INT * T2.W, KC0[3].W, literal.z, 2291; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 2292; CM-NEXT: -4096(nan), 0(0.000000e+00) 2293; CM-NEXT: ADD T1.Y, KC0[3].W, -PV.W, 2294; CM-NEXT: RNDNE T1.Z, PV.Z, 2295; CM-NEXT: MULADD_IEEE * T1.W, T1.W, literal.x, PV.Y, 2296; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 2297; CM-NEXT: MULADD_IEEE T0.X, T0.W, literal.x, PV.W, 2298; CM-NEXT: ADD T0.Y, T0.Z, -PV.Z, 2299; CM-NEXT: MUL_IEEE T0.Z, T2.W, literal.y, BS:VEC_120/SCL_212 2300; CM-NEXT: MUL_IEEE * T0.W, PV.Y, literal.x, 2301; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 2302; CM-NEXT: TRUNC T1.X, T1.Z, 2303; CM-NEXT: MULADD_IEEE T1.Y, T1.Y, literal.x, PV.W, 2304; CM-NEXT: RNDNE T1.Z, PV.Z, 2305; CM-NEXT: ADD * T0.W, PV.Y, PV.X, 2306; CM-NEXT: 1079283712(3.321289e+00), 0(0.000000e+00) 2307; CM-NEXT: EXP_IEEE T0.X, T0.W, 2308; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W, 2309; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W, 2310; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W, 2311; CM-NEXT: TRUNC T2.X, T1.Z, 2312; CM-NEXT: MULADD_IEEE T0.Y, T2.W, literal.x, T1.Y, 2313; CM-NEXT: FLT_TO_INT T2.Z, T1.X, 2314; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y, 2315; CM-NEXT: 975668412(6.390323e-04), 209715200(1.972152e-31) 2316; CM-NEXT: ADD T1.X, T0.Z, -T1.Z, 2317; CM-NEXT: MUL_IEEE T1.Y, PV.W, literal.x, 2318; CM-NEXT: MAX_INT T0.Z, PV.Z, literal.y, 2319; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.z, 2320; CM-NEXT: 209715200(1.972152e-31), -330(nan) 2321; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00) 2322; CM-NEXT: ADD_INT T3.X, PV.W, literal.x, 2323; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y, 2324; CM-NEXT: ADD_INT T0.Z, T2.Z, literal.z, 2325; CM-NEXT: SETGT_UINT * T1.W, T2.Z, literal.w, 2326; CM-NEXT: -254(nan), 204(2.858649e-43) 2327; CM-NEXT: 102(1.429324e-43), -229(nan) 2328; CM-NEXT: ADD_INT T4.X, T2.Z, literal.x, 2329; CM-NEXT: SETGT_UINT T3.Y, T2.Z, literal.y, 2330; CM-NEXT: CNDE_INT T0.Z, PV.W, PV.Y, PV.Z, 2331; CM-NEXT: SETGT_INT * T2.W, T2.Z, literal.x, 2332; CM-NEXT: -127(nan), 254(3.559298e-43) 2333; CM-NEXT: MUL_IEEE T5.X, T0.X, literal.x, 2334; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Z, T2.Z, 2335; CM-NEXT: CNDE_INT T0.Z, PV.Y, PV.X, T3.X, 2336; CM-NEXT: SETGT_INT * T3.W, T2.Z, literal.y, 2337; CM-NEXT: 2130706432(1.701412e+38), 127(1.779649e-43) 2338; CM-NEXT: AND_INT T3.X, KC0[3].Z, literal.x, 2339; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Y, PV.Z, 2340; CM-NEXT: MUL_IEEE T0.Z, PV.X, literal.y, 2341; CM-NEXT: CNDE_INT * T0.W, T1.W, T1.Y, T0.W, 2342; CM-NEXT: -4096(nan), 2130706432(1.701412e+38) 2343; CM-NEXT: CNDE_INT T0.X, T2.W, PV.W, T0.X, 2344; CM-NEXT: CNDE_INT T1.Y, T3.Y, T5.X, PV.Z, 2345; CM-NEXT: LSHL T0.Z, PV.Y, literal.x, 2346; CM-NEXT: MUL_IEEE * T0.W, PV.X, literal.y, 2347; CM-NEXT: 23(3.222986e-44), 1079283712(3.321289e+00) 2348; CM-NEXT: RNDNE T4.X, PV.W, 2349; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.x, 2350; CM-NEXT: CNDE_INT T0.Z, T3.W, PV.X, PV.Y, 2351; CM-NEXT: ADD * T1.W, T1.X, T0.Y, 2352; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00) 2353; CM-NEXT: EXP_IEEE T0.X, T1.W, 2354; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W, 2355; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W, 2356; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W, 2357; CM-NEXT: MUL_IEEE T1.X, T0.Z, T2.Y, 2358; CM-NEXT: TRUNC T0.Y, T4.X, 2359; CM-NEXT: FLT_TO_INT T0.Z, T2.X, BS:VEC_120/SCL_212 2360; CM-NEXT: MUL_IEEE * T1.W, PV.X, literal.x, 2361; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 2362; CM-NEXT: MUL_IEEE T2.X, PV.W, literal.x, 2363; CM-NEXT: MUL_IEEE T1.Y, T0.X, literal.y, 2364; CM-NEXT: MAX_INT T1.Z, PV.Z, literal.z, 2365; CM-NEXT: MIN_INT * T2.W, PV.Z, literal.w, 2366; CM-NEXT: 209715200(1.972152e-31), 2130706432(1.701412e+38) 2367; CM-NEXT: -330(nan), 381(5.338947e-43) 2368; CM-NEXT: ADD_INT T5.X, PV.W, literal.x, 2369; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y, 2370; CM-NEXT: ADD_INT T1.Z, T0.Z, literal.z, 2371; CM-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w, 2372; CM-NEXT: -254(nan), 204(2.858649e-43) 2373; CM-NEXT: 102(1.429324e-43), -229(nan) 2374; CM-NEXT: ADD_INT T6.X, T0.Z, literal.x, 2375; CM-NEXT: SETGT_UINT T3.Y, T0.Z, literal.y, 2376; CM-NEXT: CNDE_INT T1.Z, PV.W, PV.Y, PV.Z, 2377; CM-NEXT: SETGT_INT * T3.W, T0.Z, literal.x, 2378; CM-NEXT: -127(nan), 254(3.559298e-43) 2379; CM-NEXT: CNDE_INT T7.X, PV.W, PV.Z, T0.Z, 2380; CM-NEXT: CNDE_INT T2.Y, PV.Y, PV.X, T5.X, 2381; CM-NEXT: SETGT_INT * T0.Z, T0.Z, literal.x, 2382; CM-NEXT: 127(1.779649e-43), 0(0.000000e+00) 2383; CM-NEXT: ALU clause starting at 104: 2384; CM-NEXT: ADD * T4.W, KC0[3].Z, -T3.X, 2385; CM-NEXT: MUL_IEEE T5.X, PV.W, literal.x, 2386; CM-NEXT: CNDE_INT T2.Y, T0.Z, T7.X, T2.Y, 2387; CM-NEXT: MUL_IEEE T1.Z, T1.Y, literal.y, 2388; CM-NEXT: CNDE_INT * T1.W, T2.W, T2.X, T1.W, BS:VEC_021/SCL_122 2389; CM-NEXT: 975668412(6.390323e-04), 2130706432(1.701412e+38) 2390; CM-NEXT: CNDE_INT T0.X, T3.W, PV.W, T0.X, 2391; CM-NEXT: CNDE_INT T1.Y, T3.Y, T1.Y, PV.Z, 2392; CM-NEXT: LSHL T1.Z, PV.Y, literal.x, 2393; CM-NEXT: MULADD_IEEE * T1.W, T4.W, literal.y, PV.X, BS:VEC_120/SCL_212 2394; CM-NEXT: 23(3.222986e-44), 1079283712(3.321289e+00) 2395; CM-NEXT: MULADD_IEEE T2.X, T3.X, literal.x, PV.W, 2396; CM-NEXT: ADD T2.Y, T0.W, -T4.X, 2397; CM-NEXT: ADD_INT T1.Z, PV.Z, literal.y, 2398; CM-NEXT: CNDE_INT * T0.W, T0.Z, PV.X, PV.Y, 2399; CM-NEXT: 975668412(6.390323e-04), 1065353216(1.000000e+00) 2400; CM-NEXT: AND_INT T0.X, KC0[4].X, literal.x, 2401; CM-NEXT: MUL_IEEE T1.Y, PV.W, PV.Z, 2402; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].W, 2403; CM-NEXT: ADD * T0.W, PV.Y, PV.X, 2404; CM-NEXT: -4096(nan), -1036817932(-4.485347e+01) 2405; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W, 2406; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W, 2407; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W, 2408; CM-NEXT: EXP_IEEE * T0.W, T0.W, 2409; CM-NEXT: CNDE T2.X, T0.Z, T1.Y, 0.0, 2410; CM-NEXT: ADD T1.Y, KC0[4].X, -T0.X, 2411; CM-NEXT: FLT_TO_INT T0.Z, T0.Y, 2412; CM-NEXT: MUL_IEEE * T1.W, PV.W, literal.x, 2413; CM-NEXT: 209715200(1.972152e-31), 0(0.000000e+00) 2414; CM-NEXT: MUL_IEEE T3.X, PV.W, literal.x, 2415; CM-NEXT: SETGT_UINT T0.Y, PV.Z, literal.y, 2416; CM-NEXT: MUL_IEEE T1.Z, PV.Y, literal.z, 2417; CM-NEXT: MUL_IEEE * T2.W, T0.X, literal.w, 2418; CM-NEXT: 209715200(1.972152e-31), -229(nan) 2419; CM-NEXT: 975668412(6.390323e-04), 1079283712(3.321289e+00) 2420; CM-NEXT: RNDNE T4.X, PV.W, 2421; CM-NEXT: MULADD_IEEE T1.Y, T1.Y, literal.x, PV.Z, 2422; CM-NEXT: CNDE_INT T1.Z, PV.Y, PV.X, T1.W, 2423; CM-NEXT: SETGT_INT * T1.W, T0.Z, literal.y, 2424; CM-NEXT: 1079283712(3.321289e+00), -127(nan) 2425; CM-NEXT: CNDE_INT T3.X, PV.W, PV.Z, T0.W, 2426; CM-NEXT: MULADD_IEEE T1.Y, T0.X, literal.x, PV.Y, 2427; CM-NEXT: ADD T1.Z, T2.W, -PV.X, 2428; CM-NEXT: MAX_INT * T2.W, T0.Z, literal.y, 2429; CM-NEXT: 975668412(6.390323e-04), -330(nan) 2430; CM-NEXT: ADD_INT T0.X, PV.W, literal.x, 2431; CM-NEXT: ADD_INT T2.Y, T0.Z, literal.y, 2432; CM-NEXT: TRUNC T2.Z, T4.X, 2433; CM-NEXT: ADD * T2.W, PV.Z, PV.Y, 2434; CM-NEXT: 204(2.858649e-43), 102(1.429324e-43) 2435; CM-NEXT: EXP_IEEE T1.X (MASKED), T2.W, 2436; CM-NEXT: EXP_IEEE T1.Y, T2.W, 2437; CM-NEXT: EXP_IEEE T1.Z (MASKED), T2.W, 2438; CM-NEXT: EXP_IEEE * T1.W (MASKED), T2.W, 2439; CM-NEXT: MUL_IEEE T4.X, T0.W, literal.x, 2440; CM-NEXT: FLT_TO_INT T3.Y, T2.Z, 2441; CM-NEXT: MUL_IEEE T1.Z, PV.Y, literal.y, 2442; CM-NEXT: CNDE_INT * T0.W, T0.Y, T0.X, T2.Y, 2443; CM-NEXT: 2130706432(1.701412e+38), 209715200(1.972152e-31) 2444; CM-NEXT: CNDE_INT T0.X, T1.W, PV.W, T0.Z, 2445; CM-NEXT: MUL_IEEE T0.Y, PV.Z, literal.x, 2446; CM-NEXT: MAX_INT T2.Z, PV.Y, literal.y, 2447; CM-NEXT: MIN_INT * T0.W, PV.Y, literal.z, 2448; CM-NEXT: 209715200(1.972152e-31), -330(nan) 2449; CM-NEXT: 381(5.338947e-43), 0(0.000000e+00) 2450; CM-NEXT: ADD_INT T5.X, PV.W, literal.x, 2451; CM-NEXT: ADD_INT T2.Y, PV.Z, literal.y, 2452; CM-NEXT: ADD_INT T2.Z, T3.Y, literal.z, 2453; CM-NEXT: SETGT_UINT * T0.W, T3.Y, literal.w, 2454; CM-NEXT: -254(nan), 204(2.858649e-43) 2455; CM-NEXT: 102(1.429324e-43), -229(nan) 2456; CM-NEXT: ADD_INT T6.X, T3.Y, literal.x, 2457; CM-NEXT: SETGT_UINT T4.Y, T3.Y, literal.y, 2458; CM-NEXT: CNDE_INT T2.Z, PV.W, PV.Y, PV.Z, 2459; CM-NEXT: SETGT_INT * T1.W, T3.Y, literal.x, 2460; CM-NEXT: -127(nan), 254(3.559298e-43) 2461; CM-NEXT: MUL_IEEE T7.X, T1.Y, literal.x, 2462; CM-NEXT: CNDE_INT T2.Y, PV.W, PV.Z, T3.Y, 2463; CM-NEXT: CNDE_INT T2.Z, PV.Y, PV.X, T5.X, 2464; CM-NEXT: MIN_INT * T2.W, T0.Z, literal.y, 2465; CM-NEXT: 2130706432(1.701412e+38), 381(5.338947e-43) 2466; CM-NEXT: SETGT_INT T5.X, T3.Y, literal.x, 2467; CM-NEXT: ADD_INT T3.Y, PV.W, literal.y, 2468; CM-NEXT: ADD_INT T3.Z, T0.Z, literal.z, 2469; CM-NEXT: SETGT_UINT * T2.W, T0.Z, literal.w, 2470; CM-NEXT: 127(1.779649e-43), -254(nan) 2471; CM-NEXT: -127(nan), 254(3.559298e-43) 2472; CM-NEXT: CNDE_INT T6.X, PV.W, PV.Z, PV.Y, 2473; CM-NEXT: CNDE_INT T2.Y, PV.X, T2.Y, T2.Z, 2474; CM-NEXT: MUL_IEEE T2.Z, T7.X, literal.x, 2475; CM-NEXT: CNDE_INT * T0.W, T0.W, T0.Y, T1.Z, BS:VEC_021/SCL_122 2476; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 2477; CM-NEXT: SETGT_INT T8.X, T0.Z, literal.x, 2478; CM-NEXT: CNDE_INT T0.Y, T1.W, PV.W, T1.Y, 2479; CM-NEXT: CNDE_INT T0.Z, T4.Y, T7.X, PV.Z, 2480; CM-NEXT: LSHL * T0.W, PV.Y, literal.y, 2481; CM-NEXT: 127(1.779649e-43), 23(3.222986e-44) 2482; CM-NEXT: ALU clause starting at 202: 2483; CM-NEXT: ADD_INT T7.X, T0.W, literal.x, 2484; CM-NEXT: CNDE_INT * T0.Y, T5.X, T0.Y, T0.Z, 2485; CM-NEXT: 1065353216(1.000000e+00), 0(0.000000e+00) 2486; CM-NEXT: CNDE_INT * T0.Z, T8.X, T0.X, T6.X, 2487; CM-NEXT: MUL_IEEE * T0.W, T4.X, literal.x, 2488; CM-NEXT: 2130706432(1.701412e+38), 0(0.000000e+00) 2489; CM-NEXT: CNDE_INT T0.X, T2.W, T4.X, PV.W, 2490; CM-NEXT: LSHL T1.Y, T0.Z, literal.x, 2491; CM-NEXT: MUL_IEEE T0.Z, T0.Y, T7.X, BS:VEC_021/SCL_122 2492; CM-NEXT: SETGT * T0.W, literal.y, KC0[4].X, 2493; CM-NEXT: 23(3.222986e-44), -1036817932(-4.485347e+01) 2494; CM-NEXT: CNDE T4.X, PV.W, PV.Z, 0.0, 2495; CM-NEXT: SETGT T0.Y, KC0[4].X, literal.x, 2496; CM-NEXT: ADD_INT T0.Z, PV.Y, literal.y, 2497; CM-NEXT: CNDE_INT * T0.W, T8.X, T3.X, PV.X, 2498; CM-NEXT: 1109008539(3.853184e+01), 1065353216(1.000000e+00) 2499; CM-NEXT: SETGT T0.X, KC0[3].W, literal.x, 2500; CM-NEXT: MUL_IEEE T1.Y, PV.W, PV.Z, 2501; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z, 2502; CM-NEXT: CNDE * T0.W, PV.Y, PV.X, literal.z, 2503; CM-NEXT: 1109008539(3.853184e+01), -1036817932(-4.485347e+01) 2504; CM-NEXT: 2139095040(INF), 0(0.000000e+00) 2505; CM-NEXT: SETGT T3.X, literal.x, KC0[3].Y, 2506; CM-NEXT: CNDE T0.Y, PV.Z, PV.Y, 0.0, 2507; CM-NEXT: CNDE T0.Z, PV.X, T2.X, literal.y, 2508; CM-NEXT: SETGT * T1.W, KC0[3].Z, literal.z, 2509; CM-NEXT: -1036817932(-4.485347e+01), 2139095040(INF) 2510; CM-NEXT: 1109008539(3.853184e+01), 0(0.000000e+00) 2511; CM-NEXT: CNDE T0.Y, PV.W, PV.Y, literal.x, 2512; CM-NEXT: CNDE T1.Z, PV.X, T1.X, 0.0, 2513; CM-NEXT: SETGT * T1.W, KC0[3].Y, literal.y, 2514; CM-NEXT: 2139095040(INF), 1109008539(3.853184e+01) 2515; CM-NEXT: CNDE * T0.X, PV.W, PV.Z, literal.x, 2516; CM-NEXT: 2139095040(INF), 0(0.000000e+00) 2517; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 2518; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2519 %result = call <4 x float> @llvm.exp10.v4f32(<4 x float> %in) 2520 store <4 x float> %result, ptr addrspace(1) %out 2521 ret void 2522} 2523 2524define float @v_exp10_f32(float %in) { 2525; VI-SDAG-LABEL: v_exp10_f32: 2526; VI-SDAG: ; %bb.0: 2527; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2528; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 2529; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 2530; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 2531; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 2532; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 2533; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 2534; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 2535; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 2536; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 2537; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 2538; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 2539; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 2540; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 2541; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 2542; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 2543; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 2544; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 2545; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2546; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2547; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 2548; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2549; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 2550; 2551; VI-GISEL-LABEL: v_exp10_f32: 2552; VI-GISEL: ; %bb.0: 2553; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2554; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 2555; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 2556; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 2557; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 2558; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 2559; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 2560; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 2561; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 2562; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 2563; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 2564; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 2565; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 2566; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 2567; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2568; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 2569; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2570; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 2571; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2572; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 2573; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 2574; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2575; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 2576; 2577; GFX900-SDAG-LABEL: v_exp10_f32: 2578; GFX900-SDAG: ; %bb.0: 2579; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2580; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 2581; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 2582; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 2583; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 2584; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 2585; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 2586; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 2587; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 2588; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 2589; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 2590; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 2591; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 2592; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 2593; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 2594; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2595; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2596; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 2597; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2598; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 2599; 2600; GFX900-GISEL-LABEL: v_exp10_f32: 2601; GFX900-GISEL: ; %bb.0: 2602; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2603; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 2604; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 2605; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 2606; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 2607; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 2608; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 2609; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 2610; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 2611; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 2612; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 2613; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2614; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 2615; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2616; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 2617; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2618; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 2619; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 2620; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2621; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 2622; 2623; SI-SDAG-LABEL: v_exp10_f32: 2624; SI-SDAG: ; %bb.0: 2625; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2626; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 2627; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 2628; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 2629; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 2630; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 2631; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 2632; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 2633; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 2634; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 2635; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 2636; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 2637; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 2638; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 2639; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 2640; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2641; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2642; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 2643; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2644; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 2645; 2646; SI-GISEL-LABEL: v_exp10_f32: 2647; SI-GISEL: ; %bb.0: 2648; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2649; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 2650; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 2651; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 2652; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 2653; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 2654; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 2655; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 2656; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 2657; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 2658; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 2659; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2660; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 2661; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2662; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 2663; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2664; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 2665; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 2666; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2667; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 2668; 2669; R600-LABEL: v_exp10_f32: 2670; R600: ; %bb.0: 2671; R600-NEXT: CF_END 2672; R600-NEXT: PAD 2673; 2674; CM-LABEL: v_exp10_f32: 2675; CM: ; %bb.0: 2676; CM-NEXT: CF_END 2677; CM-NEXT: PAD 2678 %result = call float @llvm.exp10.f32(float %in) 2679 ret float %result 2680} 2681 2682define float @v_exp10_fabs_f32(float %in) { 2683; VI-SDAG-LABEL: v_exp10_fabs_f32: 2684; VI-SDAG: ; %bb.0: 2685; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2686; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0 2687; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1 2688; VI-SDAG-NEXT: v_sub_f32_e64 v4, |v0|, v1 2689; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 2690; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 2691; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 2692; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 2693; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 2694; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 2695; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 2696; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 2697; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 2698; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 2699; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 2700; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 2701; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4 2702; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 2703; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 2704; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2705; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2706; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4 2707; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2708; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 2709; 2710; VI-GISEL-LABEL: v_exp10_fabs_f32: 2711; VI-GISEL: ; %bb.0: 2712; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2713; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0 2714; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1 2715; VI-GISEL-NEXT: v_sub_f32_e64 v2, |v0|, v1 2716; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 2717; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 2718; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 2719; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 2720; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 2721; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 2722; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 2723; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 2724; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 2725; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 2726; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 2727; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2728; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 2729; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2730; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2 2731; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2732; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 2733; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2 2734; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2735; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 2736; 2737; GFX900-SDAG-LABEL: v_exp10_fabs_f32: 2738; GFX900-SDAG: ; %bb.0: 2739; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2740; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 2741; GFX900-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4 2742; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 2743; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 2744; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v1 2745; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 2746; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v1 2747; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 2748; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 2749; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 2750; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 2751; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4 2752; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 2753; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 2754; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2755; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2756; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4 2757; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2758; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 2759; 2760; GFX900-GISEL-LABEL: v_exp10_fabs_f32: 2761; GFX900-GISEL: ; %bb.0: 2762; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2763; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 2764; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, |v0|, v1 2765; GFX900-GISEL-NEXT: v_fma_f32 v1, |v0|, v1, -v2 2766; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 2767; GFX900-GISEL-NEXT: v_fma_f32 v1, |v0|, v3, v1 2768; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 2769; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 2770; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 2771; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 2772; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 2773; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2774; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 2775; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2776; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2 2777; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2778; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 2779; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2 2780; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2781; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 2782; 2783; SI-SDAG-LABEL: v_exp10_fabs_f32: 2784; SI-SDAG: ; %bb.0: 2785; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2786; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 2787; SI-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4 2788; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 2789; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 2790; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v1 2791; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 2792; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v1 2793; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 2794; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 2795; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 2796; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 2797; SI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4 2798; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 2799; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 2800; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2801; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2802; SI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4 2803; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2804; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 2805; 2806; SI-GISEL-LABEL: v_exp10_fabs_f32: 2807; SI-GISEL: ; %bb.0: 2808; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2809; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 2810; SI-GISEL-NEXT: v_mul_f32_e64 v2, |v0|, v1 2811; SI-GISEL-NEXT: v_fma_f32 v1, |v0|, v1, -v2 2812; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 2813; SI-GISEL-NEXT: v_fma_f32 v1, |v0|, v3, v1 2814; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 2815; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 2816; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 2817; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 2818; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 2819; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2820; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 2821; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2822; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2 2823; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2824; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 2825; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2 2826; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2827; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 2828; 2829; R600-LABEL: v_exp10_fabs_f32: 2830; R600: ; %bb.0: 2831; R600-NEXT: CF_END 2832; R600-NEXT: PAD 2833; 2834; CM-LABEL: v_exp10_fabs_f32: 2835; CM: ; %bb.0: 2836; CM-NEXT: CF_END 2837; CM-NEXT: PAD 2838 %fabs = call float @llvm.fabs.f32(float %in) 2839 %result = call float @llvm.exp10.f32(float %fabs) 2840 ret float %result 2841} 2842 2843define float @v_exp10_fneg_fabs_f32(float %in) { 2844; VI-SDAG-LABEL: v_exp10_fneg_fabs_f32: 2845; VI-SDAG: ; %bb.0: 2846; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2847; VI-SDAG-NEXT: v_or_b32_e32 v1, 0x80000000, v0 2848; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1 2849; VI-SDAG-NEXT: v_sub_f32_e64 v4, -|v0|, v1 2850; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 2851; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 2852; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 2853; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 2854; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 2855; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 2856; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 2857; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 2858; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 2859; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 2860; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 2861; VI-SDAG-NEXT: s_mov_b32 s4, 0x423369f4 2862; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4 2863; VI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b 2864; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 2865; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2866; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2867; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4 2868; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2869; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 2870; 2871; VI-GISEL-LABEL: v_exp10_fneg_fabs_f32: 2872; VI-GISEL: ; %bb.0: 2873; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2874; VI-GISEL-NEXT: v_or_b32_e32 v1, 0x80000000, v0 2875; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1 2876; VI-GISEL-NEXT: v_sub_f32_e64 v2, -|v0|, v1 2877; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 2878; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 2879; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 2880; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 2881; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 2882; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 2883; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 2884; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 2885; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 2886; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 2887; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 2888; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2889; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 2890; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2891; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v2 2892; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2893; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 2894; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v2 2895; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2896; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 2897; 2898; GFX900-SDAG-LABEL: v_exp10_fneg_fabs_f32: 2899; GFX900-SDAG: ; %bb.0: 2900; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2901; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc0549a78 2902; GFX900-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4 2903; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 2904; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 2905; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v1 2906; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xb3979a37 2907; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v1 2908; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 2909; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 2910; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 2911; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x423369f4 2912; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4 2913; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b 2914; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 2915; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2916; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2917; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4 2918; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2919; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 2920; 2921; GFX900-GISEL-LABEL: v_exp10_fneg_fabs_f32: 2922; GFX900-GISEL: ; %bb.0: 2923; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2924; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 2925; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, -|v0|, v1 2926; GFX900-GISEL-NEXT: v_fma_f32 v1, -|v0|, v1, -v2 2927; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 2928; GFX900-GISEL-NEXT: v_fma_f32 v1, -|v0|, v3, v1 2929; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 2930; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 2931; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 2932; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 2933; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 2934; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2935; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 2936; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2937; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v2 2938; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2939; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 2940; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v2 2941; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2942; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 2943; 2944; SI-SDAG-LABEL: v_exp10_fneg_fabs_f32: 2945; SI-SDAG: ; %bb.0: 2946; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2947; SI-SDAG-NEXT: s_mov_b32 s4, 0xc0549a78 2948; SI-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4 2949; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 2950; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 2951; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v1 2952; SI-SDAG-NEXT: s_mov_b32 s4, 0xb3979a37 2953; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v1 2954; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 2955; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 2956; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 2957; SI-SDAG-NEXT: s_mov_b32 s4, 0x423369f4 2958; SI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4 2959; SI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b 2960; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 2961; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 2962; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 2963; SI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4 2964; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 2965; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 2966; 2967; SI-GISEL-LABEL: v_exp10_fneg_fabs_f32: 2968; SI-GISEL: ; %bb.0: 2969; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2970; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 2971; SI-GISEL-NEXT: v_mul_f32_e64 v2, -|v0|, v1 2972; SI-GISEL-NEXT: v_fma_f32 v1, -|v0|, v1, -v2 2973; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 2974; SI-GISEL-NEXT: v_fma_f32 v1, -|v0|, v3, v1 2975; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 2976; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 2977; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 2978; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 2979; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 2980; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 2981; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 2982; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 2983; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -|v0|, v2 2984; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 2985; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 2986; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -|v0|, v2 2987; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 2988; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 2989; 2990; R600-LABEL: v_exp10_fneg_fabs_f32: 2991; R600: ; %bb.0: 2992; R600-NEXT: CF_END 2993; R600-NEXT: PAD 2994; 2995; CM-LABEL: v_exp10_fneg_fabs_f32: 2996; CM: ; %bb.0: 2997; CM-NEXT: CF_END 2998; CM-NEXT: PAD 2999 %fabs = call float @llvm.fabs.f32(float %in) 3000 %fneg.fabs = fneg float %fabs 3001 %result = call float @llvm.exp10.f32(float %fneg.fabs) 3002 ret float %result 3003} 3004 3005define float @v_exp10_fneg_f32(float %in) { 3006; VI-SDAG-LABEL: v_exp10_fneg_f32: 3007; VI-SDAG: ; %bb.0: 3008; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3009; VI-SDAG-NEXT: v_xor_b32_e32 v1, 0x80000000, v0 3010; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1 3011; VI-SDAG-NEXT: v_sub_f32_e64 v4, -v0, v1 3012; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 3013; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 3014; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 3015; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 3016; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 3017; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3018; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 3019; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 3020; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 3021; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3022; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 3023; VI-SDAG-NEXT: s_mov_b32 s4, 0x423369f4 3024; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 3025; VI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b 3026; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 3027; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 3028; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 3029; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3030; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 3031; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 3032; 3033; VI-GISEL-LABEL: v_exp10_fneg_f32: 3034; VI-GISEL: ; %bb.0: 3035; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3036; VI-GISEL-NEXT: v_xor_b32_e32 v1, 0x80000000, v0 3037; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1 3038; VI-GISEL-NEXT: v_sub_f32_e64 v2, -v0, v1 3039; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 3040; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 3041; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 3042; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 3043; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3044; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 3045; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 3046; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 3047; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 3048; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 3049; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 3050; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 3051; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 3052; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3053; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v2 3054; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 3055; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 3056; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v2 3057; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 3058; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 3059; 3060; GFX900-SDAG-LABEL: v_exp10_fneg_f32: 3061; GFX900-SDAG: ; %bb.0: 3062; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3063; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0xc0549a78, v0 3064; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc0549a78 3065; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 3066; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 3067; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 3068; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xb3979a37 3069; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 3070; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 3071; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 3072; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 3073; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x423369f4 3074; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 3075; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b 3076; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 3077; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 3078; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 3079; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3080; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 3081; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 3082; 3083; GFX900-GISEL-LABEL: v_exp10_fneg_f32: 3084; GFX900-GISEL: ; %bb.0: 3085; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3086; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 3087; GFX900-GISEL-NEXT: v_mul_f32_e64 v2, -v0, v1 3088; GFX900-GISEL-NEXT: v_fma_f32 v1, -v0, v1, -v2 3089; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 3090; GFX900-GISEL-NEXT: v_fma_f32 v1, -v0, v3, v1 3091; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 3092; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 3093; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 3094; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 3095; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 3096; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 3097; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 3098; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3099; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v2 3100; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 3101; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 3102; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v2 3103; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 3104; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 3105; 3106; SI-SDAG-LABEL: v_exp10_fneg_f32: 3107; SI-SDAG: ; %bb.0: 3108; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3109; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xc0549a78, v0 3110; SI-SDAG-NEXT: s_mov_b32 s4, 0xc0549a78 3111; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 3112; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 3113; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 3114; SI-SDAG-NEXT: s_mov_b32 s4, 0xb3979a37 3115; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 3116; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 3117; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3118; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 3119; SI-SDAG-NEXT: s_mov_b32 s4, 0x423369f4 3120; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 3121; SI-SDAG-NEXT: s_mov_b32 s4, 0xc21a209b 3122; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 3123; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 3124; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 3125; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3126; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 3127; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3128; 3129; SI-GISEL-LABEL: v_exp10_fneg_f32: 3130; SI-GISEL: ; %bb.0: 3131; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3132; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 3133; SI-GISEL-NEXT: v_mul_f32_e64 v2, -v0, v1 3134; SI-GISEL-NEXT: v_fma_f32 v1, -v0, v1, -v2 3135; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 3136; SI-GISEL-NEXT: v_fma_f32 v1, -v0, v3, v1 3137; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 3138; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 3139; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 3140; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 3141; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 3142; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 3143; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 3144; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3145; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], -v0, v2 3146; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 3147; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] 3148; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, -v0, v2 3149; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 3150; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3151; 3152; R600-LABEL: v_exp10_fneg_f32: 3153; R600: ; %bb.0: 3154; R600-NEXT: CF_END 3155; R600-NEXT: PAD 3156; 3157; CM-LABEL: v_exp10_fneg_f32: 3158; CM: ; %bb.0: 3159; CM-NEXT: CF_END 3160; CM-NEXT: PAD 3161 %fneg = fneg float %in 3162 %result = call float @llvm.exp10.f32(float %fneg) 3163 ret float %result 3164} 3165 3166define float @v_exp10_f32_fast(float %in) { 3167; GCN-SDAG-LABEL: v_exp10_f32_fast: 3168; GCN-SDAG: ; %bb.0: 3169; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3170; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3171; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3172; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3173; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3174; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3175; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3176; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 3177; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 3178; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3179; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3180; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3181; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 3182; 3183; GCN-GISEL-LABEL: v_exp10_f32_fast: 3184; GCN-GISEL: ; %bb.0: 3185; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3186; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3187; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3188; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3189; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3190; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3191; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 3192; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3193; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3194; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 3195; 3196; SI-SDAG-LABEL: v_exp10_f32_fast: 3197; SI-SDAG: ; %bb.0: 3198; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3199; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3200; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3201; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3202; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3203; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3204; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3205; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3206; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 3207; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3208; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3209; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3210; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3211; 3212; SI-GISEL-LABEL: v_exp10_f32_fast: 3213; SI-GISEL: ; %bb.0: 3214; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3215; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3216; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3217; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3218; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3219; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3220; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 3221; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3222; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3223; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3224; 3225; R600-LABEL: v_exp10_f32_fast: 3226; R600: ; %bb.0: 3227; R600-NEXT: CF_END 3228; R600-NEXT: PAD 3229; 3230; CM-LABEL: v_exp10_f32_fast: 3231; CM: ; %bb.0: 3232; CM-NEXT: CF_END 3233; CM-NEXT: PAD 3234 %result = call fast float @llvm.exp10.f32(float %in) 3235 ret float %result 3236} 3237 3238define float @v_exp10_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { 3239; GCN-SDAG-LABEL: v_exp10_f32_unsafe_math_attr: 3240; GCN-SDAG: ; %bb.0: 3241; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3242; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3243; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3244; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3245; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3246; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3247; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3248; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 3249; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 3250; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3251; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3252; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3253; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 3254; 3255; GCN-GISEL-LABEL: v_exp10_f32_unsafe_math_attr: 3256; GCN-GISEL: ; %bb.0: 3257; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3258; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3259; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3260; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3261; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3262; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3263; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 3264; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3265; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3266; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 3267; 3268; SI-SDAG-LABEL: v_exp10_f32_unsafe_math_attr: 3269; SI-SDAG: ; %bb.0: 3270; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3271; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3272; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3273; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3274; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3275; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3276; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3277; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3278; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 3279; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3280; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3281; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3282; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3283; 3284; SI-GISEL-LABEL: v_exp10_f32_unsafe_math_attr: 3285; SI-GISEL: ; %bb.0: 3286; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3287; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3288; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3289; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3290; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3291; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3292; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 3293; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3294; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3295; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3296; 3297; R600-LABEL: v_exp10_f32_unsafe_math_attr: 3298; R600: ; %bb.0: 3299; R600-NEXT: CF_END 3300; R600-NEXT: PAD 3301; 3302; CM-LABEL: v_exp10_f32_unsafe_math_attr: 3303; CM: ; %bb.0: 3304; CM-NEXT: CF_END 3305; CM-NEXT: PAD 3306 %result = call float @llvm.exp10.f32(float %in) 3307 ret float %result 3308} 3309 3310define float @v_exp10_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" { 3311; GCN-SDAG-LABEL: v_exp10_f32_approx_fn_attr: 3312; GCN-SDAG: ; %bb.0: 3313; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3314; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3315; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3316; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3317; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3318; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3319; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3320; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 3321; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 3322; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3323; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3324; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3325; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 3326; 3327; GCN-GISEL-LABEL: v_exp10_f32_approx_fn_attr: 3328; GCN-GISEL: ; %bb.0: 3329; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3330; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3331; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3332; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3333; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3334; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3335; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 3336; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3337; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3338; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 3339; 3340; SI-SDAG-LABEL: v_exp10_f32_approx_fn_attr: 3341; SI-SDAG: ; %bb.0: 3342; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3343; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3344; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3345; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3346; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3347; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3348; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3349; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3350; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 3351; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3352; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3353; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3354; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3355; 3356; SI-GISEL-LABEL: v_exp10_f32_approx_fn_attr: 3357; SI-GISEL: ; %bb.0: 3358; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3359; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3360; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3361; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3362; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3363; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3364; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 3365; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3366; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3367; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3368; 3369; R600-LABEL: v_exp10_f32_approx_fn_attr: 3370; R600: ; %bb.0: 3371; R600-NEXT: CF_END 3372; R600-NEXT: PAD 3373; 3374; CM-LABEL: v_exp10_f32_approx_fn_attr: 3375; CM: ; %bb.0: 3376; CM-NEXT: CF_END 3377; CM-NEXT: PAD 3378 %result = call float @llvm.exp10.f32(float %in) 3379 ret float %result 3380} 3381 3382define float @v_exp10_f32_ninf(float %in) { 3383; VI-SDAG-LABEL: v_exp10_f32_ninf: 3384; VI-SDAG: ; %bb.0: 3385; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3386; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 3387; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 3388; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 3389; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 3390; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 3391; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 3392; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 3393; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3394; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 3395; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 3396; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 3397; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3398; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 3399; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 3400; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3401; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 3402; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 3403; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 3404; 3405; VI-GISEL-LABEL: v_exp10_f32_ninf: 3406; VI-GISEL: ; %bb.0: 3407; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3408; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 3409; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 3410; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 3411; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 3412; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 3413; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 3414; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3415; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 3416; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 3417; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 3418; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 3419; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 3420; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 3421; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 3422; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3423; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 3424; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 3425; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 3426; 3427; GFX900-SDAG-LABEL: v_exp10_f32_ninf: 3428; GFX900-SDAG: ; %bb.0: 3429; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3430; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 3431; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 3432; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 3433; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 3434; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 3435; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 3436; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 3437; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 3438; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 3439; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 3440; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 3441; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3442; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 3443; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 3444; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 3445; 3446; GFX900-GISEL-LABEL: v_exp10_f32_ninf: 3447; GFX900-GISEL: ; %bb.0: 3448; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3449; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 3450; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 3451; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 3452; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 3453; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 3454; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 3455; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 3456; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 3457; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 3458; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 3459; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 3460; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3461; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 3462; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 3463; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 3464; 3465; SI-SDAG-LABEL: v_exp10_f32_ninf: 3466; SI-SDAG: ; %bb.0: 3467; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3468; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 3469; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 3470; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 3471; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 3472; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 3473; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 3474; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 3475; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 3476; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3477; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 3478; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 3479; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3480; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 3481; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 3482; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3483; 3484; SI-GISEL-LABEL: v_exp10_f32_ninf: 3485; SI-GISEL: ; %bb.0: 3486; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3487; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 3488; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 3489; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 3490; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 3491; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 3492; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 3493; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 3494; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 3495; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 3496; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 3497; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 3498; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3499; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 3500; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 3501; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3502; 3503; R600-LABEL: v_exp10_f32_ninf: 3504; R600: ; %bb.0: 3505; R600-NEXT: CF_END 3506; R600-NEXT: PAD 3507; 3508; CM-LABEL: v_exp10_f32_ninf: 3509; CM: ; %bb.0: 3510; CM-NEXT: CF_END 3511; CM-NEXT: PAD 3512 %result = call ninf float @llvm.exp10.f32(float %in) 3513 ret float %result 3514} 3515 3516define float @v_exp10_f32_afn(float %in) { 3517; GCN-SDAG-LABEL: v_exp10_f32_afn: 3518; GCN-SDAG: ; %bb.0: 3519; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3520; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3521; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3522; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3523; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3524; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3525; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3526; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 3527; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 3528; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3529; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3530; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3531; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 3532; 3533; GCN-GISEL-LABEL: v_exp10_f32_afn: 3534; GCN-GISEL: ; %bb.0: 3535; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3536; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3537; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3538; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3539; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3540; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3541; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 3542; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3543; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3544; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 3545; 3546; SI-SDAG-LABEL: v_exp10_f32_afn: 3547; SI-SDAG: ; %bb.0: 3548; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3549; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3550; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3551; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3552; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3553; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3554; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3555; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3556; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 3557; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3558; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3559; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3560; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3561; 3562; SI-GISEL-LABEL: v_exp10_f32_afn: 3563; SI-GISEL: ; %bb.0: 3564; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3565; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3566; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3567; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3568; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3569; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3570; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 3571; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3572; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3573; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3574; 3575; R600-LABEL: v_exp10_f32_afn: 3576; R600: ; %bb.0: 3577; R600-NEXT: CF_END 3578; R600-NEXT: PAD 3579; 3580; CM-LABEL: v_exp10_f32_afn: 3581; CM: ; %bb.0: 3582; CM-NEXT: CF_END 3583; CM-NEXT: PAD 3584 %result = call afn float @llvm.exp10.f32(float %in) 3585 ret float %result 3586} 3587 3588define float @v_exp10_f32_afn_daz(float %in) #0 { 3589; GCN-SDAG-LABEL: v_exp10_f32_afn_daz: 3590; GCN-SDAG: ; %bb.0: 3591; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3592; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3593; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3594; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 3595; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 3596; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3597; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 3598; 3599; GCN-GISEL-LABEL: v_exp10_f32_afn_daz: 3600; GCN-GISEL: ; %bb.0: 3601; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3602; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3603; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 3604; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 3605; 3606; SI-SDAG-LABEL: v_exp10_f32_afn_daz: 3607; SI-SDAG: ; %bb.0: 3608; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3609; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3610; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3611; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3612; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 3613; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3614; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3615; 3616; SI-GISEL-LABEL: v_exp10_f32_afn_daz: 3617; SI-GISEL: ; %bb.0: 3618; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3619; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3620; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 3621; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3622; 3623; R600-LABEL: v_exp10_f32_afn_daz: 3624; R600: ; %bb.0: 3625; R600-NEXT: CF_END 3626; R600-NEXT: PAD 3627; 3628; CM-LABEL: v_exp10_f32_afn_daz: 3629; CM: ; %bb.0: 3630; CM-NEXT: CF_END 3631; CM-NEXT: PAD 3632 %result = call afn float @llvm.exp10.f32(float %in) 3633 ret float %result 3634} 3635 3636define float @v_exp10_f32_afn_dynamic(float %in) #1 { 3637; GCN-SDAG-LABEL: v_exp10_f32_afn_dynamic: 3638; GCN-SDAG: ; %bb.0: 3639; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3640; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3641; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3642; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3643; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3644; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3645; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3646; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 3647; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 3648; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3649; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3650; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3651; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 3652; 3653; GCN-GISEL-LABEL: v_exp10_f32_afn_dynamic: 3654; GCN-GISEL: ; %bb.0: 3655; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3656; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3657; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3658; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3659; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3660; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3661; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 3662; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3663; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3664; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 3665; 3666; SI-SDAG-LABEL: v_exp10_f32_afn_dynamic: 3667; SI-SDAG: ; %bb.0: 3668; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3669; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3670; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 3671; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 3672; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3673; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3674; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3675; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3676; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 3677; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3678; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3679; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3680; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3681; 3682; SI-GISEL-LABEL: v_exp10_f32_afn_dynamic: 3683; SI-GISEL: ; %bb.0: 3684; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3685; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3686; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0 3687; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 3688; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 3689; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3690; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 3691; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3692; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3693; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3694; 3695; R600-LABEL: v_exp10_f32_afn_dynamic: 3696; R600: ; %bb.0: 3697; R600-NEXT: CF_END 3698; R600-NEXT: PAD 3699; 3700; CM-LABEL: v_exp10_f32_afn_dynamic: 3701; CM: ; %bb.0: 3702; CM-NEXT: CF_END 3703; CM-NEXT: PAD 3704 %result = call afn float @llvm.exp10.f32(float %in) 3705 ret float %result 3706} 3707 3708define float @v_fabs_exp10_f32_afn(float %in) { 3709; GCN-SDAG-LABEL: v_fabs_exp10_f32_afn: 3710; GCN-SDAG: ; %bb.0: 3711; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3712; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3713; GCN-SDAG-NEXT: s_mov_b32 s5, 0x42000000 3714; GCN-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5 3715; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 3716; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc 3717; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3718; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3719; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 3720; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 3721; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3722; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3723; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3724; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 3725; 3726; GCN-GISEL-LABEL: v_fabs_exp10_f32_afn: 3727; GCN-GISEL: ; %bb.0: 3728; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3729; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3730; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 3731; GCN-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2 3732; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 3733; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc 3734; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3735; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 3736; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3737; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3738; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 3739; 3740; SI-SDAG-LABEL: v_fabs_exp10_f32_afn: 3741; SI-SDAG: ; %bb.0: 3742; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3743; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 3744; SI-SDAG-NEXT: s_mov_b32 s5, 0x42000000 3745; SI-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5 3746; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 3747; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc 3748; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 3749; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 3750; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3751; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 3752; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 3753; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 3754; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3755; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3756; 3757; SI-GISEL-LABEL: v_fabs_exp10_f32_afn: 3758; SI-GISEL: ; %bb.0: 3759; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3760; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50 3761; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 3762; SI-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2 3763; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 3764; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc 3765; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 3766; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 3767; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0 3768; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 3769; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3770; 3771; R600-LABEL: v_fabs_exp10_f32_afn: 3772; R600: ; %bb.0: 3773; R600-NEXT: CF_END 3774; R600-NEXT: PAD 3775; 3776; CM-LABEL: v_fabs_exp10_f32_afn: 3777; CM: ; %bb.0: 3778; CM-NEXT: CF_END 3779; CM-NEXT: PAD 3780 %fabs = call float @llvm.fabs.f32(float %in) 3781 %result = call afn float @llvm.exp10.f32(float %fabs) 3782 ret float %result 3783} 3784 3785define float @v_exp10_f32_daz(float %in) #0 { 3786; VI-SDAG-LABEL: v_exp10_f32_daz: 3787; VI-SDAG: ; %bb.0: 3788; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3789; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 3790; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 3791; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 3792; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 3793; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 3794; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 3795; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 3796; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3797; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 3798; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 3799; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 3800; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3801; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 3802; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 3803; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3804; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 3805; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 3806; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 3807; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 3808; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 3809; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 3810; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 3811; 3812; VI-GISEL-LABEL: v_exp10_f32_daz: 3813; VI-GISEL: ; %bb.0: 3814; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3815; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 3816; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 3817; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 3818; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 3819; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 3820; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 3821; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3822; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 3823; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 3824; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 3825; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 3826; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 3827; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 3828; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 3829; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 3830; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3831; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 3832; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 3833; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 3834; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 3835; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 3836; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 3837; 3838; GFX900-SDAG-LABEL: v_exp10_f32_daz: 3839; GFX900-SDAG: ; %bb.0: 3840; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3841; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 3842; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 3843; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 3844; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 3845; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 3846; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 3847; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 3848; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 3849; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 3850; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 3851; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 3852; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3853; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 3854; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 3855; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 3856; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 3857; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 3858; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 3859; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 3860; 3861; GFX900-GISEL-LABEL: v_exp10_f32_daz: 3862; GFX900-GISEL: ; %bb.0: 3863; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3864; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 3865; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 3866; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 3867; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 3868; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 3869; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 3870; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 3871; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 3872; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 3873; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 3874; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 3875; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 3876; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3877; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 3878; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 3879; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 3880; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 3881; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 3882; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 3883; 3884; SI-SDAG-LABEL: v_exp10_f32_daz: 3885; SI-SDAG: ; %bb.0: 3886; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3887; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 3888; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 3889; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 3890; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 3891; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 3892; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 3893; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 3894; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 3895; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3896; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 3897; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 3898; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3899; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 3900; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 3901; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 3902; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 3903; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 3904; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 3905; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 3906; 3907; SI-GISEL-LABEL: v_exp10_f32_daz: 3908; SI-GISEL: ; %bb.0: 3909; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3910; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 3911; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 3912; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 3913; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 3914; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 3915; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 3916; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 3917; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 3918; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 3919; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 3920; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 3921; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 3922; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3923; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 3924; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 3925; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 3926; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 3927; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 3928; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 3929; 3930; R600-LABEL: v_exp10_f32_daz: 3931; R600: ; %bb.0: 3932; R600-NEXT: CF_END 3933; R600-NEXT: PAD 3934; 3935; CM-LABEL: v_exp10_f32_daz: 3936; CM: ; %bb.0: 3937; CM-NEXT: CF_END 3938; CM-NEXT: PAD 3939 %result = call float @llvm.exp10.f32(float %in) 3940 ret float %result 3941} 3942 3943define float @v_exp10_f32_nnan(float %in) { 3944; VI-SDAG-LABEL: v_exp10_f32_nnan: 3945; VI-SDAG: ; %bb.0: 3946; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3947; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 3948; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 3949; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 3950; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 3951; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 3952; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 3953; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 3954; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3955; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 3956; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 3957; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 3958; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 3959; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 3960; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 3961; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 3962; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 3963; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 3964; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 3965; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 3966; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 3967; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 3968; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 3969; 3970; VI-GISEL-LABEL: v_exp10_f32_nnan: 3971; VI-GISEL: ; %bb.0: 3972; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3973; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 3974; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 3975; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 3976; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 3977; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 3978; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 3979; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 3980; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 3981; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 3982; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 3983; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 3984; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 3985; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 3986; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 3987; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 3988; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 3989; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 3990; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 3991; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 3992; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 3993; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 3994; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 3995; 3996; GFX900-SDAG-LABEL: v_exp10_f32_nnan: 3997; GFX900-SDAG: ; %bb.0: 3998; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 3999; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4000; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4001; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4002; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4003; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4004; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4005; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4006; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4007; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 4008; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4009; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4010; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4011; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4012; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4013; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4014; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4015; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4016; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4017; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 4018; 4019; GFX900-GISEL-LABEL: v_exp10_f32_nnan: 4020; GFX900-GISEL: ; %bb.0: 4021; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4022; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4023; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4024; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4025; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4026; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4027; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4028; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4029; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4030; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4031; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 4032; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4033; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4034; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4035; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4036; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4037; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4038; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4039; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4040; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 4041; 4042; SI-SDAG-LABEL: v_exp10_f32_nnan: 4043; SI-SDAG: ; %bb.0: 4044; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4045; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4046; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4047; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4048; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4049; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4050; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4051; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4052; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4053; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4054; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4055; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4056; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4057; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4058; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 4059; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4060; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4061; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4062; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4063; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 4064; 4065; SI-GISEL-LABEL: v_exp10_f32_nnan: 4066; SI-GISEL: ; %bb.0: 4067; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4068; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4069; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4070; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4071; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4072; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4073; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4074; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4075; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4076; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4077; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4078; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4079; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 4080; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4081; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4082; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4083; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4084; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4085; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4086; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 4087; 4088; R600-LABEL: v_exp10_f32_nnan: 4089; R600: ; %bb.0: 4090; R600-NEXT: CF_END 4091; R600-NEXT: PAD 4092; 4093; CM-LABEL: v_exp10_f32_nnan: 4094; CM: ; %bb.0: 4095; CM-NEXT: CF_END 4096; CM-NEXT: PAD 4097 %result = call nnan float @llvm.exp10.f32(float %in) 4098 ret float %result 4099} 4100 4101define float @v_exp10_f32_nnan_daz(float %in) #0 { 4102; VI-SDAG-LABEL: v_exp10_f32_nnan_daz: 4103; VI-SDAG: ; %bb.0: 4104; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4105; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4106; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 4107; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 4108; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 4109; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 4110; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 4111; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 4112; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4113; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 4114; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 4115; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 4116; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4117; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 4118; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4119; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4120; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4121; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4122; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4123; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4124; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4125; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4126; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 4127; 4128; VI-GISEL-LABEL: v_exp10_f32_nnan_daz: 4129; VI-GISEL: ; %bb.0: 4130; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4131; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4132; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 4133; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 4134; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 4135; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 4136; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 4137; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4138; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 4139; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 4140; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 4141; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 4142; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 4143; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4144; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4145; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4146; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4147; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4148; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4149; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4150; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4151; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4152; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 4153; 4154; GFX900-SDAG-LABEL: v_exp10_f32_nnan_daz: 4155; GFX900-SDAG: ; %bb.0: 4156; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4157; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4158; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4159; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4160; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4161; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4162; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4163; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4164; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4165; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 4166; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4167; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4168; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4169; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4170; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4171; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4172; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4173; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4174; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4175; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 4176; 4177; GFX900-GISEL-LABEL: v_exp10_f32_nnan_daz: 4178; GFX900-GISEL: ; %bb.0: 4179; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4180; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4181; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4182; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4183; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4184; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4185; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4186; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4187; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4188; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4189; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 4190; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4191; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4192; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4193; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4194; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4195; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4196; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4197; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4198; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 4199; 4200; SI-SDAG-LABEL: v_exp10_f32_nnan_daz: 4201; SI-SDAG: ; %bb.0: 4202; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4203; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4204; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4205; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4206; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4207; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4208; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4209; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4210; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4211; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4212; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4213; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4214; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4215; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4216; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 4217; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4218; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4219; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4220; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4221; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 4222; 4223; SI-GISEL-LABEL: v_exp10_f32_nnan_daz: 4224; SI-GISEL: ; %bb.0: 4225; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4226; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4227; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4228; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4229; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4230; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4231; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4232; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4233; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4234; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4235; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4236; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4237; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 4238; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4239; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4240; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4241; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4242; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4243; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4244; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 4245; 4246; R600-LABEL: v_exp10_f32_nnan_daz: 4247; R600: ; %bb.0: 4248; R600-NEXT: CF_END 4249; R600-NEXT: PAD 4250; 4251; CM-LABEL: v_exp10_f32_nnan_daz: 4252; CM: ; %bb.0: 4253; CM-NEXT: CF_END 4254; CM-NEXT: PAD 4255 %result = call nnan float @llvm.exp10.f32(float %in) 4256 ret float %result 4257} 4258 4259define float @v_exp10_f32_nnan_dynamic(float %in) #1 { 4260; VI-SDAG-LABEL: v_exp10_f32_nnan_dynamic: 4261; VI-SDAG: ; %bb.0: 4262; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4263; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4264; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 4265; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 4266; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 4267; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 4268; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 4269; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 4270; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4271; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 4272; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 4273; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 4274; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4275; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 4276; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4277; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4278; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4279; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4280; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4281; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4282; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4283; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4284; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 4285; 4286; VI-GISEL-LABEL: v_exp10_f32_nnan_dynamic: 4287; VI-GISEL: ; %bb.0: 4288; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4289; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4290; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 4291; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 4292; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 4293; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 4294; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 4295; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4296; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 4297; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 4298; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 4299; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 4300; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 4301; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4302; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4303; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4304; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4305; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4306; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4307; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4308; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4309; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4310; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 4311; 4312; GFX900-SDAG-LABEL: v_exp10_f32_nnan_dynamic: 4313; GFX900-SDAG: ; %bb.0: 4314; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4315; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4316; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4317; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4318; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4319; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4320; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4321; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4322; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4323; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 4324; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4325; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4326; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4327; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4328; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4329; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4330; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4331; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4332; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4333; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 4334; 4335; GFX900-GISEL-LABEL: v_exp10_f32_nnan_dynamic: 4336; GFX900-GISEL: ; %bb.0: 4337; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4338; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4339; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4340; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4341; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4342; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4343; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4344; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4345; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4346; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4347; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 4348; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4349; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4350; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4351; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4352; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4353; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4354; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4355; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4356; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 4357; 4358; SI-SDAG-LABEL: v_exp10_f32_nnan_dynamic: 4359; SI-SDAG: ; %bb.0: 4360; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4361; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4362; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4363; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4364; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4365; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4366; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4367; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4368; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4369; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4370; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4371; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4372; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4373; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 4374; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 4375; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 4376; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 4377; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 4378; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 4379; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 4380; 4381; SI-GISEL-LABEL: v_exp10_f32_nnan_dynamic: 4382; SI-GISEL: ; %bb.0: 4383; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4384; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4385; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4386; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4387; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4388; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4389; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4390; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4391; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4392; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4393; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4394; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 4395; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 4396; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4397; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4398; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 4399; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 4400; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 4401; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 4402; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 4403; 4404; R600-LABEL: v_exp10_f32_nnan_dynamic: 4405; R600: ; %bb.0: 4406; R600-NEXT: CF_END 4407; R600-NEXT: PAD 4408; 4409; CM-LABEL: v_exp10_f32_nnan_dynamic: 4410; CM: ; %bb.0: 4411; CM-NEXT: CF_END 4412; CM-NEXT: PAD 4413 %result = call nnan float @llvm.exp10.f32(float %in) 4414 ret float %result 4415} 4416 4417define float @v_exp10_f32_ninf_daz(float %in) #0 { 4418; VI-SDAG-LABEL: v_exp10_f32_ninf_daz: 4419; VI-SDAG: ; %bb.0: 4420; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4421; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4422; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 4423; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 4424; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 4425; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 4426; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 4427; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 4428; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4429; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 4430; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 4431; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 4432; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4433; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 4434; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4435; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4436; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4437; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4438; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 4439; 4440; VI-GISEL-LABEL: v_exp10_f32_ninf_daz: 4441; VI-GISEL: ; %bb.0: 4442; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4443; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4444; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 4445; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 4446; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 4447; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 4448; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 4449; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4450; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 4451; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 4452; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 4453; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 4454; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 4455; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4456; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4457; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4458; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4459; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4460; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 4461; 4462; GFX900-SDAG-LABEL: v_exp10_f32_ninf_daz: 4463; GFX900-SDAG: ; %bb.0: 4464; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4465; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4466; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4467; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4468; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4469; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4470; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4471; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4472; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4473; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 4474; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4475; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4476; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4477; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4478; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4479; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 4480; 4481; GFX900-GISEL-LABEL: v_exp10_f32_ninf_daz: 4482; GFX900-GISEL: ; %bb.0: 4483; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4484; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4485; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4486; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4487; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4488; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4489; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4490; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4491; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4492; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4493; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 4494; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4495; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4496; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4497; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4498; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 4499; 4500; SI-SDAG-LABEL: v_exp10_f32_ninf_daz: 4501; SI-SDAG: ; %bb.0: 4502; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4503; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4504; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4505; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4506; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4507; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4508; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4509; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4510; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4511; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4512; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4513; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4514; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4515; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 4516; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4517; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 4518; 4519; SI-GISEL-LABEL: v_exp10_f32_ninf_daz: 4520; SI-GISEL: ; %bb.0: 4521; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4522; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4523; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4524; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4525; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4526; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4527; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4528; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4529; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4530; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4531; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4532; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 4533; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4534; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4535; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4536; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 4537; 4538; R600-LABEL: v_exp10_f32_ninf_daz: 4539; R600: ; %bb.0: 4540; R600-NEXT: CF_END 4541; R600-NEXT: PAD 4542; 4543; CM-LABEL: v_exp10_f32_ninf_daz: 4544; CM: ; %bb.0: 4545; CM-NEXT: CF_END 4546; CM-NEXT: PAD 4547 %result = call ninf float @llvm.exp10.f32(float %in) 4548 ret float %result 4549} 4550 4551define float @v_exp10_f32_ninf_dynamic(float %in) #1 { 4552; VI-SDAG-LABEL: v_exp10_f32_ninf_dynamic: 4553; VI-SDAG: ; %bb.0: 4554; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4555; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4556; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 4557; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 4558; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 4559; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 4560; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 4561; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 4562; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4563; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 4564; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 4565; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 4566; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4567; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 4568; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4569; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4570; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4571; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4572; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 4573; 4574; VI-GISEL-LABEL: v_exp10_f32_ninf_dynamic: 4575; VI-GISEL: ; %bb.0: 4576; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4577; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4578; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 4579; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 4580; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 4581; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 4582; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 4583; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4584; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 4585; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 4586; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 4587; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 4588; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 4589; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4590; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4591; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4592; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4593; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4594; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 4595; 4596; GFX900-SDAG-LABEL: v_exp10_f32_ninf_dynamic: 4597; GFX900-SDAG: ; %bb.0: 4598; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4599; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4600; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4601; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4602; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4603; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4604; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4605; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4606; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4607; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 4608; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4609; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4610; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4611; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4612; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4613; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 4614; 4615; GFX900-GISEL-LABEL: v_exp10_f32_ninf_dynamic: 4616; GFX900-GISEL: ; %bb.0: 4617; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4618; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4619; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4620; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4621; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4622; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4623; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4624; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4625; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4626; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4627; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 4628; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4629; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4630; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4631; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4632; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 4633; 4634; SI-SDAG-LABEL: v_exp10_f32_ninf_dynamic: 4635; SI-SDAG: ; %bb.0: 4636; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4637; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4638; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4639; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4640; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4641; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4642; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4643; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4644; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4645; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4646; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4647; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4648; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4649; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 4650; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4651; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 4652; 4653; SI-GISEL-LABEL: v_exp10_f32_ninf_dynamic: 4654; SI-GISEL: ; %bb.0: 4655; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4656; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4657; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4658; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4659; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4660; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4661; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4662; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4663; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4664; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4665; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4666; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 4667; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4668; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4669; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4670; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 4671; 4672; R600-LABEL: v_exp10_f32_ninf_dynamic: 4673; R600: ; %bb.0: 4674; R600-NEXT: CF_END 4675; R600-NEXT: PAD 4676; 4677; CM-LABEL: v_exp10_f32_ninf_dynamic: 4678; CM: ; %bb.0: 4679; CM-NEXT: CF_END 4680; CM-NEXT: PAD 4681 %result = call ninf float @llvm.exp10.f32(float %in) 4682 ret float %result 4683} 4684 4685define float @v_exp10_f32_nnan_ninf(float %in) { 4686; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf: 4687; VI-SDAG: ; %bb.0: 4688; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4689; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4690; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 4691; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 4692; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 4693; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 4694; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 4695; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 4696; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4697; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 4698; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 4699; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 4700; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4701; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 4702; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4703; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4704; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4705; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4706; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 4707; 4708; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf: 4709; VI-GISEL: ; %bb.0: 4710; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4711; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4712; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 4713; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 4714; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 4715; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 4716; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 4717; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4718; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 4719; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 4720; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 4721; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 4722; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 4723; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4724; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4725; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4726; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4727; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4728; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 4729; 4730; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf: 4731; GFX900-SDAG: ; %bb.0: 4732; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4733; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4734; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4735; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4736; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4737; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4738; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4739; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4740; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4741; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 4742; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4743; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4744; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4745; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4746; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4747; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 4748; 4749; GFX900-GISEL-LABEL: v_exp10_f32_nnan_ninf: 4750; GFX900-GISEL: ; %bb.0: 4751; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4752; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4753; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4754; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4755; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4756; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4757; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4758; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4759; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4760; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4761; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 4762; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4763; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4764; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4765; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4766; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 4767; 4768; SI-SDAG-LABEL: v_exp10_f32_nnan_ninf: 4769; SI-SDAG: ; %bb.0: 4770; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4771; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4772; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4773; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4774; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4775; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4776; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4777; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4778; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4779; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4780; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4781; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4782; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4783; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 4784; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4785; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 4786; 4787; SI-GISEL-LABEL: v_exp10_f32_nnan_ninf: 4788; SI-GISEL: ; %bb.0: 4789; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4790; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4791; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4792; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4793; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4794; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4795; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4796; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4797; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4798; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4799; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4800; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 4801; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4802; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4803; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4804; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 4805; 4806; R600-LABEL: v_exp10_f32_nnan_ninf: 4807; R600: ; %bb.0: 4808; R600-NEXT: CF_END 4809; R600-NEXT: PAD 4810; 4811; CM-LABEL: v_exp10_f32_nnan_ninf: 4812; CM: ; %bb.0: 4813; CM-NEXT: CF_END 4814; CM-NEXT: PAD 4815 %result = call nnan ninf float @llvm.exp10.f32(float %in) 4816 ret float %result 4817} 4818 4819define float @v_exp10_f32_nnan_ninf_daz(float %in) #0 { 4820; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz: 4821; VI-SDAG: ; %bb.0: 4822; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4823; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4824; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 4825; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 4826; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 4827; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 4828; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 4829; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 4830; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4831; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 4832; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 4833; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 4834; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4835; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 4836; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4837; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4838; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4839; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4840; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 4841; 4842; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf_daz: 4843; VI-GISEL: ; %bb.0: 4844; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4845; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4846; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 4847; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 4848; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 4849; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 4850; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 4851; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4852; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 4853; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 4854; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 4855; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 4856; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 4857; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4858; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4859; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4860; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4861; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4862; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 4863; 4864; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz: 4865; GFX900-SDAG: ; %bb.0: 4866; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4867; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4868; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4869; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4870; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4871; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4872; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4873; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4874; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4875; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 4876; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4877; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4878; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4879; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4880; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4881; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 4882; 4883; GFX900-GISEL-LABEL: v_exp10_f32_nnan_ninf_daz: 4884; GFX900-GISEL: ; %bb.0: 4885; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4886; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4887; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4888; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4889; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4890; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4891; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4892; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4893; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4894; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4895; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 4896; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4897; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4898; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4899; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4900; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 4901; 4902; SI-SDAG-LABEL: v_exp10_f32_nnan_ninf_daz: 4903; SI-SDAG: ; %bb.0: 4904; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4905; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 4906; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 4907; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 4908; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 4909; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 4910; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 4911; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 4912; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 4913; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4914; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 4915; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4916; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4917; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 4918; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4919; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 4920; 4921; SI-GISEL-LABEL: v_exp10_f32_nnan_ninf_daz: 4922; SI-GISEL: ; %bb.0: 4923; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4924; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 4925; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 4926; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 4927; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 4928; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 4929; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 4930; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 4931; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 4932; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 4933; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4934; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 4935; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4936; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4937; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4938; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 4939; 4940; R600-LABEL: v_exp10_f32_nnan_ninf_daz: 4941; R600: ; %bb.0: 4942; R600-NEXT: CF_END 4943; R600-NEXT: PAD 4944; 4945; CM-LABEL: v_exp10_f32_nnan_ninf_daz: 4946; CM: ; %bb.0: 4947; CM-NEXT: CF_END 4948; CM-NEXT: PAD 4949 %result = call nnan ninf float @llvm.exp10.f32(float %in) 4950 ret float %result 4951} 4952 4953define float @v_exp10_f32_nnan_ninf_dynamic(float %in) #1 { 4954; VI-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic: 4955; VI-SDAG: ; %bb.0: 4956; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4957; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4958; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 4959; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 4960; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 4961; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 4962; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 4963; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 4964; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4965; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 4966; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 4967; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 4968; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 4969; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 4970; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 4971; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 4972; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 4973; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 4974; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 4975; 4976; VI-GISEL-LABEL: v_exp10_f32_nnan_ninf_dynamic: 4977; VI-GISEL: ; %bb.0: 4978; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 4979; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 4980; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 4981; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 4982; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 4983; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 4984; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 4985; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 4986; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 4987; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 4988; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 4989; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 4990; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 4991; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 4992; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 4993; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 4994; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 4995; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 4996; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 4997; 4998; GFX900-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic: 4999; GFX900-SDAG: ; %bb.0: 5000; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5001; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5002; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5003; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 5004; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 5005; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 5006; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 5007; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 5008; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 5009; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 5010; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 5011; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5012; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5013; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5014; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 5015; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 5016; 5017; GFX900-GISEL-LABEL: v_exp10_f32_nnan_ninf_dynamic: 5018; GFX900-GISEL: ; %bb.0: 5019; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5020; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5021; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 5022; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 5023; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 5024; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 5025; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 5026; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 5027; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 5028; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 5029; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 5030; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 5031; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5032; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5033; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 5034; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 5035; 5036; SI-SDAG-LABEL: v_exp10_f32_nnan_ninf_dynamic: 5037; SI-SDAG: ; %bb.0: 5038; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5039; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5040; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5041; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 5042; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 5043; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 5044; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 5045; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 5046; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 5047; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5048; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 5049; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5050; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5051; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 5052; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 5053; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 5054; 5055; SI-GISEL-LABEL: v_exp10_f32_nnan_ninf_dynamic: 5056; SI-GISEL: ; %bb.0: 5057; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5058; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5059; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 5060; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 5061; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 5062; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 5063; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 5064; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 5065; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 5066; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 5067; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5068; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 5069; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5070; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5071; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 5072; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 5073; 5074; R600-LABEL: v_exp10_f32_nnan_ninf_dynamic: 5075; R600: ; %bb.0: 5076; R600-NEXT: CF_END 5077; R600-NEXT: PAD 5078; 5079; CM-LABEL: v_exp10_f32_nnan_ninf_dynamic: 5080; CM: ; %bb.0: 5081; CM-NEXT: CF_END 5082; CM-NEXT: PAD 5083 %result = call nnan ninf float @llvm.exp10.f32(float %in) 5084 ret float %result 5085} 5086 5087define float @v_exp10_f32_fast_daz(float %in) #0 { 5088; GCN-SDAG-LABEL: v_exp10_f32_fast_daz: 5089; GCN-SDAG: ; %bb.0: 5090; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5091; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 5092; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 5093; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 5094; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 5095; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 5096; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 5097; 5098; GCN-GISEL-LABEL: v_exp10_f32_fast_daz: 5099; GCN-GISEL: ; %bb.0: 5100; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5101; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 5102; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 5103; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 5104; 5105; SI-SDAG-LABEL: v_exp10_f32_fast_daz: 5106; SI-SDAG: ; %bb.0: 5107; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5108; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 5109; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 5110; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5111; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 5112; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 5113; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 5114; 5115; SI-GISEL-LABEL: v_exp10_f32_fast_daz: 5116; SI-GISEL: ; %bb.0: 5117; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5118; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 5119; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 5120; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 5121; 5122; R600-LABEL: v_exp10_f32_fast_daz: 5123; R600: ; %bb.0: 5124; R600-NEXT: CF_END 5125; R600-NEXT: PAD 5126; 5127; CM-LABEL: v_exp10_f32_fast_daz: 5128; CM: ; %bb.0: 5129; CM-NEXT: CF_END 5130; CM-NEXT: PAD 5131 %result = call fast float @llvm.exp10.f32(float %in) 5132 ret float %result 5133} 5134 5135define float @v_exp10_f32_dynamic_mode(float %in) #1 { 5136; VI-SDAG-LABEL: v_exp10_f32_dynamic_mode: 5137; VI-SDAG: ; %bb.0: 5138; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5139; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5140; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 5141; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 5142; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 5143; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 5144; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 5145; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 5146; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 5147; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 5148; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 5149; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 5150; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5151; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 5152; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5153; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5154; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5155; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5156; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5157; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5158; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5159; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5160; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 5161; 5162; VI-GISEL-LABEL: v_exp10_f32_dynamic_mode: 5163; VI-GISEL: ; %bb.0: 5164; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5165; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5166; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 5167; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 5168; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 5169; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 5170; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 5171; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 5172; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 5173; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 5174; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 5175; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 5176; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 5177; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5178; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5179; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 5180; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5181; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5182; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5183; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5184; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5185; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5186; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 5187; 5188; GFX900-SDAG-LABEL: v_exp10_f32_dynamic_mode: 5189; GFX900-SDAG: ; %bb.0: 5190; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5191; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5192; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5193; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 5194; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 5195; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 5196; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 5197; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 5198; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 5199; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 5200; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 5201; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5202; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5203; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5204; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5205; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5206; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5207; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5208; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5209; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 5210; 5211; GFX900-GISEL-LABEL: v_exp10_f32_dynamic_mode: 5212; GFX900-GISEL: ; %bb.0: 5213; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5214; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5215; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 5216; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 5217; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 5218; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 5219; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 5220; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 5221; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 5222; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 5223; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 5224; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5225; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 5226; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5227; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5228; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5229; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5230; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5231; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5232; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 5233; 5234; SI-SDAG-LABEL: v_exp10_f32_dynamic_mode: 5235; SI-SDAG: ; %bb.0: 5236; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5237; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5238; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5239; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 5240; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 5241; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 5242; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 5243; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 5244; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 5245; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5246; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 5247; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5248; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5249; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5250; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 5251; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5252; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5253; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5254; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5255; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 5256; 5257; SI-GISEL-LABEL: v_exp10_f32_dynamic_mode: 5258; SI-GISEL: ; %bb.0: 5259; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5260; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5261; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 5262; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 5263; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 5264; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 5265; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 5266; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 5267; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 5268; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 5269; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5270; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5271; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 5272; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5273; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5274; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5275; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5276; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5277; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5278; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 5279; 5280; R600-LABEL: v_exp10_f32_dynamic_mode: 5281; R600: ; %bb.0: 5282; R600-NEXT: CF_END 5283; R600-NEXT: PAD 5284; 5285; CM-LABEL: v_exp10_f32_dynamic_mode: 5286; CM: ; %bb.0: 5287; CM-NEXT: CF_END 5288; CM-NEXT: PAD 5289 %result = call float @llvm.exp10.f32(float %in) 5290 ret float %result 5291} 5292 5293define float @v_exp10_f32_undef() { 5294; VI-SDAG-LABEL: v_exp10_f32_undef: 5295; VI-SDAG: ; %bb.0: 5296; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5297; VI-SDAG-NEXT: v_rndne_f32_e32 v0, 0 5298; VI-SDAG-NEXT: s_mov_b32 s4, 0x7fc00000 5299; VI-SDAG-NEXT: v_add_f32_e64 v1, -v0, s4 5300; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5301; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0 5302; VI-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 5303; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 5304; 5305; VI-GISEL-LABEL: v_exp10_f32_undef: 5306; VI-GISEL: ; %bb.0: 5307; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5308; VI-GISEL-NEXT: v_sub_f32_e64 v0, s4, 0 5309; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549000 5310; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3a2784bc 5311; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v0 5312; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 5313; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0, v1 5314; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3 5315; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0, v2 5316; VI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0 5317; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v1 5318; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 5319; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0 5320; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2 5321; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 5322; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 5323; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 5324; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4 5325; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1 5326; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b 5327; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 5328; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1 5329; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 5330; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 5331; 5332; GFX900-SDAG-LABEL: v_exp10_f32_undef: 5333; GFX900-SDAG: ; %bb.0: 5334; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5335; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 5336; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xffc00000 5337; GFX900-SDAG-NEXT: v_fma_f32 v0, s4, v0, v1 5338; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 5339; GFX900-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0 5340; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, 0x7fc00000 5341; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, 0x7fc00000, v1 5342; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v2, v0 5343; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 5344; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 5345; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 5346; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 5347; 5348; GFX900-GISEL-LABEL: v_exp10_f32_undef: 5349; GFX900-GISEL: ; %bb.0: 5350; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5351; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78 5352; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s4, v0 5353; GFX900-GISEL-NEXT: v_fma_f32 v0, s4, v0, -v1 5354; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 5355; GFX900-GISEL-NEXT: v_fma_f32 v0, s4, v2, v0 5356; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v1 5357; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 5358; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0 5359; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2 5360; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 5361; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 5362; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 5363; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4 5364; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1 5365; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b 5366; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 5367; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1 5368; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 5369; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 5370; 5371; SI-SDAG-LABEL: v_exp10_f32_undef: 5372; SI-SDAG: ; %bb.0: 5373; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5374; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78 5375; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xffc00000 5376; SI-SDAG-NEXT: v_fma_f32 v0, s4, v0, v1 5377; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37 5378; SI-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0 5379; SI-SDAG-NEXT: v_rndne_f32_e32 v1, 0x7fc00000 5380; SI-SDAG-NEXT: v_sub_f32_e32 v2, 0x7fc00000, v1 5381; SI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0 5382; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 5383; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 5384; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 5385; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 5386; 5387; SI-GISEL-LABEL: v_exp10_f32_undef: 5388; SI-GISEL: ; %bb.0: 5389; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5390; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78 5391; SI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v0 5392; SI-GISEL-NEXT: v_fma_f32 v0, s4, v0, -v1 5393; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 5394; SI-GISEL-NEXT: v_fma_f32 v0, s4, v2, v0 5395; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v1 5396; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 5397; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0 5398; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2 5399; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 5400; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 5401; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 5402; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4 5403; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1 5404; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b 5405; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 5406; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1 5407; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 5408; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 5409; 5410; R600-LABEL: v_exp10_f32_undef: 5411; R600: ; %bb.0: 5412; R600-NEXT: CF_END 5413; R600-NEXT: PAD 5414; 5415; CM-LABEL: v_exp10_f32_undef: 5416; CM: ; %bb.0: 5417; CM-NEXT: CF_END 5418; CM-NEXT: PAD 5419 %result = call float @llvm.exp10.f32(float undef) 5420 ret float %result 5421} 5422 5423define float @v_exp10_f32_0() { 5424; GCN-LABEL: v_exp10_f32_0: 5425; GCN: ; %bb.0: 5426; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5427; GCN-NEXT: v_mov_b32_e32 v0, 1.0 5428; GCN-NEXT: s_setpc_b64 s[30:31] 5429; 5430; SI-LABEL: v_exp10_f32_0: 5431; SI: ; %bb.0: 5432; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5433; SI-NEXT: v_mov_b32_e32 v0, 1.0 5434; SI-NEXT: s_setpc_b64 s[30:31] 5435; 5436; R600-LABEL: v_exp10_f32_0: 5437; R600: ; %bb.0: 5438; R600-NEXT: CF_END 5439; R600-NEXT: PAD 5440; 5441; CM-LABEL: v_exp10_f32_0: 5442; CM: ; %bb.0: 5443; CM-NEXT: CF_END 5444; CM-NEXT: PAD 5445 %result = call float @llvm.exp10.f32(float 0.0) 5446 ret float %result 5447} 5448 5449define float @v_exp10_f32_from_fpext_f16(i16 %src.i) { 5450; VI-SDAG-LABEL: v_exp10_f32_from_fpext_f16: 5451; VI-SDAG: ; %bb.0: 5452; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5453; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5454; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5455; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5456; VI-SDAG-NEXT: v_sub_f32_e32 v3, v0, v1 5457; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 5458; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v3 5459; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x40549000, v3 5460; VI-SDAG-NEXT: v_rndne_f32_e32 v4, v2 5461; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5 5462; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 5463; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v4 5464; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v3 5465; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 5466; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v4 5467; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5468; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5469; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5470; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5471; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5472; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5473; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5474; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5475; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 5476; 5477; VI-GISEL-LABEL: v_exp10_f32_from_fpext_f16: 5478; VI-GISEL: ; %bb.0: 5479; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5480; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5481; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5482; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 5483; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 5484; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 5485; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 5486; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 5487; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 5488; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 5489; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 5490; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 5491; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 5492; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 5493; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5494; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5495; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 5496; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5497; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5498; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5499; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5500; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5501; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5502; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 5503; 5504; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_f16: 5505; GFX900-SDAG: ; %bb.0: 5506; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5507; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5508; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5509; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x33979a37 5510; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5511; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 5512; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 5513; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2 5514; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s5, v3 5515; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v3 5516; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 5517; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 5518; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5519; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5520; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5521; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5522; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5523; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5524; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5525; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5526; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 5527; 5528; GFX900-GISEL-LABEL: v_exp10_f32_from_fpext_f16: 5529; GFX900-GISEL: ; %bb.0: 5530; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5531; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5532; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5533; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 5534; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v0 5535; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v3 5536; GFX900-GISEL-NEXT: v_rndne_f32_e32 v4, v3 5537; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 5538; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v3, v4 5539; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 5540; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v4 5541; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 5542; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4 5543; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3 5544; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5545; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 5546; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5547; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5548; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5549; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5550; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 5551; 5552; SI-SDAG-LABEL: v_exp10_f32_from_fpext_f16: 5553; SI-SDAG: ; %bb.0: 5554; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5555; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5556; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5557; SI-SDAG-NEXT: s_mov_b32 s5, 0x33979a37 5558; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5559; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 5560; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 5561; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2 5562; SI-SDAG-NEXT: v_fma_f32 v3, v0, s5, v3 5563; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v3 5564; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 5565; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5566; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5567; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5568; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5569; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 5570; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5571; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5572; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5573; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5574; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 5575; 5576; SI-GISEL-LABEL: v_exp10_f32_from_fpext_f16: 5577; SI-GISEL: ; %bb.0: 5578; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5579; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5580; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5581; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 5582; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v0 5583; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v3 5584; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v3 5585; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 5586; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v4 5587; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 5588; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v4 5589; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5590; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc23369f4 5591; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3 5592; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5593; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 5594; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5595; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5596; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5597; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5598; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 5599; 5600; R600-LABEL: v_exp10_f32_from_fpext_f16: 5601; R600: ; %bb.0: 5602; R600-NEXT: CF_END 5603; R600-NEXT: PAD 5604; 5605; CM-LABEL: v_exp10_f32_from_fpext_f16: 5606; CM: ; %bb.0: 5607; CM-NEXT: CF_END 5608; CM-NEXT: PAD 5609 %src = bitcast i16 %src.i to half 5610 %fpext = fpext half %src to float 5611 %result = call float @llvm.exp10.f32(float %fpext) 5612 ret float %result 5613} 5614 5615define float @v_exp10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) { 5616; VI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16: 5617; VI-SDAG: ; %bb.0: 5618; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5619; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1 5620; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5621; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5622; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5623; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1 5624; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 5625; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 5626; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1 5627; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 5628; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v1 5629; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 5630; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 5631; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 5632; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 5633; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5634; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 5635; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5636; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5637; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5638; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5639; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5640; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5641; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5642; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 5643; 5644; VI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16: 5645; VI-GISEL: ; %bb.0: 5646; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5647; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1 5648; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5649; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5650; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 5651; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 5652; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 5653; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 5654; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 5655; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 5656; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 5657; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 5658; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 5659; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 5660; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 5661; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5662; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5663; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 5664; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5665; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5666; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5667; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5668; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5669; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5670; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 5671; 5672; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16: 5673; GFX900-SDAG: ; %bb.0: 5674; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5675; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v1 5676; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5677; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5678; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x33979a37 5679; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5680; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 5681; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v1 5682; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 5683; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 5684; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 5685; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 5686; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 5687; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5688; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5689; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5690; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5691; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5692; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5693; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5694; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5695; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 5696; 5697; GFX900-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16: 5698; GFX900-GISEL: ; %bb.0: 5699; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5700; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v1 5701; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5702; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5703; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 5704; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v0 5705; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v3 5706; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 5707; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v3 5708; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 5709; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 5710; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 5711; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 5712; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5713; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 5714; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5715; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5716; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 5717; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5718; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 5719; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 5720; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 5721; 5722; SI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16: 5723; SI-SDAG: ; %bb.0: 5724; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5725; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5726; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 5727; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 5728; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 5729; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5730; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 5731; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 5732; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 5733; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2 5734; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 5735; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 5736; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5737; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 5738; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5739; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5740; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5741; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 5742; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5743; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5744; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5745; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5746; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 5747; 5748; SI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16: 5749; SI-GISEL: ; %bb.0: 5750; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5751; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5752; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 5753; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 5754; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 5755; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 5756; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 5757; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 5758; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5759; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v0 5760; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v3 5761; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v3 5762; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 5763; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v4 5764; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 5765; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 5766; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5767; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 5768; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b 5769; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 5770; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v3 5771; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 5772; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v4 5773; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc 5774; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 5775; 5776; R600-LABEL: v_exp10_f32_from_fpext_math_f16: 5777; R600: ; %bb.0: 5778; R600-NEXT: CF_END 5779; R600-NEXT: PAD 5780; 5781; CM-LABEL: v_exp10_f32_from_fpext_math_f16: 5782; CM: ; %bb.0: 5783; CM-NEXT: CF_END 5784; CM-NEXT: PAD 5785 %src0 = bitcast i16 %src0.i to half 5786 %src1 = bitcast i16 %src1.i to half 5787 %fadd = fadd half %src0, %src1 5788 %fpext = fpext half %fadd to float 5789 %result = call float @llvm.exp10.f32(float %fpext) 5790 ret float %result 5791} 5792 5793define float @v_exp10_f32_from_fpext_bf16(bfloat %src) { 5794; VI-LABEL: v_exp10_f32_from_fpext_bf16: 5795; VI: ; %bb.0: 5796; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5797; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 5798; VI-NEXT: v_sub_f32_e32 v3, v0, v0 5799; VI-NEXT: v_mul_f32_e32 v1, 0x40549000, v0 5800; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v3 5801; VI-NEXT: v_mul_f32_e32 v3, 0x40549000, v3 5802; VI-NEXT: v_rndne_f32_e32 v2, v1 5803; VI-NEXT: v_add_f32_e32 v3, v3, v4 5804; VI-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v0 5805; VI-NEXT: v_sub_f32_e32 v1, v1, v2 5806; VI-NEXT: v_add_f32_e32 v3, v4, v3 5807; VI-NEXT: v_add_f32_e32 v1, v1, v3 5808; VI-NEXT: v_exp_f32_e32 v1, v1 5809; VI-NEXT: v_cvt_i32_f32_e32 v2, v2 5810; VI-NEXT: s_mov_b32 s4, 0xc23369f4 5811; VI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5812; VI-NEXT: s_mov_b32 s4, 0x421a209b 5813; VI-NEXT: v_ldexp_f32 v1, v1, v2 5814; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5815; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000 5816; VI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5817; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5818; VI-NEXT: s_setpc_b64 s[30:31] 5819; 5820; GFX900-LABEL: v_exp10_f32_from_fpext_bf16: 5821; GFX900: ; %bb.0: 5822; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5823; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0 5824; GFX900-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5825; GFX900-NEXT: s_mov_b32 s4, 0x40549a78 5826; GFX900-NEXT: v_rndne_f32_e32 v2, v1 5827; GFX900-NEXT: v_sub_f32_e32 v3, v1, v2 5828; GFX900-NEXT: v_fma_f32 v1, v0, s4, -v1 5829; GFX900-NEXT: s_mov_b32 s4, 0x33979a37 5830; GFX900-NEXT: v_fma_f32 v1, v0, s4, v1 5831; GFX900-NEXT: v_add_f32_e32 v1, v3, v1 5832; GFX900-NEXT: v_exp_f32_e32 v1, v1 5833; GFX900-NEXT: v_cvt_i32_f32_e32 v2, v2 5834; GFX900-NEXT: s_mov_b32 s4, 0xc23369f4 5835; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5836; GFX900-NEXT: s_mov_b32 s4, 0x421a209b 5837; GFX900-NEXT: v_ldexp_f32 v1, v1, v2 5838; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5839; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f800000 5840; GFX900-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5841; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5842; GFX900-NEXT: s_setpc_b64 s[30:31] 5843; 5844; SI-LABEL: v_exp10_f32_from_fpext_bf16: 5845; SI: ; %bb.0: 5846; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5847; SI-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 5848; SI-NEXT: s_mov_b32 s4, 0x40549a78 5849; SI-NEXT: v_rndne_f32_e32 v2, v1 5850; SI-NEXT: v_sub_f32_e32 v3, v1, v2 5851; SI-NEXT: v_fma_f32 v1, v0, s4, -v1 5852; SI-NEXT: s_mov_b32 s4, 0x33979a37 5853; SI-NEXT: v_fma_f32 v1, v0, s4, v1 5854; SI-NEXT: v_add_f32_e32 v1, v3, v1 5855; SI-NEXT: v_exp_f32_e32 v1, v1 5856; SI-NEXT: v_cvt_i32_f32_e32 v2, v2 5857; SI-NEXT: s_mov_b32 s4, 0xc23369f4 5858; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5859; SI-NEXT: s_mov_b32 s4, 0x421a209b 5860; SI-NEXT: v_ldexp_f32_e32 v1, v1, v2 5861; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5862; SI-NEXT: v_mov_b32_e32 v2, 0x7f800000 5863; SI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5864; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5865; SI-NEXT: s_setpc_b64 s[30:31] 5866; 5867; R600-LABEL: v_exp10_f32_from_fpext_bf16: 5868; R600: ; %bb.0: 5869; R600-NEXT: CF_END 5870; R600-NEXT: PAD 5871; 5872; CM-LABEL: v_exp10_f32_from_fpext_bf16: 5873; CM: ; %bb.0: 5874; CM-NEXT: CF_END 5875; CM-NEXT: PAD 5876 %fpext = fpext bfloat %src to float 5877 %result = call float @llvm.exp10.f32(float %fpext) 5878 ret float %result 5879} 5880 5881define float @v_exp10_f32_from_fpext_math_f16_fast(i16 %src0.i, i16 %src1.i) { 5882; GCN-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_fast: 5883; GCN-SDAG: ; %bb.0: 5884; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5885; GCN-SDAG-NEXT: v_add_f16_e32 v0, v0, v1 5886; GCN-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5887; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 5888; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 5889; GCN-SDAG-NEXT: v_exp_f32_e32 v1, v1 5890; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 5891; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 5892; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 5893; 5894; GCN-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_fast: 5895; GCN-GISEL: ; %bb.0: 5896; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5897; GCN-GISEL-NEXT: v_add_f16_e32 v0, v0, v1 5898; GCN-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5899; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 5900; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 5901; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 5902; 5903; SI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_fast: 5904; SI-SDAG: ; %bb.0: 5905; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5906; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5907; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 5908; SI-SDAG-NEXT: s_mov_b32 s4, 0xc217b818 5909; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 5910; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42000000, v0 5911; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0 5912; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 5913; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v0 5914; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x40549000, v0 5915; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5916; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 5917; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 5918; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0xa4fb11f, v0 5919; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 5920; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 5921; 5922; SI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_fast: 5923; SI-GISEL: ; %bb.0: 5924; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5925; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5926; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 5927; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 5928; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 5929; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5930; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 5931; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 5932; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 5933; 5934; R600-LABEL: v_exp10_f32_from_fpext_math_f16_fast: 5935; R600: ; %bb.0: 5936; R600-NEXT: CF_END 5937; R600-NEXT: PAD 5938; 5939; CM-LABEL: v_exp10_f32_from_fpext_math_f16_fast: 5940; CM: ; %bb.0: 5941; CM-NEXT: CF_END 5942; CM-NEXT: PAD 5943 %src0 = bitcast i16 %src0.i to half 5944 %src1 = bitcast i16 %src1.i to half 5945 %fadd = fadd half %src0, %src1 5946 %fpext = fpext half %fadd to float 5947 %result = call fast float @llvm.exp10.f32(float %fpext) 5948 ret float %result 5949} 5950 5951define float @v_exp10_f32_from_fpext_math_f16_daz(i16 %src0.i, i16 %src1.i) #0 { 5952; VI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 5953; VI-SDAG: ; %bb.0: 5954; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5955; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1 5956; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 5957; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 5958; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5959; VI-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1 5960; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 5961; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 5962; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v1 5963; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4 5964; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549000, v1 5965; VI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 5966; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 5967; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 5968; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 5969; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 5970; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 5971; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 5972; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 5973; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 5974; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 5975; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 5976; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 5977; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 5978; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 5979; 5980; VI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 5981; VI-GISEL: ; %bb.0: 5982; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 5983; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1 5984; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 5985; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 5986; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 5987; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 5988; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 5989; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 5990; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 5991; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 5992; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 5993; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 5994; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 5995; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 5996; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 5997; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 5998; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 5999; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 6000; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 6001; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 6002; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 6003; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 6004; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 6005; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 6006; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 6007; 6008; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 6009; GFX900-SDAG: ; %bb.0: 6010; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6011; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v1 6012; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6013; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 6014; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x33979a37 6015; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 6016; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 6017; GFX900-SDAG-NEXT: v_rndne_f32_e32 v3, v1 6018; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 6019; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 6020; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 6021; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 6022; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 6023; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 6024; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 6025; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 6026; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 6027; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 6028; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 6029; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 6030; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 6031; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 6032; 6033; GFX900-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 6034; GFX900-GISEL: ; %bb.0: 6035; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6036; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v1 6037; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6038; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 6039; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 6040; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v0 6041; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v3 6042; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 6043; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v3 6044; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 6045; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 6046; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 6047; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 6048; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 6049; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 6050; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 6051; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 6052; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 6053; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 6054; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 6055; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 6056; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 6057; 6058; SI-SDAG-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 6059; SI-SDAG: ; %bb.0: 6060; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6061; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6062; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6063; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 6064; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 6065; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 6066; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 6067; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 6068; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 6069; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2 6070; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 6071; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 6072; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6073; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 6074; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 6075; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 6076; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 6077; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 6078; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 6079; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 6080; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 6081; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 6082; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6083; 6084; SI-GISEL-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 6085; SI-GISEL: ; %bb.0: 6086; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6087; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6088; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 6089; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37 6090; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 6091; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 6092; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6093; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 6094; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6095; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549a78, v0 6096; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v3 6097; SI-GISEL-NEXT: v_rndne_f32_e32 v4, v3 6098; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 6099; SI-GISEL-NEXT: v_sub_f32_e32 v2, v3, v4 6100; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 6101; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v3, v4 6102; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6103; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 6104; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x421a209b 6105; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 6106; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v3 6107; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 6108; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v4 6109; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc 6110; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6111; 6112; R600-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 6113; R600: ; %bb.0: 6114; R600-NEXT: CF_END 6115; R600-NEXT: PAD 6116; 6117; CM-LABEL: v_exp10_f32_from_fpext_math_f16_daz: 6118; CM: ; %bb.0: 6119; CM-NEXT: CF_END 6120; CM-NEXT: PAD 6121 %src0 = bitcast i16 %src0.i to half 6122 %src1 = bitcast i16 %src1.i to half 6123 %fadd = fadd half %src0, %src1 6124 %fpext = fpext half %fadd to float 6125 %result = call float @llvm.exp10.f32(float %fpext) 6126 ret float %result 6127} 6128 6129; FIXME: Fold out fp16_to_fp (FP_TO_FP16) on no-f16 targets 6130define half @v_exp10_f16(half %in) { 6131; GCN-LABEL: v_exp10_f16: 6132; GCN: ; %bb.0: 6133; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6134; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 6135; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6136; GCN-NEXT: v_exp_f32_e32 v0, v0 6137; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 6138; GCN-NEXT: s_setpc_b64 s[30:31] 6139; 6140; SI-SDAG-LABEL: v_exp10_f16: 6141; SI-SDAG: ; %bb.0: 6142; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6143; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6144; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6145; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6146; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6147; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6148; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6149; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6150; 6151; SI-GISEL-LABEL: v_exp10_f16: 6152; SI-GISEL: ; %bb.0: 6153; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6154; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6155; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6156; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6157; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6158; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6159; 6160; R600-LABEL: v_exp10_f16: 6161; R600: ; %bb.0: 6162; R600-NEXT: CF_END 6163; R600-NEXT: PAD 6164; 6165; CM-LABEL: v_exp10_f16: 6166; CM: ; %bb.0: 6167; CM-NEXT: CF_END 6168; CM-NEXT: PAD 6169 %result = call half @llvm.exp10.f16(half %in) 6170 ret half %result 6171} 6172 6173define half @v_exp10_fabs_f16(half %in) { 6174; GCN-LABEL: v_exp10_fabs_f16: 6175; GCN: ; %bb.0: 6176; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6177; GCN-NEXT: v_cvt_f32_f16_e64 v0, |v0| 6178; GCN-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6179; GCN-NEXT: v_exp_f32_e32 v0, v0 6180; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 6181; GCN-NEXT: s_setpc_b64 s[30:31] 6182; 6183; SI-SDAG-LABEL: v_exp10_fabs_f16: 6184; SI-SDAG: ; %bb.0: 6185; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6186; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6187; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0| 6188; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6189; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6190; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6191; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6192; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6193; 6194; SI-GISEL-LABEL: v_exp10_fabs_f16: 6195; SI-GISEL: ; %bb.0: 6196; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6197; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, |v0| 6198; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6199; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6200; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6201; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6202; 6203; R600-LABEL: v_exp10_fabs_f16: 6204; R600: ; %bb.0: 6205; R600-NEXT: CF_END 6206; R600-NEXT: PAD 6207; 6208; CM-LABEL: v_exp10_fabs_f16: 6209; CM: ; %bb.0: 6210; CM-NEXT: CF_END 6211; CM-NEXT: PAD 6212 %fabs = call half @llvm.fabs.f16(half %in) 6213 %result = call half @llvm.exp10.f16(half %fabs) 6214 ret half %result 6215} 6216 6217define half @v_exp10_fneg_fabs_f16(half %in) { 6218; GCN-SDAG-LABEL: v_exp10_fneg_fabs_f16: 6219; GCN-SDAG: ; %bb.0: 6220; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6221; GCN-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0| 6222; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v0 6223; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 6224; GCN-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6225; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 6226; 6227; GCN-GISEL-LABEL: v_exp10_fneg_fabs_f16: 6228; GCN-GISEL: ; %bb.0: 6229; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6230; GCN-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0| 6231; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6232; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 6233; GCN-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6234; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 6235; 6236; SI-SDAG-LABEL: v_exp10_fneg_fabs_f16: 6237; SI-SDAG: ; %bb.0: 6238; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6239; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6240; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0| 6241; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v0 6242; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6243; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6244; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6245; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6246; 6247; SI-GISEL-LABEL: v_exp10_fneg_fabs_f16: 6248; SI-GISEL: ; %bb.0: 6249; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6250; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0| 6251; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6252; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6253; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6254; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6255; 6256; R600-LABEL: v_exp10_fneg_fabs_f16: 6257; R600: ; %bb.0: 6258; R600-NEXT: CF_END 6259; R600-NEXT: PAD 6260; 6261; CM-LABEL: v_exp10_fneg_fabs_f16: 6262; CM: ; %bb.0: 6263; CM-NEXT: CF_END 6264; CM-NEXT: PAD 6265 %fabs = call half @llvm.fabs.f16(half %in) 6266 %fneg.fabs = fneg half %fabs 6267 %result = call half @llvm.exp10.f16(half %fneg.fabs) 6268 ret half %result 6269} 6270 6271define half @v_exp10_fneg_f16(half %in) { 6272; GCN-SDAG-LABEL: v_exp10_fneg_f16: 6273; GCN-SDAG: ; %bb.0: 6274; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6275; GCN-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6276; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0xbfb8aa3b, v0 6277; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0 6278; GCN-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6279; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] 6280; 6281; GCN-GISEL-LABEL: v_exp10_fneg_f16: 6282; GCN-GISEL: ; %bb.0: 6283; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6284; GCN-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0 6285; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6286; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 6287; GCN-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6288; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] 6289; 6290; SI-SDAG-LABEL: v_exp10_fneg_f16: 6291; SI-SDAG: ; %bb.0: 6292; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6293; SI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -v0 6294; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6295; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6296; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6297; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6298; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6299; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6300; 6301; SI-GISEL-LABEL: v_exp10_fneg_f16: 6302; SI-GISEL: ; %bb.0: 6303; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6304; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0 6305; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6306; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6307; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6308; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6309; 6310; R600-LABEL: v_exp10_fneg_f16: 6311; R600: ; %bb.0: 6312; R600-NEXT: CF_END 6313; R600-NEXT: PAD 6314; 6315; CM-LABEL: v_exp10_fneg_f16: 6316; CM: ; %bb.0: 6317; CM-NEXT: CF_END 6318; CM-NEXT: PAD 6319 %fneg = fneg half %in 6320 %result = call half @llvm.exp10.f16(half %fneg) 6321 ret half %result 6322} 6323 6324define half @v_exp10_f16_fast(half %in) { 6325; GCN-LABEL: v_exp10_f16_fast: 6326; GCN: ; %bb.0: 6327; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6328; GCN-NEXT: v_mul_f16_e32 v0, 0x3dc5, v0 6329; GCN-NEXT: v_exp_f16_e32 v0, v0 6330; GCN-NEXT: s_setpc_b64 s[30:31] 6331; 6332; SI-SDAG-LABEL: v_exp10_f16_fast: 6333; SI-SDAG: ; %bb.0: 6334; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6335; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6336; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6337; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0 6338; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6339; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6340; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6341; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6342; 6343; SI-GISEL-LABEL: v_exp10_f16_fast: 6344; SI-GISEL: ; %bb.0: 6345; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6346; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6347; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, 0x3dc5 6348; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 6349; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6350; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6351; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6352; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6353; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6354; 6355; R600-LABEL: v_exp10_f16_fast: 6356; R600: ; %bb.0: 6357; R600-NEXT: CF_END 6358; R600-NEXT: PAD 6359; 6360; CM-LABEL: v_exp10_f16_fast: 6361; CM: ; %bb.0: 6362; CM-NEXT: CF_END 6363; CM-NEXT: PAD 6364 %result = call fast half @llvm.exp10.f16(half %in) 6365 ret half %result 6366} 6367 6368define <2 x half> @v_exp10_v2f16(<2 x half> %in) { 6369; VI-SDAG-LABEL: v_exp10_v2f16: 6370; VI-SDAG: ; %bb.0: 6371; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6372; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6373; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6374; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6375; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6376; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6377; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6378; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6379; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6380; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1 6381; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 6382; 6383; VI-GISEL-LABEL: v_exp10_v2f16: 6384; VI-GISEL: ; %bb.0: 6385; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6386; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6387; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6388; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6389; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6390; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6391; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6392; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6393; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6394; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 6395; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 6396; 6397; GFX900-LABEL: v_exp10_v2f16: 6398; GFX900: ; %bb.0: 6399; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6400; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v0 6401; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6402; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6403; GFX900-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6404; GFX900-NEXT: v_exp_f32_e32 v1, v1 6405; GFX900-NEXT: v_exp_f32_e32 v0, v0 6406; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1 6407; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0 6408; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0 6409; GFX900-NEXT: s_setpc_b64 s[30:31] 6410; 6411; SI-SDAG-LABEL: v_exp10_v2f16: 6412; SI-SDAG: ; %bb.0: 6413; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6414; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6415; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6416; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6417; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6418; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6419; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6420; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6421; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6422; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6423; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6424; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6425; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6426; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6427; 6428; SI-GISEL-LABEL: v_exp10_v2f16: 6429; SI-GISEL: ; %bb.0: 6430; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6431; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6432; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 6433; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6434; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6435; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6436; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6437; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6438; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6439; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6440; 6441; R600-LABEL: v_exp10_v2f16: 6442; R600: ; %bb.0: 6443; R600-NEXT: CF_END 6444; R600-NEXT: PAD 6445; 6446; CM-LABEL: v_exp10_v2f16: 6447; CM: ; %bb.0: 6448; CM-NEXT: CF_END 6449; CM-NEXT: PAD 6450 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %in) 6451 ret <2 x half> %result 6452} 6453 6454define <2 x half> @v_exp10_fabs_v2f16(<2 x half> %in) { 6455; VI-SDAG-LABEL: v_exp10_fabs_v2f16: 6456; VI-SDAG: ; %bb.0: 6457; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6458; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6459; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0| 6460; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6461; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6462; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6463; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6464; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6465; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6466; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1 6467; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 6468; 6469; VI-GISEL-LABEL: v_exp10_fabs_v2f16: 6470; VI-GISEL: ; %bb.0: 6471; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6472; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 6473; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6474; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6475; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6476; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6477; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6478; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6479; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6480; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6481; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 6482; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 6483; 6484; GFX900-SDAG-LABEL: v_exp10_fabs_v2f16: 6485; GFX900-SDAG: ; %bb.0: 6486; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6487; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v0| 6488; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6489; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6490; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6491; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 6492; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 6493; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6494; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6495; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v0 6496; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 6497; 6498; GFX900-GISEL-LABEL: v_exp10_fabs_v2f16: 6499; GFX900-GISEL: ; %bb.0: 6500; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6501; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 6502; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6503; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6504; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6505; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6506; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 6507; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 6508; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6509; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6510; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 6511; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 6512; 6513; SI-SDAG-LABEL: v_exp10_fabs_v2f16: 6514; SI-SDAG: ; %bb.0: 6515; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6516; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6517; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6518; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0| 6519; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v1| 6520; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6521; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6522; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6523; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6524; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6525; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6526; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6527; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6528; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6529; 6530; SI-GISEL-LABEL: v_exp10_fabs_v2f16: 6531; SI-GISEL: ; %bb.0: 6532; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6533; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 6534; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 6535; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 6536; SI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 6537; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6538; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0 6539; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6540; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6541; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6542; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6543; SI-GISEL-NEXT: v_exp_f32_e32 v2, v0 6544; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v1 6545; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2 6546; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6547; 6548; R600-LABEL: v_exp10_fabs_v2f16: 6549; R600: ; %bb.0: 6550; R600-NEXT: CF_END 6551; R600-NEXT: PAD 6552; 6553; CM-LABEL: v_exp10_fabs_v2f16: 6554; CM: ; %bb.0: 6555; CM-NEXT: CF_END 6556; CM-NEXT: PAD 6557 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 6558 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %fabs) 6559 ret <2 x half> %result 6560} 6561 6562define <2 x half> @v_exp10_fneg_fabs_v2f16(<2 x half> %in) { 6563; VI-SDAG-LABEL: v_exp10_fneg_fabs_v2f16: 6564; VI-SDAG: ; %bb.0: 6565; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6566; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6567; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -|v0| 6568; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6569; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6570; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6571; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6572; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6573; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6574; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1 6575; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 6576; 6577; VI-GISEL-LABEL: v_exp10_fneg_fabs_v2f16: 6578; VI-GISEL: ; %bb.0: 6579; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6580; VI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0 6581; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6582; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6583; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6584; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6585; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6586; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6587; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6588; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6589; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 6590; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 6591; 6592; GFX900-SDAG-LABEL: v_exp10_fneg_fabs_v2f16: 6593; GFX900-SDAG: ; %bb.0: 6594; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6595; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, -|v0| 6596; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6597; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6598; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6599; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 6600; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 6601; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6602; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6603; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v0 6604; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 6605; 6606; GFX900-GISEL-LABEL: v_exp10_fneg_fabs_v2f16: 6607; GFX900-GISEL: ; %bb.0: 6608; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6609; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0 6610; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6611; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6612; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6613; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6614; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 6615; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 6616; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6617; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6618; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 6619; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 6620; 6621; SI-SDAG-LABEL: v_exp10_fneg_fabs_v2f16: 6622; SI-SDAG: ; %bb.0: 6623; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6624; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6625; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6626; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 6627; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1 6628; SI-SDAG-NEXT: v_or_b32_e32 v0, 0x80008000, v0 6629; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v0 6630; SI-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 6631; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6632; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6633; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6634; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6635; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6636; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6637; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v0 6638; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v1 6639; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v2 6640; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6641; 6642; SI-GISEL-LABEL: v_exp10_fneg_fabs_v2f16: 6643; SI-GISEL: ; %bb.0: 6644; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6645; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 6646; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 6647; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 6648; SI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0 6649; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6650; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0 6651; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6652; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6653; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6654; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6655; SI-GISEL-NEXT: v_exp_f32_e32 v2, v0 6656; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v1 6657; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2 6658; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6659; 6660; R600-LABEL: v_exp10_fneg_fabs_v2f16: 6661; R600: ; %bb.0: 6662; R600-NEXT: CF_END 6663; R600-NEXT: PAD 6664; 6665; CM-LABEL: v_exp10_fneg_fabs_v2f16: 6666; CM: ; %bb.0: 6667; CM-NEXT: CF_END 6668; CM-NEXT: PAD 6669 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 6670 %fneg.fabs = fneg <2 x half> %fabs 6671 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %fneg.fabs) 6672 ret <2 x half> %result 6673} 6674 6675define <2 x half> @v_exp10_fneg_v2f16(<2 x half> %in) { 6676; VI-SDAG-LABEL: v_exp10_fneg_v2f16: 6677; VI-SDAG: ; %bb.0: 6678; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6679; VI-SDAG-NEXT: v_cvt_f32_f16_sdwa v1, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6680; VI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -v0 6681; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6682; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6683; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6684; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6685; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6686; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6687; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1 6688; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 6689; 6690; VI-GISEL-LABEL: v_exp10_fneg_v2f16: 6691; VI-GISEL: ; %bb.0: 6692; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6693; VI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 6694; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6695; VI-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6696; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6697; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6698; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6699; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6700; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6701; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6702; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 6703; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 6704; 6705; GFX900-SDAG-LABEL: v_exp10_fneg_v2f16: 6706; GFX900-SDAG: ; %bb.0: 6707; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6708; GFX900-SDAG-NEXT: v_cvt_f32_f16_e64 v1, -v0 6709; GFX900-SDAG-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6710; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6711; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6712; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 6713; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0 6714; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6715; GFX900-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6716; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v0 6717; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 6718; 6719; GFX900-GISEL-LABEL: v_exp10_fneg_v2f16: 6720; GFX900-GISEL: ; %bb.0: 6721; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6722; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 6723; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6724; GFX900-GISEL-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6725; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6726; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6727; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 6728; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 6729; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6730; GFX900-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6731; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 6732; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 6733; 6734; SI-SDAG-LABEL: v_exp10_fneg_v2f16: 6735; SI-SDAG: ; %bb.0: 6736; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6737; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6738; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6739; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 6740; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1 6741; SI-SDAG-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 6742; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v0 6743; SI-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 6744; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6745; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6746; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6747; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6748; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6749; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6750; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v0 6751; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v1 6752; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v2 6753; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6754; 6755; SI-GISEL-LABEL: v_exp10_fneg_v2f16: 6756; SI-GISEL: ; %bb.0: 6757; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6758; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1 6759; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 6760; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 6761; SI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 6762; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v0 6763; SI-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0 6764; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6765; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6766; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6767; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6768; SI-GISEL-NEXT: v_exp_f32_e32 v2, v0 6769; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v1 6770; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2 6771; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6772; 6773; R600-LABEL: v_exp10_fneg_v2f16: 6774; R600: ; %bb.0: 6775; R600-NEXT: CF_END 6776; R600-NEXT: PAD 6777; 6778; CM-LABEL: v_exp10_fneg_v2f16: 6779; CM: ; %bb.0: 6780; CM-NEXT: CF_END 6781; CM-NEXT: PAD 6782 %fneg = fneg <2 x half> %in 6783 %result = call <2 x half> @llvm.exp10.v2f16(<2 x half> %fneg) 6784 ret <2 x half> %result 6785} 6786 6787define <2 x half> @v_exp10_v2f16_fast(<2 x half> %in) { 6788; VI-SDAG-LABEL: v_exp10_v2f16_fast: 6789; VI-SDAG: ; %bb.0: 6790; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6791; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x3dc5 6792; VI-SDAG-NEXT: v_mul_f16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 6793; VI-SDAG-NEXT: v_mul_f16_e32 v0, 0x3dc5, v0 6794; VI-SDAG-NEXT: v_exp_f16_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6795; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0 6796; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1 6797; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 6798; 6799; VI-GISEL-LABEL: v_exp10_v2f16_fast: 6800; VI-GISEL: ; %bb.0: 6801; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6802; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3dc5 6803; VI-GISEL-NEXT: v_mul_f16_e32 v2, 0x3dc5, v0 6804; VI-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 6805; VI-GISEL-NEXT: v_exp_f16_e32 v2, v2 6806; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6807; VI-GISEL-NEXT: v_or_b32_e32 v0, v2, v0 6808; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 6809; 6810; GFX900-SDAG-LABEL: v_exp10_v2f16_fast: 6811; GFX900-SDAG: ; %bb.0: 6812; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6813; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x3dc5 6814; GFX900-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v0 6815; GFX900-SDAG-NEXT: v_mul_f16_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 6816; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v1 6817; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0 6818; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v1, v0 6819; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 6820; 6821; GFX900-GISEL-LABEL: v_exp10_v2f16_fast: 6822; GFX900-GISEL: ; %bb.0: 6823; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6824; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3dc5 6825; GFX900-GISEL-NEXT: v_mul_f16_e32 v2, 0x3dc5, v0 6826; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 6827; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v2 6828; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v0 6829; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2 6830; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 6831; 6832; SI-SDAG-LABEL: v_exp10_v2f16_fast: 6833; SI-SDAG: ; %bb.0: 6834; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6835; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6836; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6837; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6838; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6839; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0 6840; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1 6841; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6842; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6843; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6844; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6845; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6846; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6847; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6848; 6849; SI-GISEL-LABEL: v_exp10_v2f16_fast: 6850; SI-GISEL: ; %bb.0: 6851; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6852; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6853; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, 0x3dc5 6854; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 6855; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v2 6856; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2 6857; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6858; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6859; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6860; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 6861; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6862; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6863; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6864; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6865; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6866; 6867; R600-LABEL: v_exp10_v2f16_fast: 6868; R600: ; %bb.0: 6869; R600-NEXT: CF_END 6870; R600-NEXT: PAD 6871; 6872; CM-LABEL: v_exp10_v2f16_fast: 6873; CM: ; %bb.0: 6874; CM-NEXT: CF_END 6875; CM-NEXT: PAD 6876 %result = call fast <2 x half> @llvm.exp10.v2f16(<2 x half> %in) 6877 ret <2 x half> %result 6878} 6879 6880define <3 x half> @v_exp10_v3f16(<3 x half> %in) { 6881; VI-LABEL: v_exp10_v3f16: 6882; VI: ; %bb.0: 6883; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6884; VI-NEXT: v_cvt_f32_f16_e32 v2, v0 6885; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6886; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 6887; VI-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2 6888; VI-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6889; VI-NEXT: v_exp_f32_e32 v2, v2 6890; VI-NEXT: v_exp_f32_e32 v0, v0 6891; VI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6892; VI-NEXT: v_exp_f32_e32 v1, v1 6893; VI-NEXT: v_cvt_f16_f32_e32 v2, v2 6894; VI-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6895; VI-NEXT: v_cvt_f16_f32_e32 v1, v1 6896; VI-NEXT: v_or_b32_e32 v0, v2, v0 6897; VI-NEXT: s_setpc_b64 s[30:31] 6898; 6899; GFX900-LABEL: v_exp10_v3f16: 6900; GFX900: ; %bb.0: 6901; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6902; GFX900-NEXT: v_cvt_f32_f16_e32 v2, v0 6903; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 6904; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 6905; GFX900-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2 6906; GFX900-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6907; GFX900-NEXT: v_exp_f32_e32 v2, v2 6908; GFX900-NEXT: v_exp_f32_e32 v0, v0 6909; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6910; GFX900-NEXT: v_exp_f32_e32 v1, v1 6911; GFX900-NEXT: v_cvt_f16_f32_e32 v2, v2 6912; GFX900-NEXT: v_cvt_f16_f32_e32 v0, v0 6913; GFX900-NEXT: v_cvt_f16_f32_e32 v1, v1 6914; GFX900-NEXT: v_pack_b32_f16 v0, v2, v0 6915; GFX900-NEXT: s_setpc_b64 s[30:31] 6916; 6917; SI-SDAG-LABEL: v_exp10_v3f16: 6918; SI-SDAG: ; %bb.0: 6919; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6920; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6921; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6922; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 6923; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6924; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6925; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 6926; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6927; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6928; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2 6929; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 6930; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 6931; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 6932; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 6933; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 6934; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 6935; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 6936; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 6937; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 6938; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 6939; 6940; SI-GISEL-LABEL: v_exp10_v3f16: 6941; SI-GISEL: ; %bb.0: 6942; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6943; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 6944; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 6945; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 6946; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0 6947; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v1 6948; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v2 6949; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 6950; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 6951; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2 6952; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 6953; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 6954; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 6955; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 6956; 6957; R600-LABEL: v_exp10_v3f16: 6958; R600: ; %bb.0: 6959; R600-NEXT: CF_END 6960; R600-NEXT: PAD 6961; 6962; CM-LABEL: v_exp10_v3f16: 6963; CM: ; %bb.0: 6964; CM-NEXT: CF_END 6965; CM-NEXT: PAD 6966 %result = call <3 x half> @llvm.exp10.v3f16(<3 x half> %in) 6967 ret <3 x half> %result 6968} 6969 6970define <3 x half> @v_exp10_v3f16_afn(<3 x half> %in) { 6971; VI-SDAG-LABEL: v_exp10_v3f16_afn: 6972; VI-SDAG: ; %bb.0: 6973; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6974; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x3dc5 6975; VI-SDAG-NEXT: v_mul_f16_e32 v2, 0x3dc5, v0 6976; VI-SDAG-NEXT: v_mul_f16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 6977; VI-SDAG-NEXT: v_exp_f16_e32 v2, v2 6978; VI-SDAG-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6979; VI-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v1 6980; VI-SDAG-NEXT: v_exp_f16_e32 v1, v1 6981; VI-SDAG-NEXT: v_or_b32_e32 v0, v2, v0 6982; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 6983; 6984; VI-GISEL-LABEL: v_exp10_v3f16_afn: 6985; VI-GISEL: ; %bb.0: 6986; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 6987; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3dc5 6988; VI-GISEL-NEXT: v_mul_f16_e32 v3, 0x3dc5, v0 6989; VI-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 6990; VI-GISEL-NEXT: v_exp_f16_e32 v3, v3 6991; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 6992; VI-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v1 6993; VI-GISEL-NEXT: v_exp_f16_e32 v1, v1 6994; VI-GISEL-NEXT: v_or_b32_e32 v0, v3, v0 6995; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 6996; 6997; GFX900-SDAG-LABEL: v_exp10_v3f16_afn: 6998; GFX900-SDAG: ; %bb.0: 6999; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7000; GFX900-SDAG-NEXT: s_movk_i32 s4, 0x3dc5 7001; GFX900-SDAG-NEXT: v_mul_f16_e32 v2, 0x3dc5, v0 7002; GFX900-SDAG-NEXT: v_mul_f16_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 7003; GFX900-SDAG-NEXT: v_exp_f16_e32 v2, v2 7004; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0 7005; GFX900-SDAG-NEXT: v_mul_f16_e32 v1, 0x3dc5, v1 7006; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v1 7007; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0 7008; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 7009; 7010; GFX900-GISEL-LABEL: v_exp10_v3f16_afn: 7011; GFX900-GISEL: ; %bb.0: 7012; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7013; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3dc5 7014; GFX900-GISEL-NEXT: v_mul_f16_e32 v3, 0x3dc5, v0 7015; GFX900-GISEL-NEXT: v_mul_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 7016; GFX900-GISEL-NEXT: v_exp_f16_e32 v3, v3 7017; GFX900-GISEL-NEXT: v_exp_f16_e32 v0, v0 7018; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x3dc5, v1 7019; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1 7020; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v3 7021; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 7022; 7023; SI-SDAG-LABEL: v_exp10_v3f16_afn: 7024; SI-SDAG: ; %bb.0: 7025; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7026; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 7027; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 7028; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 7029; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 7030; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 7031; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 7032; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0 7033; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8a000, v1 7034; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2 7035; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0 7036; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 7037; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 7038; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 7039; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 7040; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 7041; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 7042; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 7043; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 7044; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 7045; 7046; SI-GISEL-LABEL: v_exp10_v3f16_afn: 7047; SI-GISEL: ; %bb.0: 7048; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7049; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 7050; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v3, 0x3dc5 7051; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 7052; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 7053; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v3 7054; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v3 7055; SI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3 7056; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 7057; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 7058; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 7059; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 7060; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 7061; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 7062; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 7063; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 7064; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2 7065; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 7066; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 7067; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 7068; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 7069; 7070; R600-LABEL: v_exp10_v3f16_afn: 7071; R600: ; %bb.0: 7072; R600-NEXT: CF_END 7073; R600-NEXT: PAD 7074; 7075; CM-LABEL: v_exp10_v3f16_afn: 7076; CM: ; %bb.0: 7077; CM-NEXT: CF_END 7078; CM-NEXT: PAD 7079 %result = call afn <3 x half> @llvm.exp10.v3f16(<3 x half> %in) 7080 ret <3 x half> %result 7081} 7082 7083define float @v_exp10_f32_contract(float %in) { 7084; VI-SDAG-LABEL: v_exp10_f32_contract: 7085; VI-SDAG: ; %bb.0: 7086; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7087; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 7088; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 7089; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 7090; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 7091; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 7092; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 7093; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 7094; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 7095; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 7096; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 7097; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 7098; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 7099; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 7100; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7101; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7102; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 7103; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 7104; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 7105; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 7106; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 7107; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 7108; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 7109; 7110; VI-GISEL-LABEL: v_exp10_f32_contract: 7111; VI-GISEL: ; %bb.0: 7112; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7113; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 7114; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 7115; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 7116; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 7117; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 7118; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 7119; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 7120; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 7121; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 7122; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 7123; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 7124; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 7125; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 7126; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 7127; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 7128; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7129; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7130; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 7131; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 7132; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 7133; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 7134; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 7135; 7136; GFX900-SDAG-LABEL: v_exp10_f32_contract: 7137; GFX900-SDAG: ; %bb.0: 7138; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7139; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 7140; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 7141; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 7142; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 7143; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 7144; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 7145; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 7146; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 7147; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 7148; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 7149; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7150; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7151; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 7152; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 7153; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 7154; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 7155; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 7156; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 7157; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 7158; 7159; GFX900-GISEL-LABEL: v_exp10_f32_contract: 7160; GFX900-GISEL: ; %bb.0: 7161; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7162; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 7163; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 7164; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 7165; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 7166; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 7167; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 7168; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 7169; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 7170; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 7171; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 7172; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 7173; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 7174; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7175; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7176; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 7177; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 7178; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 7179; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 7180; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 7181; 7182; SI-SDAG-LABEL: v_exp10_f32_contract: 7183; SI-SDAG: ; %bb.0: 7184; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7185; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 7186; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 7187; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 7188; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 7189; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 7190; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 7191; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 7192; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 7193; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 7194; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 7195; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7196; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7197; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 7198; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 7199; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 7200; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 7201; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 7202; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 7203; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 7204; 7205; SI-GISEL-LABEL: v_exp10_f32_contract: 7206; SI-GISEL: ; %bb.0: 7207; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7208; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 7209; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 7210; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 7211; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 7212; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 7213; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 7214; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 7215; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 7216; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 7217; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 7218; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 7219; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 7220; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7221; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7222; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 7223; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 7224; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 7225; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 7226; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 7227; 7228; R600-LABEL: v_exp10_f32_contract: 7229; R600: ; %bb.0: 7230; R600-NEXT: CF_END 7231; R600-NEXT: PAD 7232; 7233; CM-LABEL: v_exp10_f32_contract: 7234; CM: ; %bb.0: 7235; CM-NEXT: CF_END 7236; CM-NEXT: PAD 7237 %result = call contract float @llvm.exp10.f32(float %in) 7238 ret float %result 7239} 7240 7241define float @v_exp10_f32_contract_daz(float %in) #0 { 7242; VI-SDAG-LABEL: v_exp10_f32_contract_daz: 7243; VI-SDAG: ; %bb.0: 7244; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7245; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 7246; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 7247; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 7248; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 7249; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 7250; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 7251; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 7252; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 7253; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 7254; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 7255; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 7256; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 7257; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 7258; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7259; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7260; VI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 7261; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 7262; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 7263; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 7264; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 7265; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 7266; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 7267; 7268; VI-GISEL-LABEL: v_exp10_f32_contract_daz: 7269; VI-GISEL: ; %bb.0: 7270; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7271; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 7272; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 7273; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 7274; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 7275; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 7276; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 7277; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 7278; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 7279; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 7280; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 7281; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 7282; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 7283; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 7284; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 7285; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 7286; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7287; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7288; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 7289; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 7290; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 7291; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 7292; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 7293; 7294; GFX900-SDAG-LABEL: v_exp10_f32_contract_daz: 7295; GFX900-SDAG: ; %bb.0: 7296; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7297; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 7298; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 7299; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 7300; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 7301; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 7302; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 7303; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 7304; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 7305; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 7306; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 7307; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7308; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7309; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 7310; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 7311; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 7312; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 7313; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 7314; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 7315; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 7316; 7317; GFX900-GISEL-LABEL: v_exp10_f32_contract_daz: 7318; GFX900-GISEL: ; %bb.0: 7319; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7320; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 7321; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 7322; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 7323; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 7324; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 7325; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 7326; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 7327; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 7328; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 7329; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 7330; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 7331; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 7332; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7333; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7334; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 7335; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 7336; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 7337; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 7338; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 7339; 7340; SI-SDAG-LABEL: v_exp10_f32_contract_daz: 7341; SI-SDAG: ; %bb.0: 7342; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7343; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 7344; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 7345; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 7346; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 7347; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 7348; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 7349; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 7350; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 7351; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 7352; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 7353; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7354; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7355; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b 7356; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 7357; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 7358; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 7359; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 7360; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc 7361; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 7362; 7363; SI-GISEL-LABEL: v_exp10_f32_contract_daz: 7364; SI-GISEL: ; %bb.0: 7365; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7366; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 7367; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 7368; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 7369; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 7370; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 7371; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 7372; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 7373; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 7374; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 7375; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 7376; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 7377; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 7378; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7379; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7380; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b 7381; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc 7382; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 7383; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 7384; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 7385; 7386; R600-LABEL: v_exp10_f32_contract_daz: 7387; R600: ; %bb.0: 7388; R600-NEXT: CF_END 7389; R600-NEXT: PAD 7390; 7391; CM-LABEL: v_exp10_f32_contract_daz: 7392; CM: ; %bb.0: 7393; CM-NEXT: CF_END 7394; CM-NEXT: PAD 7395 %result = call contract float @llvm.exp10.f32(float %in) 7396 ret float %result 7397} 7398 7399define float @v_exp10_f32_contract_nnan_ninf(float %in) { 7400; VI-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf: 7401; VI-SDAG: ; %bb.0: 7402; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7403; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 7404; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 7405; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x40549000, v1 7406; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3a2784bc, v4 7407; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x40549000, v4 7408; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 7409; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 7410; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 7411; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 7412; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4 7413; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1 7414; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1 7415; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3 7416; VI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7417; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7418; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 7419; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 7420; VI-SDAG-NEXT: s_setpc_b64 s[30:31] 7421; 7422; VI-GISEL-LABEL: v_exp10_f32_contract_nnan_ninf: 7423; VI-GISEL: ; %bb.0: 7424; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7425; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 7426; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 7427; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3a2784bc, v2 7428; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549000, v2 7429; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x40549000, v1 7430; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 7431; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3a2784bc, v1 7432; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 7433; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3 7434; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2 7435; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1 7436; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2 7437; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 7438; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 7439; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7440; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7441; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 7442; VI-GISEL-NEXT: s_setpc_b64 s[30:31] 7443; 7444; GFX900-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf: 7445; GFX900-SDAG: ; %bb.0: 7446; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7447; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 7448; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 7449; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1 7450; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 7451; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 7452; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 7453; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 7454; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 7455; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1 7456; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 7457; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7458; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7459; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2 7460; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 7461; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] 7462; 7463; GFX900-GISEL-LABEL: v_exp10_f32_contract_nnan_ninf: 7464; GFX900-GISEL: ; %bb.0: 7465; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7466; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 7467; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 7468; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 7469; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 7470; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 7471; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2 7472; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 7473; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 7474; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 7475; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 7476; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 7477; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7478; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7479; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 7480; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] 7481; 7482; SI-SDAG-LABEL: v_exp10_f32_contract_nnan_ninf: 7483; SI-SDAG: ; %bb.0: 7484; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7485; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0 7486; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78 7487; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 7488; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 7489; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 7490; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37 7491; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 7492; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 7493; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 7494; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2 7495; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4 7496; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 7497; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2 7498; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc 7499; SI-SDAG-NEXT: s_setpc_b64 s[30:31] 7500; 7501; SI-GISEL-LABEL: v_exp10_f32_contract_nnan_ninf: 7502; SI-GISEL: ; %bb.0: 7503; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 7504; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78 7505; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0 7506; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2 7507; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37 7508; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1 7509; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2 7510; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 7511; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1 7512; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 7513; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 7514; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 7515; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4 7516; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 7517; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc 7518; SI-GISEL-NEXT: s_setpc_b64 s[30:31] 7519; 7520; R600-LABEL: v_exp10_f32_contract_nnan_ninf: 7521; R600: ; %bb.0: 7522; R600-NEXT: CF_END 7523; R600-NEXT: PAD 7524; 7525; CM-LABEL: v_exp10_f32_contract_nnan_ninf: 7526; CM: ; %bb.0: 7527; CM-NEXT: CF_END 7528; CM-NEXT: PAD 7529 %result = call contract nnan ninf float @llvm.exp10.f32(float %in) 7530 ret float %result 7531} 7532 7533declare float @llvm.fabs.f32(float) #2 7534declare float @llvm.exp10.f32(float) #2 7535declare <2 x float> @llvm.exp10.v2f32(<2 x float>) #2 7536declare <3 x float> @llvm.exp10.v3f32(<3 x float>) #2 7537declare <4 x float> @llvm.exp10.v4f32(<4 x float>) #2 7538declare half @llvm.fabs.f16(half) #2 7539declare half @llvm.exp10.f16(half) #2 7540declare <2 x half> @llvm.exp10.v2f16(<2 x half>) #2 7541declare <3 x half> @llvm.exp10.v3f16(<3 x half>) #2 7542declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 7543 7544attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } 7545attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } 7546attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 7547