xref: /llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll (revision 6548b6354d1d990e1c98736f5e7c3de876bedc8e)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; FIXME: Check gfx90a, 940. 908 should fail to select.
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200 %s
4
5define <2 x bfloat> @struct_ptr_buffer_atomic_add_v2bf16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x bfloat> %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) #0 {
6; GFX1200-LABEL: struct_ptr_buffer_atomic_add_v2bf16_rtn__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
7; GFX1200:       ; %bb.0:
8; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
9; GFX1200-NEXT:    s_wait_expcnt 0x0
10; GFX1200-NEXT:    s_wait_samplecnt 0x0
11; GFX1200-NEXT:    s_wait_bvhcnt 0x0
12; GFX1200-NEXT:    s_wait_kmcnt 0x0
13; GFX1200-NEXT:    buffer_atomic_pk_add_bf16 v0, v[1:2], s[0:3], s16 idxen offen th:TH_ATOMIC_RETURN
14; GFX1200-NEXT:    s_wait_loadcnt 0x0
15; GFX1200-NEXT:    s_setpc_b64 s[30:31]
16  %ret = call <2 x bfloat> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16(<2 x bfloat> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
17  ret <2 x bfloat> %ret
18}
19
20define void @struct_ptr_buffer_atomic_add_v2bf16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x bfloat> %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) #0 {
21; GFX1200-LABEL: struct_ptr_buffer_atomic_add_v2bf16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
22; GFX1200:       ; %bb.0:
23; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
24; GFX1200-NEXT:    s_wait_expcnt 0x0
25; GFX1200-NEXT:    s_wait_samplecnt 0x0
26; GFX1200-NEXT:    s_wait_bvhcnt 0x0
27; GFX1200-NEXT:    s_wait_kmcnt 0x0
28; GFX1200-NEXT:    buffer_atomic_pk_add_bf16 v0, v[1:2], s[0:3], s16 idxen offen
29; GFX1200-NEXT:    s_setpc_b64 s[30:31]
30  %unused = call <2 x bfloat> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16(<2 x bfloat> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
31  ret void
32}
33
34; Test waterfall loop
35define <2 x bfloat> @struct_ptr_buffer_atomic_add_v2bf16_rtn__vgpr_val__vgpr_rsrc__vgpr_voffset__vgpr_soffset(<2 x bfloat> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) #0 {
36; GFX1200-LABEL: struct_ptr_buffer_atomic_add_v2bf16_rtn__vgpr_val__vgpr_rsrc__vgpr_voffset__vgpr_soffset:
37; GFX1200:       ; %bb.0:
38; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
39; GFX1200-NEXT:    s_wait_expcnt 0x0
40; GFX1200-NEXT:    s_wait_samplecnt 0x0
41; GFX1200-NEXT:    s_wait_bvhcnt 0x0
42; GFX1200-NEXT:    s_wait_kmcnt 0x0
43; GFX1200-NEXT:    s_mov_b32 s2, exec_lo
44; GFX1200-NEXT:  .LBB2_1: ; =>This Inner Loop Header: Depth=1
45; GFX1200-NEXT:    v_readfirstlane_b32 s4, v1
46; GFX1200-NEXT:    v_readfirstlane_b32 s5, v2
47; GFX1200-NEXT:    v_readfirstlane_b32 s6, v3
48; GFX1200-NEXT:    v_readfirstlane_b32 s7, v4
49; GFX1200-NEXT:    v_readfirstlane_b32 s3, v7
50; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
51; GFX1200-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
52; GFX1200-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
53; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
54; GFX1200-NEXT:    v_cmp_eq_u32_e64 s1, s3, v7
55; GFX1200-NEXT:    s_wait_alu 0xfffe
56; GFX1200-NEXT:    s_and_b32 s0, vcc_lo, s0
57; GFX1200-NEXT:    s_wait_alu 0xfffe
58; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
59; GFX1200-NEXT:    s_and_b32 s0, s0, s1
60; GFX1200-NEXT:    s_wait_alu 0xfffe
61; GFX1200-NEXT:    s_and_saveexec_b32 s0, s0
62; GFX1200-NEXT:    s_wait_loadcnt 0x0
63; GFX1200-NEXT:    buffer_atomic_pk_add_bf16 v0, v[5:6], s[4:7], s3 idxen offen th:TH_ATOMIC_RETURN
64; GFX1200-NEXT:    ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
65; GFX1200-NEXT:    ; implicit-def: $vgpr7
66; GFX1200-NEXT:    ; implicit-def: $vgpr5_vgpr6
67; GFX1200-NEXT:    s_wait_alu 0xfffe
68; GFX1200-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
69; GFX1200-NEXT:    s_cbranch_execnz .LBB2_1
70; GFX1200-NEXT:  ; %bb.2:
71; GFX1200-NEXT:    s_mov_b32 exec_lo, s2
72; GFX1200-NEXT:    s_wait_loadcnt 0x0
73; GFX1200-NEXT:    s_wait_alu 0xfffe
74; GFX1200-NEXT:    s_setpc_b64 s[30:31]
75  %ret = call <2 x bfloat> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16(<2 x bfloat> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
76  ret <2 x bfloat> %ret
77}
78
79define void @struct_ptr_buffer_atomic_add_v2bf16_noret__vgpr_val__vgpr_rsrc__vgpr_voffset__vgpr_soffset(<2 x bfloat> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) #0 {
80; GFX1200-LABEL: struct_ptr_buffer_atomic_add_v2bf16_noret__vgpr_val__vgpr_rsrc__vgpr_voffset__vgpr_soffset:
81; GFX1200:       ; %bb.0:
82; GFX1200-NEXT:    s_wait_loadcnt_dscnt 0x0
83; GFX1200-NEXT:    s_wait_expcnt 0x0
84; GFX1200-NEXT:    s_wait_samplecnt 0x0
85; GFX1200-NEXT:    s_wait_bvhcnt 0x0
86; GFX1200-NEXT:    s_wait_kmcnt 0x0
87; GFX1200-NEXT:    s_mov_b32 s2, exec_lo
88; GFX1200-NEXT:  .LBB3_1: ; =>This Inner Loop Header: Depth=1
89; GFX1200-NEXT:    v_readfirstlane_b32 s4, v1
90; GFX1200-NEXT:    v_readfirstlane_b32 s5, v2
91; GFX1200-NEXT:    v_readfirstlane_b32 s6, v3
92; GFX1200-NEXT:    v_readfirstlane_b32 s7, v4
93; GFX1200-NEXT:    v_readfirstlane_b32 s3, v7
94; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
95; GFX1200-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[1:2]
96; GFX1200-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[3:4]
97; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
98; GFX1200-NEXT:    v_cmp_eq_u32_e64 s1, s3, v7
99; GFX1200-NEXT:    s_wait_alu 0xfffe
100; GFX1200-NEXT:    s_and_b32 s0, vcc_lo, s0
101; GFX1200-NEXT:    s_wait_alu 0xfffe
102; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
103; GFX1200-NEXT:    s_and_b32 s0, s0, s1
104; GFX1200-NEXT:    s_wait_alu 0xfffe
105; GFX1200-NEXT:    s_and_saveexec_b32 s0, s0
106; GFX1200-NEXT:    buffer_atomic_pk_add_bf16 v0, v[5:6], s[4:7], s3 idxen offen
107; GFX1200-NEXT:    ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4
108; GFX1200-NEXT:    ; implicit-def: $vgpr7
109; GFX1200-NEXT:    ; implicit-def: $vgpr0
110; GFX1200-NEXT:    ; implicit-def: $vgpr5_vgpr6
111; GFX1200-NEXT:    s_wait_alu 0xfffe
112; GFX1200-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
113; GFX1200-NEXT:    s_cbranch_execnz .LBB3_1
114; GFX1200-NEXT:  ; %bb.2:
115; GFX1200-NEXT:    s_mov_b32 exec_lo, s2
116; GFX1200-NEXT:    s_wait_alu 0xfffe
117; GFX1200-NEXT:    s_setpc_b64 s[30:31]
118  %ret = call <2 x bfloat> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16(<2 x bfloat> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
119  ret void
120}
121
122declare <2 x bfloat> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16(<2 x bfloat>, ptr addrspace(8), i32, i32, i32, i32 immarg)
123
124attributes #0 = { nounwind }
125