xref: /llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX906
2; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
3; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
4; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
5; RUN: llc -mtriple=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11
7
8declare i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 %clamp)
9
10; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_clamp
11; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
12; GFX10:  v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
13; GFX11:  v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,1,0] clamp{{$}}
14define amdgpu_kernel void @test_llvm_amdgcn_sdot4_clamp(
15    ptr addrspace(1) %r,
16    ptr addrspace(1) %a,
17    ptr addrspace(1) %b,
18    ptr addrspace(1) %c) {
19entry:
20  %a.val = load <4 x i8>, ptr addrspace(1) %a
21  %b.val = load <4 x i8>, ptr addrspace(1) %b
22  %a.val.cast = bitcast <4 x i8> %a.val to i32
23  %b.val.cast = bitcast <4 x i8> %b.val to i32
24  %c.val = load i32, ptr addrspace(1) %c
25  %r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1)
26  store i32 %r.val, ptr addrspace(1) %r
27  ret void
28}
29
30; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_no_clamp
31; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
32; GFX10:  v_dot4c_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
33; GF11:   v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}} neg_lo:[1,1,0]{{$}}
34define amdgpu_kernel void @test_llvm_amdgcn_sdot4_no_clamp(
35    ptr addrspace(1) %r,
36    ptr addrspace(1) %a,
37    ptr addrspace(1) %b,
38    ptr addrspace(1) %c) {
39entry:
40  %a.val = load <4 x i8>, ptr addrspace(1) %a
41  %b.val = load <4 x i8>, ptr addrspace(1) %b
42  %a.val.cast = bitcast <4 x i8> %a.val to i32
43  %b.val.cast = bitcast <4 x i8> %b.val to i32
44  %c.val = load i32, ptr addrspace(1) %c
45  %r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0)
46  store i32 %r.val, ptr addrspace(1) %r
47  ret void
48}
49