1; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT,PREGFX10,PREGFX10-OPT %s 2; RUN: llc -O0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-NOOPT,PREGFX10,PREGFX10-NOOPT %s 3; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s 4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -amdgpu-enable-vopd=0 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s 5 6; FIXME: The register allocator / scheduler should be able to avoid these hazards. 7 8; VI-LABEL: {{^}}dpp_test: 9; VI: v_mov_b32_e32 v0, s{{[0-9]+}} 10; VI-NOOPT: v_mov_b32_e32 v1, s{{[0-9]+}} 11; PREGFX10: s_nop 1 12; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11] 13; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11] 14define amdgpu_kernel void @dpp_test(ptr addrspace(1) %out, i32 %in) { 15 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0 16 store i32 %tmp0, ptr addrspace(1) %out 17 ret void 18} 19 20; VI-LABEL: {{^}}dpp_wait_states: 21; VI-NOOPT: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s{{[0-9]+}} 22; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}} 23; PREGFX10: s_nop 1 24; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 25; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl: 26; PREGFX10: s_nop 1 27; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 28; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 29define amdgpu_kernel void @dpp_wait_states(ptr addrspace(1) %out, i32 %in) { 30 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0 31 %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0 32 store i32 %tmp1, ptr addrspace(1) %out 33 ret void 34} 35 36; VI-LABEL: {{^}}dpp_first_in_bb: 37; VI: ; %endif 38; PREGFX10-NOOPT: s_waitcnt 39; PREGFX10-NOOPT: v_mov_b32_e32 40; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 41; PREGFX10-OPT: s_mov_b32 42; PREGFX10-OPT: s_mov_b32 43; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 44; PREGFX10: s_nop 1 45; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 46define amdgpu_kernel void @dpp_first_in_bb(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cond, float %a, float %b) { 47 %cmp = fcmp oeq float %cond, 0.0 48 br i1 %cmp, label %if, label %else 49 50if: 51 %out_val = load float, ptr addrspace(1) %out 52 %if_val = fadd float %a, %out_val 53 br label %endif 54 55else: 56 %in_val = load float, ptr addrspace(1) %in 57 %else_val = fadd float %b, %in_val 58 br label %endif 59 60endif: 61 %val = phi float [%if_val, %if], [%else_val, %else] 62 %val_i32 = bitcast float %val to i32 63 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %val_i32, i32 1, i32 1, i32 1, i1 1) #0 64 %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0 65 %tmp2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp1, i32 1, i32 1, i32 1, i1 1) #0 66 %tmp_float = bitcast i32 %tmp2 to float 67 store float %tmp_float, ptr addrspace(1) %out 68 ret void 69} 70 71; VI-LABEL: {{^}}mov_dpp64_test: 72; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 73; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 74define amdgpu_kernel void @mov_dpp64_test(ptr addrspace(1) %out, i64 %in1) { 75 %tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 %in1, i32 1, i32 1, i32 1, i1 0) #0 76 store i64 %tmp0, ptr addrspace(1) %out 77 ret void 78} 79 80; VI-LABEL: {{^}}mov_dpp64_imm_test: 81; VI-OPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9 82; VI-OPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x7047 83; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], s[[SOLD_LO]] 84; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], s[[SOLD_HI]] 85; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 86; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 87; VI-NOOPT-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 88define amdgpu_kernel void @mov_dpp64_imm_test(ptr addrspace(1) %out) { 89 %tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 123451234512345, i32 1, i32 1, i32 1, i1 0) #0 90 store i64 %tmp0, ptr addrspace(1) %out 91 ret void 92} 93 94declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #0 95declare i64 @llvm.amdgcn.mov.dpp.i64(i64, i32, i32, i32, i1) #0 96 97attributes #0 = { nounwind readnone convergent } 98 99