1; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX908 %s 2; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX908 %s 3; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX90A %s 4 5declare <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32, i32, <16 x i32>, i32, i32, i32) 6declare <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32, i32, <4 x i32>, i32, i32, i32) 7 8; GCN-LABEL: {{^}}test_mfma_i32_32x32x8i8: 9; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 10; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 11; GCN-DAG: s_load_dwordx16 12; GFX908-DAG-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} 13; GFX90A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}} 14; GCN: v_mfma_i32_32x32x8i8 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 15; GFX908-COUNT-16: v_accvgpr_read_b32 16; GFX908: global_store_dwordx4 17; GFX90A-NOT: v_accvgpr_read_b32 18; GFX90A-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}] 19define amdgpu_kernel void @test_mfma_i32_32x32x8i8(ptr addrspace(1) %arg) #0 { 20bb: 21 %in.1 = load <16 x i32>, ptr addrspace(1) %arg 22 %mai.1 = tail call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32 1, i32 2, <16 x i32> %in.1, i32 1, i32 2, i32 3) 23 store <16 x i32> %mai.1, ptr addrspace(1) %arg 24 ret void 25} 26 27; GCN-LABEL: {{^}}test_mfma_i32_16x16x16i8: 28; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 29; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 30; GCN: s_load_dwordx4 31; GFX908-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} 32; GFX90A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}} 33; GCN: v_mfma_i32_16x16x16i8 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 34; GFX908-COUNT-4: v_accvgpr_read_b32 35; GFX908: global_store_dwordx4 36; GFX90A-NOT: v_accvgpr_read_b32 37; GFX90A: global_store_dwordx4 v{{[0-9]+}}, [[RES]] 38define amdgpu_kernel void @test_mfma_i32_16x16x16i8(ptr addrspace(1) %arg) #0 { 39bb: 40 %in.1 = load <4 x i32>, ptr addrspace(1) %arg 41 %mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32 1, i32 2, <4 x i32> %in.1, i32 1, i32 2, i32 3) 42 store <4 x i32> %mai.1, ptr addrspace(1) %arg 43 ret void 44} 45 46attributes #0 = { "amdgpu-flat-work-group-size"="1,256" } 47