1; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s 3; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s 4 5; ALL-LABEL: {{^}}test: 6; CO-V2: enable_sgpr_kernarg_segment_ptr = 1 7; HSA: kernarg_segment_byte_size = 8 8; HSA: kernarg_segment_alignment = 4 9 10; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa 11 12; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa 13define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 { 14 %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() 15 %header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)* 16 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10 17 %value = load i32, i32 addrspace(4)* %gep 18 store i32 %value, i32 addrspace(1)* %out 19 ret void 20} 21 22; ALL-LABEL: {{^}}test_implicit: 23; HSA: kernarg_segment_byte_size = 8 24; OS-MESA3D: kernarg_segment_byte_size = 24 25; CO-V2: kernarg_segment_alignment = 4 26 27; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15 28; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15 29define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 { 30 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 31 %header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* 32 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10 33 %value = load i32, i32 addrspace(4)* %gep 34 store i32 %value, i32 addrspace(1)* %out 35 ret void 36} 37 38; ALL-LABEL: {{^}}test_implicit_alignment: 39; HSA: kernarg_segment_byte_size = 12 40; OS-MESA3D: kernarg_segment_byte_size = 28 41; CO-V2: kernarg_segment_alignment = 4 42 43 44; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc 45; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 46; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 47; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] 48; MESA: buffer_store_dword [[V_VAL]] 49; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] 50define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 { 51 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 52 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* 53 %val = load i32, i32 addrspace(4)* %arg.ptr 54 store i32 %val, i32 addrspace(1)* %out 55 ret void 56} 57 58; ALL-LABEL: {{^}}opencl_test_implicit_alignment 59; HSA: kernarg_segment_byte_size = 64 60; OS-MESA3D: kernarg_segment_byte_size = 28 61; CO-V2: kernarg_segment_alignment = 4 62 63 64; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc 65; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 66; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 67; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] 68; MESA: buffer_store_dword [[V_VAL]] 69; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] 70define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 { 71 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 72 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* 73 %val = load i32, i32 addrspace(4)* %arg.ptr 74 store i32 %val, i32 addrspace(1)* %out 75 ret void 76} 77 78; Mesa implies 16-bytes are always allocated, hsa requires the 79; attribute for the additional space. 80; ALL-LABEL: {{^}}test_no_kernargs: 81; HSA: enable_sgpr_kernarg_segment_ptr = 0 82; HSA: kernarg_segment_byte_size = 0 83 84; OS-MESA3D: enable_sgpr_kernarg_segment_ptr = 1 85; OS-MESA3D: kernarg_segment_byte_size = 16 86; CO-V2: kernarg_segment_alignment = 4 87 88; HSA: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0{{$}} 89; HSA: s_load_dword s{{[0-9]+}}, [[NULL]], 0xa{{$}} 90define amdgpu_kernel void @test_no_kernargs() #1 { 91 %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() 92 %header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)* 93 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10 94 %value = load i32, i32 addrspace(4)* %gep 95 store volatile i32 %value, i32 addrspace(1)* undef 96 ret void 97} 98 99; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs: 100; HSA: kernarg_segment_byte_size = 48 101; OS-MESA3d: kernarg_segment_byte_size = 16 102; CO-V2: kernarg_segment_alignment = 4 103define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs() #2 { 104 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 105 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* 106 %val = load volatile i32, i32 addrspace(4)* %arg.ptr 107 store volatile i32 %val, i32 addrspace(1)* null 108 ret void 109} 110 111; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs_round_up: 112; HSA: kernarg_segment_byte_size = 40 113; OS-MESA3D: kernarg_segment_byte_size = 16 114; CO-V2: kernarg_segment_alignment = 4 115define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs_round_up() #3 { 116 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 117 %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)* 118 %val = load volatile i32, i32 addrspace(4)* %arg.ptr 119 store volatile i32 %val, i32 addrspace(1)* null 120 ret void 121} 122 123declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 124declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0 125 126attributes #0 = { nounwind readnone } 127attributes #1 = { nounwind } 128attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" } 129attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" } 130