1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V4,HSA,ALL %s 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V4,OS-MESA3D,ALL %s 3; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,ALL %s 4 5; ALL-LABEL: {{^}}test: 6; OS-MESA3D: enable_sgpr_kernarg_segment_ptr = 1 7; CO-V4: s_load_dword s{{[0-9]+}}, s[8:9], 0xa 8 9; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[4:5], 0xa 10 11; HSA: .amdhsa_kernarg_size 8 12; HSA: .amdhsa_user_sgpr_kernarg_segment_ptr 1 13define amdgpu_kernel void @test(ptr addrspace(1) %out) #1 { 14 %kernarg.segment.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 15 %gep = getelementptr i32, ptr addrspace(4) %kernarg.segment.ptr, i64 10 16 %value = load i32, ptr addrspace(4) %gep 17 store i32 %value, ptr addrspace(1) %out 18 ret void 19} 20 21; ALL-LABEL: {{^}}test_implicit: 22; OS-MESA3D: kernarg_segment_byte_size = 24 23; OS-MESA3D: kernarg_segment_alignment = 4 24 25; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15 26; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[4:5], 0x15 27; HSA: .amdhsa_kernarg_size 8 28define amdgpu_kernel void @test_implicit(ptr addrspace(1) %out) #1 { 29 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 30 %gep = getelementptr i32, ptr addrspace(4) %implicitarg.ptr, i64 10 31 %value = load i32, ptr addrspace(4) %gep 32 store i32 %value, ptr addrspace(1) %out 33 ret void 34} 35 36; ALL-LABEL: {{^}}test_implicit_alignment: 37; OS-MESA3D: kernarg_segment_byte_size = 28 38; OS-MESA3D: kernarg_segment_alignment = 4 39 40; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc 41; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 42; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 43; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] 44; MESA: buffer_store_dword [[V_VAL]] 45; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] 46 47; HSA: .amdhsa_kernarg_size 12 48define amdgpu_kernel void @test_implicit_alignment(ptr addrspace(1) %out, <2 x i8> %in) #1 { 49 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 50 %val = load i32, ptr addrspace(4) %implicitarg.ptr 51 store i32 %val, ptr addrspace(1) %out 52 ret void 53} 54 55; ALL-LABEL: {{^}}opencl_test_implicit_alignment 56; OS-MESA3D: kernarg_segment_byte_size = 28 57; OS-MESA3D: kernarg_segment_alignment = 4 58 59; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc 60; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 61; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 62; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] 63; MESA: buffer_store_dword [[V_VAL]] 64; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] 65; HSA: .amdhsa_kernarg_size 64 66define amdgpu_kernel void @opencl_test_implicit_alignment(ptr addrspace(1) %out, <2 x i8> %in) #2 { 67 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 68 %val = load i32, ptr addrspace(4) %implicitarg.ptr 69 store i32 %val, ptr addrspace(1) %out 70 ret void 71} 72 73; ALL-LABEL: {{^}}test_no_kernargs: 74; OS-MESA3D: enable_sgpr_kernarg_segment_ptr = 0 75; OS-MESA3D: kernarg_segment_byte_size = 0 76; OS-MESA3D: kernarg_segment_alignment = 4 77 78 79; HSA: .amdhsa_kernarg_size 0 80; HSA: .amdhsa_user_sgpr_kernarg_segment_ptr 0 81define amdgpu_kernel void @test_no_kernargs() #4 { 82 %kernarg.segment.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 83 %gep = getelementptr i32, ptr addrspace(4) %kernarg.segment.ptr, i64 10 84 %value = load i32, ptr addrspace(4) %gep 85 store volatile i32 %value, ptr addrspace(1) undef 86 ret void 87} 88 89; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs: 90; OS-MESA3D: kernarg_segment_byte_size = 16 91; OS-MESA3D: kernarg_segment_alignment = 4 92; HSA: .amdhsa_kernarg_size 48 93define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs() #2 { 94 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 95 %val = load volatile i32, ptr addrspace(4) %implicitarg.ptr 96 store volatile i32 %val, ptr addrspace(1) null 97 ret void 98} 99 100; ALL-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs_round_up: 101; OS-MESA3D: kernarg_segment_byte_size = 16 102; OS-MESA3D: kernarg_segment_alignment = 4 103; HSA: .amdhsa_kernarg_size 40 104define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs_round_up() #3 { 105 %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 106 %val = load volatile i32, ptr addrspace(4) %implicitarg.ptr 107 store volatile i32 %val, ptr addrspace(1) null 108 ret void 109} 110 111; ALL-LABEL: {{^}}func_kernarg_segment_ptr: 112; ALL: v_mov_b32_e32 v0, 0{{$}} 113; ALL: v_mov_b32_e32 v1, 0{{$}} 114define ptr addrspace(4) @func_kernarg_segment_ptr() { 115 %ptr = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() 116 ret ptr addrspace(4) %ptr 117} 118 119declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0 120declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0 121 122attributes #0 = { nounwind readnone } 123attributes #1 = { nounwind "amdgpu-implicitarg-num-bytes"="0" } 124attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" } 125attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" } 126attributes #4 = { nounwind "amdgpu-implicitarg-num-bytes"="0" "amdgpu-no-implicitarg-ptr" } 127 128!llvm.module.flags = !{!0} 129!0 = !{i32 1, !"amdhsa_code_object_version", i32 400} 130