1; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s 2; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -early-live-intervals < %s | FileCheck -check-prefixes=GCN %s 3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s 4 5; GCN-LABEL: {{^}}load_1d: 6; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm{{$}} 7define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, i32 %s) { 8main_body: 9 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 10 ret <4 x float> %v 11} 12 13; GCN-LABEL: {{^}}load_1d_lwe: 14; GCN: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf unorm lwe{{$}} 15define amdgpu_ps <4 x float> @load_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s) { 16main_body: 17 %v = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 2, i32 0) 18 %v.vec = extractvalue {<4 x float>, i32} %v, 0 19 %v.err = extractvalue {<4 x float>, i32} %v, 1 20 store i32 %v.err, ptr addrspace(1) %out, align 4 21 ret <4 x float> %v.vec 22} 23 24; GCN-LABEL: {{^}}load_2d: 25; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}} 26define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, i32 %s, i32 %t) { 27main_body: 28 %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) 29 ret <4 x float> %v 30} 31 32; GCN-LABEL: {{^}}load_3d: 33; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm{{$}} 34define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) { 35main_body: 36 %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0) 37 ret <4 x float> %v 38} 39 40; GCN-LABEL: {{^}}load_cube: 41; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da{{$}} 42define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice) { 43main_body: 44 %v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 45 ret <4 x float> %v 46} 47 48; GCN-LABEL: {{^}}load_cube_lwe: 49; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}} 50define amdgpu_ps <4 x float> @load_cube_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice) { 51main_body: 52 %v = call {<4 x float>,i32} @llvm.amdgcn.image.load.cube.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 2, i32 0) 53 %v.vec = extractvalue {<4 x float>, i32} %v, 0 54 %v.err = extractvalue {<4 x float>, i32} %v, 1 55 store i32 %v.err, ptr addrspace(1) %out, align 4 56 ret <4 x float> %v.vec 57} 58 59; GCN-LABEL: {{^}}load_1darray: 60; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm da{{$}} 61define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, i32 %s, i32 %slice) { 62main_body: 63 %v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 64 ret <4 x float> %v 65} 66 67; GCN-LABEL: {{^}}load_2darray: 68; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da{{$}} 69define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice) { 70main_body: 71 %v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 72 ret <4 x float> %v 73} 74 75; GCN-LABEL: {{^}}load_2darray_lwe: 76; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}} 77define amdgpu_ps <4 x float> @load_2darray_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice) { 78main_body: 79 %v = call {<4 x float>,i32} @llvm.amdgcn.image.load.2darray.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 2, i32 0) 80 %v.vec = extractvalue {<4 x float>, i32} %v, 0 81 %v.err = extractvalue {<4 x float>, i32} %v, 1 82 store i32 %v.err, ptr addrspace(1) %out, align 4 83 ret <4 x float> %v.vec 84} 85 86; GCN-LABEL: {{^}}load_2dmsaa: 87; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm{{$}} 88define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) { 89main_body: 90 %v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) 91 ret <4 x float> %v 92} 93 94; GCN-LABEL: {{^}}load_2darraymsaa: 95; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}} 96define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) { 97main_body: 98 %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) 99 ret <4 x float> %v 100} 101 102; GCN-LABEL: {{^}}load_1d_addr_align: 103; GCN: v_mov_b32_e32 [[VADDR:v[0-9]?[02468]]], v1 104; GCN: image_load v[0:3], [[VADDR]], s[0:7] dmask:0xf unorm{{$}} 105define amdgpu_ps <4 x float> @load_1d_addr_align(<8 x i32> inreg %rsrc, <2 x i32> %s) { 106main_body: 107 %s1 = extractelement <2 x i32> %s, i32 1 108 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s1, <8 x i32> %rsrc, i32 0, i32 0) 109 ret <4 x float> %v 110} 111 112; GCN-LABEL: {{^}}store_1d: 113; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm{{$}} 114define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { 115main_body: 116 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 117 ret void 118} 119 120; GCN-LABEL: {{^}}store_2d: 121; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm{{$}} 122define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) { 123main_body: 124 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) 125 ret void 126} 127 128; GCN-LABEL: {{^}}store_3d: 129; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm{{$}} 130define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %r) { 131main_body: 132 call void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0) 133 ret void 134} 135 136; GCN-LABEL: {{^}}store_cube: 137; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da{{$}} 138define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice) { 139main_body: 140 call void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 141 ret void 142} 143 144; GCN-LABEL: {{^}}store_1darray: 145; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm da{{$}} 146define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %slice) { 147main_body: 148 call void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 149 ret void 150} 151 152; GCN-LABEL: {{^}}store_2darray: 153; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da{{$}} 154define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice) { 155main_body: 156 call void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) 157 ret void 158} 159 160; GCN-LABEL: {{^}}store_2dmsaa: 161; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm{{$}} 162define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %fragid) { 163main_body: 164 call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) 165 ret void 166} 167 168; GCN-LABEL: {{^}}store_2darraymsaa: 169; GCN: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}} 170define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice, i32 %fragid) { 171main_body: 172 call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) 173 ret void 174} 175 176; GCN-LABEL: {{^}}load_1d_V1: 177; GCN: image_load v0, v0, s[0:7] dmask:0x8 unorm{{$}} 178define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, i32 %s) { 179main_body: 180 %v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 181 ret float %v 182} 183 184; GCN-LABEL: {{^}}load_1d_V2: 185; GCN: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm{{$}} 186define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, i32 %s) { 187main_body: 188 %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 9, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 189 ret <2 x float> %v 190} 191 192; GCN-LABEL: {{^}}store_1d_V1: 193; GCN: v_mov_b32_e32 [[VADDR:v[0-9]?[02468]]], v1 194; GCN: image_store v0, [[VADDR]], s[0:7] dmask:0x2 unorm{{$}} 195define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, i32 %s) { 196main_body: 197 call void @llvm.amdgcn.image.store.1d.f32.i32(float %vdata, i32 2, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 198 ret void 199} 200 201; GCN-LABEL: {{^}}store_1d_V2: 202; GCN: image_store v[0:1], v2, s[0:7] dmask:0xc unorm{{$}} 203define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, i32 %s) { 204main_body: 205 call void @llvm.amdgcn.image.store.1d.v2f32.i32(<2 x float> %vdata, i32 12, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) 206 ret void 207} 208 209; GCN-LABEL: {{^}}load_1d_glc: 210; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc{{$}} 211define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, i32 %s) { 212main_body: 213 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1) 214 ret <4 x float> %v 215} 216 217; GCN-LABEL: {{^}}load_1d_slc: 218; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc{{$}} 219define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, i32 %s) { 220main_body: 221 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2) 222 ret <4 x float> %v 223} 224 225; GCN-LABEL: {{^}}load_1d_glc_slc: 226; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc{{$}} 227define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, i32 %s) { 228main_body: 229 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3) 230 ret <4 x float> %v 231} 232 233; GCN-LABEL: {{^}}store_1d_glc: 234; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc{{$}} 235define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { 236main_body: 237 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1) 238 ret void 239} 240 241; GCN-LABEL: {{^}}store_1d_slc: 242; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc{{$}} 243define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { 244main_body: 245 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2) 246 ret void 247} 248 249; GCN-LABEL: {{^}}store_1d_glc_slc: 250; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc{{$}} 251define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { 252main_body: 253 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3) 254 ret void 255} 256 257; GCN-LABEL: {{^}}image_store_wait: 258; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf 259; SI: s_waitcnt expcnt(0) 260; GCN: image_load v[0:3], v4, s[8:15] dmask:0xf 261; GCN: s_waitcnt vmcnt(0) 262; GCN: image_store v[0:3], v4, s[16:23] dmask:0xf 263define amdgpu_ps void @image_store_wait(<8 x i32> inreg %arg, <8 x i32> inreg %arg1, <8 x i32> inreg %arg2, <4 x float> %arg3, i32 %arg4) #0 { 264main_body: 265 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %arg3, i32 15, i32 %arg4, <8 x i32> %arg, i32 0, i32 0) 266 %data = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %arg4, <8 x i32> %arg1, i32 0, i32 0) 267 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %data, i32 15, i32 %arg4, <8 x i32> %arg2, i32 0, i32 0) 268 ret void 269} 270 271; GCN-LABEL: image_load_mmo 272; GCN: image_load v1, v[{{[0-9:]+}}], s[0:7] dmask:0x1 unorm 273define amdgpu_ps float @image_load_mmo(<8 x i32> inreg %rsrc, ptr addrspace(3) %lds, <2 x i32> %c) #0 { 274 store float 0.000000e+00, ptr addrspace(3) %lds 275 %c0 = extractelement <2 x i32> %c, i32 0 276 %c1 = extractelement <2 x i32> %c, i32 1 277 %tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 %c0, i32 %c1, <8 x i32> %rsrc, i32 0, i32 0) 278 %tmp2 = getelementptr float, ptr addrspace(3) %lds, i32 4 279 store float 0.000000e+00, ptr addrspace(3) %tmp2 280 ret float %tex 281} 282 283; GCN: v_mov_b32_e32 [[VADDR:v[0-9]?[02468]]], v1 284; GCN: image_get_resinfo v[0:3], [[VADDR]], s[0:7] dmask:0xf unorm 285define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i32> %s) { 286main_body: 287 %s1 = extractelement <2 x i32> %s, i32 1 288 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 15, i32 %s1, <8 x i32> %rsrc, i32 0, i32 0) 289 ret <4 x float> %v 290} 291 292declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #1 293declare {float,i32} @llvm.amdgcn.image.load.1d.f32i32.i32(i32, i32, <8 x i32>, i32, i32) #1 294declare {<2 x float>,i32} @llvm.amdgcn.image.load.1d.v2f32i32.i32(i32, i32, <8 x i32>, i32, i32) #1 295declare {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32, i32, <8 x i32>, i32, i32) #1 296declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1 297declare {<4 x float>,i32} @llvm.amdgcn.image.load.2d.v4f32i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1 298declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 299declare {<4 x float>,i32} @llvm.amdgcn.image.load.3d.v4f32i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 300declare <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 301declare {<4 x float>,i32} @llvm.amdgcn.image.load.cube.v4f32i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 302declare <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1 303declare {<4 x float>,i32} @llvm.amdgcn.image.load.1darray.v4f32i32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1 304declare <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 305declare {<4 x float>,i32} @llvm.amdgcn.image.load.2darray.v4f32i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 306declare <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 307declare {<4 x float>,i32} @llvm.amdgcn.image.load.2dmsaa.v4f32i32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1 308declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #1 309declare {<4 x float>,i32} @llvm.amdgcn.image.load.2darraymsaa.v4f32i32.i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #1 310 311declare void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float>, i32, i32, <8 x i32>, i32, i32) #0 312declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32, i32, i32, <8 x i32>, i32, i32) #0 313declare void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #0 314declare void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #0 315declare void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float>, i32, i32, i32, <8 x i32>, i32, i32) #0 316declare void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #0 317declare void @llvm.amdgcn.image.store.2dmsaa.v4f32.i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #0 318declare void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #0 319 320declare float @llvm.amdgcn.image.load.1d.f32.i32(i32, i32, <8 x i32>, i32, i32) #1 321declare float @llvm.amdgcn.image.load.2d.f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1 322declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32, i32, <8 x i32>, i32, i32) #1 323declare void @llvm.amdgcn.image.store.1d.f32.i32(float, i32, i32, <8 x i32>, i32, i32) #0 324declare void @llvm.amdgcn.image.store.1d.v2f32.i32(<2 x float>, i32, i32, <8 x i32>, i32, i32) #0 325 326declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2 327 328attributes #0 = { nounwind } 329attributes #1 = { nounwind readonly } 330attributes #2 = { nounwind readnone } 331