xref: /llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll (revision 6548b6354d1d990e1c98736f5e7c3de876bedc8e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11
3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11
4
5declare half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %a, <2 x half> %b, half %c)
6
7define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f16_f16(
8; GFX11-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
9; GFX11:       ; %bb.0: ; %entry
10; GFX11-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
11; GFX11-NEXT:    v_mov_b32_e32 v0, 0
12; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
13; GFX11-NEXT:    global_load_u16 v1, v0, s[6:7]
14; GFX11-NEXT:    s_load_b32 s2, s[2:3], 0x0
15; GFX11-NEXT:    s_load_b32 s3, s[4:5], 0x0
16; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
17; GFX11-NEXT:    v_dot2_f16_f16 v1, s2, s3, v1
18; GFX11-NEXT:    global_store_b16 v0, v1, s[0:1]
19; GFX11-NEXT:    s_endpgm
20    ptr addrspace(1) %r,
21    ptr addrspace(1) %a,
22    ptr addrspace(1) %b,
23    ptr addrspace(1) %c) {
24entry:
25  %a.val = load <2 x half>, ptr addrspace(1) %a
26  %b.val = load <2 x half>, ptr addrspace(1) %b
27  %c.val = load half, ptr addrspace(1) %c
28  %r.val = call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %a.val, <2 x half> %b.val, half %c.val)
29  store half %r.val, ptr addrspace(1) %r
30  ret void
31}
32
33define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f16_f16_dpp(
34; SDAG-GFX11-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
35; SDAG-GFX11:       ; %bb.0: ; %entry
36; SDAG-GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
37; SDAG-GFX11-NEXT:    s_waitcnt lgkmcnt(0)
38; SDAG-GFX11-NEXT:    scratch_load_b32 v0, off, s2
39; SDAG-GFX11-NEXT:    scratch_load_u16 v1, off, s3
40; SDAG-GFX11-NEXT:    scratch_load_b32 v2, off, s1
41; SDAG-GFX11-NEXT:    s_waitcnt vmcnt(0)
42; SDAG-GFX11-NEXT:    v_dot2_f16_f16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
43; SDAG-GFX11-NEXT:    scratch_store_b16 off, v0, s0
44; SDAG-GFX11-NEXT:    s_endpgm
45;
46; GISEL-GFX11-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
47; GISEL-GFX11:       ; %bb.0: ; %entry
48; GISEL-GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
49; GISEL-GFX11-NEXT:    s_waitcnt lgkmcnt(0)
50; GISEL-GFX11-NEXT:    scratch_load_b32 v0, off, s1
51; GISEL-GFX11-NEXT:    scratch_load_b32 v1, off, s2
52; GISEL-GFX11-NEXT:    scratch_load_u16 v2, off, s3
53; GISEL-GFX11-NEXT:    s_waitcnt vmcnt(0)
54; GISEL-GFX11-NEXT:    v_dot2_f16_f16_e64_dpp v0, v0, v1, v2 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
55; GISEL-GFX11-NEXT:    scratch_store_b16 off, v0, s0
56; GISEL-GFX11-NEXT:    s_endpgm
57    ptr addrspace(5) %r,
58    ptr addrspace(5) %a,
59    ptr addrspace(5) %b,
60    ptr addrspace(5) %c) {
61entry:
62  %a.val = load <2 x half>, ptr addrspace(5) %a
63  %b.val = load <2 x half>, ptr addrspace(5) %b
64  %c.val = load half, ptr addrspace(5) %c
65  %a.val.i32 = bitcast <2 x half> %a.val to i32
66  %dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %a.val.i32, i32 %a.val.i32, i32 1, i32 15, i32 15, i1 1)
67  %a.val.dpp.v2half = bitcast i32 %dpp to <2 x half>
68  %r.val = call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %a.val.dpp.v2half, <2 x half> %b.val, half %c.val)
69  store half %r.val, ptr addrspace(5) %r
70  ret void
71}
72
73declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
74