1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11 3; FIXME: GlobalIsel doesn't support BF16 for now. 4; xUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11 5 6declare bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a, <2 x bfloat> %b, bfloat %c) 7 8define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16( 9; GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16: 10; GFX11: ; %bb.0: ; %entry 11; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 12; GFX11-NEXT: v_mov_b32_e32 v0, 0 13; GFX11-NEXT: s_waitcnt lgkmcnt(0) 14; GFX11-NEXT: global_load_u16 v1, v0, s[6:7] 15; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0 16; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x0 17; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 18; GFX11-NEXT: v_dot2_bf16_bf16 v1, s2, s3, v1 19; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] 20; GFX11-NEXT: s_endpgm 21 ptr addrspace(1) %r, 22 ptr addrspace(1) %a, 23 ptr addrspace(1) %b, 24 ptr addrspace(1) %c) { 25entry: 26 %a.val = load <2 x bfloat>, ptr addrspace(1) %a 27 %b.val = load <2 x bfloat>, ptr addrspace(1) %b 28 %c.val = load bfloat, ptr addrspace(1) %c 29 %r.val = call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a.val, <2 x bfloat> %b.val, bfloat %c.val) 30 store bfloat %r.val, ptr addrspace(1) %r 31 ret void 32} 33 34define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16_dpp( 35; GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp: 36; GFX11: ; %bb.0: ; %entry 37; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 38; GFX11-NEXT: s_waitcnt lgkmcnt(0) 39; GFX11-NEXT: scratch_load_b32 v0, off, s2 40; GFX11-NEXT: scratch_load_u16 v1, off, s3 41; GFX11-NEXT: scratch_load_b32 v2, off, s1 42; GFX11-NEXT: s_waitcnt vmcnt(0) 43; GFX11-NEXT: v_dot2_bf16_bf16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1 44; GFX11-NEXT: scratch_store_b16 off, v0, s0 45; GFX11-NEXT: s_endpgm 46 ptr addrspace(5) %r, 47 ptr addrspace(5) %a, 48 ptr addrspace(5) %b, 49 ptr addrspace(5) %c) { 50entry: 51 %a.val = load <2 x bfloat>, ptr addrspace(5) %a 52 %b.val = load <2 x bfloat>, ptr addrspace(5) %b 53 %c.val = load bfloat, ptr addrspace(5) %c 54 %a.val.i32 = bitcast <2 x bfloat> %a.val to i32 55 %dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %a.val.i32, i32 %a.val.i32, i32 1, i32 15, i32 15, i1 1) 56 %a.val.dpp.v2bfloat = bitcast i32 %dpp to <2 x bfloat> 57 %r.val = call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a.val.dpp.v2bfloat, <2 x bfloat> %b.val, bfloat %c.val) 58 store bfloat %r.val, ptr addrspace(5) %r 59 ret void 60} 61 62; Make sure we do not violate constant bus restriction with 3 scalar inputs and simingly inlinable literal. 63 64define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis( 65; GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis: 66; GFX11: ; %bb.0: ; %entry 67; GFX11-NEXT: v_mov_b32_e32 v2, s1 68; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 69; GFX11-NEXT: v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2 70; GFX11-NEXT: global_store_b16 v[0:1], v2, off 71; GFX11-NEXT: s_endpgm 72 ptr addrspace(1) %r, 73 <2 x bfloat> inreg %a, 74 bfloat inreg %c) { 75entry: 76 %r.val = call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a, <2 x bfloat> <bfloat 1.0, bfloat 1.0>, bfloat %c) 77 store bfloat %r.val, ptr addrspace(1) %r 78 ret void 79} 80 81declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) 82;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: 83; SDAG-GFX11: {{.*}} 84