1; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 2; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 6; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 7; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 8; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 9 10; FUNC-LABEL: {{^}}ds_ordered_swap: 11; GCN: s_mov_b32 m0, s0 12; VIGFX9-NEXT: s_nop 0 13; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v0 offset:4868 gds 14; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 15define amdgpu_cs float @ds_ordered_swap(ptr addrspace(2) inreg %gds, i32 %value) { 16 %val = call i32@llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 %value, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 17 %r = bitcast i32 %val to float 18 ret float %r 19} 20 21; FUNC-LABEL: {{^}}ds_ordered_swap_conditional: 22; GCN: v_cmp_ne_u32_e32 vcc, 0, v[[VALUE:[0-9]+]] 23; GCN: s_and_saveexec_b64 s[[SAVED:\[[0-9]+:[0-9]+\]]], vcc 24; // We have to use s_cbranch, because ds_ordered_count has side effects with EXEC=0 25; GCN: s_cbranch_execz [[BB:.LBB._.]] 26; GCN: s_mov_b32 m0, s0 27; VIGFX9-NEXT: s_nop 0 28; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[VALUE]] offset:4868 gds 29; GCN-NEXT: [[BB]]: 30; // Wait for expcnt(0) before modifying EXEC 31; GCN-NEXT: s_waitcnt expcnt(0) 32; GCN-NEXT: s_or_b64 exec, exec, s[[SAVED]] 33; GCN-NEXT: s_waitcnt lgkmcnt(0) 34define amdgpu_cs float @ds_ordered_swap_conditional(ptr addrspace(2) inreg %gds, i32 %value) { 35entry: 36 %c = icmp ne i32 %value, 0 37 br i1 %c, label %if-true, label %endif 38 39if-true: 40 %val = call i32@llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) %gds, i32 %value, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 41 br label %endif 42 43endif: 44 %v = phi i32 [ %val, %if-true ], [ undef, %entry ] 45 %r = bitcast i32 %v to float 46 ret float %r 47} 48 49declare i32 @llvm.amdgcn.ds.ordered.swap(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1) 50