1; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 2; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 6; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 7; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 8; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s 9 10; FUNC-LABEL: {{^}}ds_ordered_add: 11; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 12; GCN-DAG: s_mov_b32 m0, 13; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 14define amdgpu_kernel void @ds_ordered_add(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) { 15 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 16 store i32 %val, ptr addrspace(1) %out 17 ret void 18} 19 20; Below are various modifications of input operands and shader types. 21 22; FUNC-LABEL: {{^}}ds_ordered_add_counter2: 23; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 24; GCN-DAG: s_mov_b32 m0, 25; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:776 gds 26define amdgpu_kernel void @ds_ordered_add_counter2(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) { 27 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 2, i1 true, i1 true) 28 store i32 %val, ptr addrspace(1) %out 29 ret void 30} 31 32; FUNC-LABEL: {{^}}ds_ordered_add_nodone: 33; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 34; GCN-DAG: s_mov_b32 m0, 35; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:260 gds 36define amdgpu_kernel void @ds_ordered_add_nodone(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) { 37 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 false) 38 store i32 %val, ptr addrspace(1) %out 39 ret void 40} 41 42; FUNC-LABEL: {{^}}ds_ordered_add_norelease: 43; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 44; GCN-DAG: s_mov_b32 m0, 45; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:4 gds 46define amdgpu_kernel void @ds_ordered_add_norelease(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) { 47 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 false, i1 false) 48 store i32 %val, ptr addrspace(1) %out 49 ret void 50} 51 52; FUNC-LABEL: {{^}}ds_ordered_add_cs: 53; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 54; GCN: s_mov_b32 m0, s0 55; VIGFX9-NEXT: s_nop 0 56; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 57; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 58define amdgpu_cs float @ds_ordered_add_cs(ptr addrspace(2) inreg %gds) { 59 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 60 %r = bitcast i32 %val to float 61 ret float %r 62} 63 64; FUNC-LABEL: {{^}}ds_ordered_add_default_cc: 65; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 66; GCN: s_mov_b32 m0, 0{{$}} 67; VIGFX9-NEXT: s_nop 0 68; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 69; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 70define float @ds_ordered_add_default_cc() { 71 %val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 72 %r = bitcast i32 %val to float 73 ret float %r 74} 75 76; FUNC-LABEL: {{^}}ds_ordered_add_fastcc: 77; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 78; GCN: s_mov_b32 m0, 0{{$}} 79; VIGFX9-NEXT: s_nop 0 80; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 81; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 82define fastcc float @ds_ordered_add_fastcc() { 83 %val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 84 %r = bitcast i32 %val to float 85 ret float %r 86} 87 88; FUNC-LABEL: {{^}}ds_ordered_add_func: 89; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 90; GCN: s_mov_b32 m0, 0{{$}} 91; VIGFX9-NEXT: s_nop 0 92; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 93; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 94define float @ds_ordered_add_func() { 95 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 96 %r = bitcast i32 %val to float 97 ret float %r 98} 99 100; FUNC-LABEL: {{^}}ds_ordered_add_ps: 101; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 102; GCN: s_mov_b32 m0, s0 103; VIGFX9-NEXT: s_nop 0 104; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:1796 gds 105; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 106define amdgpu_ps float @ds_ordered_add_ps(ptr addrspace(2) inreg %gds) { 107 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 108 %r = bitcast i32 %val to float 109 ret float %r 110} 111 112; FUNC-LABEL: {{^}}ds_ordered_add_vs: 113; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 114; GCN: s_mov_b32 m0, s0 115; VIGFX9-NEXT: s_nop 0 116; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:2820 gds 117; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 118define amdgpu_vs float @ds_ordered_add_vs(ptr addrspace(2) inreg %gds) { 119 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 120 %r = bitcast i32 %val to float 121 ret float %r 122} 123 124; FUNC-LABEL: {{^}}ds_ordered_add_gs: 125; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 126; GCN: s_mov_b32 m0, s0 127; VIGFX9-NEXT: s_nop 0 128; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:3844 gds 129; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 130define amdgpu_gs float @ds_ordered_add_gs(ptr addrspace(2) inreg %gds) { 131 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true) 132 %r = bitcast i32 %val to float 133 ret float %r 134} 135 136declare i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1) 137