1; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s 3; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s 4 5; GFX12-ERR: LLVM ERROR: Cannot select: {{.*}} = DS_ORDERED_COUNT 6 7; FUNC-LABEL: {{^}}ds_ordered_add: 8; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 9; GCN-DAG: s_mov_b32 m0, 10; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 11define amdgpu_kernel void @ds_ordered_add(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) { 12 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true) 13 store i32 %val, ptr addrspace(1) %out 14 ret void 15} 16 17; FUNC-LABEL: {{^}}ds_ordered_add_cs: 18; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 19; GCN: s_mov_b32 m0, s0 20; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 21; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 22define amdgpu_cs float @ds_ordered_add_cs(ptr addrspace(2) inreg %gds) { 23 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true) 24 %r = bitcast i32 %val to float 25 ret float %r 26} 27 28; FUNC-LABEL: {{^}}ds_ordered_add_ps: 29; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 30; GCN: s_mov_b32 m0, s0 31; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 32; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 33define amdgpu_ps float @ds_ordered_add_ps(ptr addrspace(2) inreg %gds) { 34 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true) 35 %r = bitcast i32 %val to float 36 ret float %r 37} 38 39; FUNC-LABEL: {{^}}ds_ordered_add_vs: 40; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 41; GCN: s_mov_b32 m0, s0 42; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 43; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 44define amdgpu_vs float @ds_ordered_add_vs(ptr addrspace(2) inreg %gds) { 45 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true) 46 %r = bitcast i32 %val to float 47 ret float %r 48} 49 50; FUNC-LABEL: {{^}}ds_ordered_add_gs: 51; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31 52; GCN: s_mov_b32 m0, s0 53; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds 54; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0) 55define amdgpu_gs float @ds_ordered_add_gs(ptr addrspace(2) inreg %gds) { 56 %val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 16777217, i1 true, i1 true) 57 %r = bitcast i32 %val to float 58 ret float %r 59} 60 61declare i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1) 62