1; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s 2; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s 3; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s 4; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s 5; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s 6; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s 7; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP %s 8; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP %s 9; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP %s 10; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP %s 11; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP %s 12; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP %s 13 14; GCN-LABEL: {{^}}gws_sema_br_offset0: 15; NOLOOP-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]] 16; NOLOOP-DAG: s_mov_b32 m0, 0{{$}} 17; NOLOOP: v_mov_b32_e32 v0, [[BAR_NUM]] 18; NOLOOP: ds_gws_sema_br v0 gds{{$}} 19 20; LOOP: s_mov_b32 m0, 0{{$}} 21; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]: 22; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0 23; LOOP-NEXT: ds_gws_sema_br v0 gds 24; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 25; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1) 26; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0 27; LOOP-NEXT: s_cbranch_scc1 [[LOOP]] 28define amdgpu_kernel void @gws_sema_br_offset0(i32 %val) #0 { 29 call void @llvm.amdgcn.ds.gws.sema.br(i32 %val, i32 0) 30 ret void 31} 32 33declare void @llvm.amdgcn.ds.gws.sema.br(i32, i32) #0 34 35attributes #0 = { convergent inaccessiblememonly nounwind } 36