1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s
3
4# Make sure coalescing doesn't produce "no live segment at def" when
5# there is a live out implicit_def with subranges.
6
7# %1 will be coalesced into %0. %0 is a cross block implicit_def that
8# cannot be deleted. The def of %0 in %bb.2 is a live out subregister
9# def of the same register. We need to ensure that the resulting
10# subrange for %0.sub0 includes the def in %bb.1
11
12---
13name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def
14tracksRegLiveness: true
15body:             |
16  ; CHECK-LABEL: name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def
17  ; CHECK: bb.0:
18  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
19  ; CHECK-NEXT: {{  $}}
20  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit undef $scc
21  ; CHECK-NEXT: {{  $}}
22  ; CHECK-NEXT: bb.1:
23  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
24  ; CHECK-NEXT: {{  $}}
25  ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
26  ; CHECK-NEXT:   S_BRANCH %bb.3
27  ; CHECK-NEXT: {{  $}}
28  ; CHECK-NEXT: bb.2:
29  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
30  ; CHECK-NEXT: {{  $}}
31  ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF
32  ; CHECK-NEXT: {{  $}}
33  ; CHECK-NEXT: bb.3:
34  ; CHECK-NEXT:   S_NOP 0, implicit [[S_MOV_B32_]]
35  ; CHECK-NEXT:   S_NOP 0, implicit [[S_MOV_B32_]].sub0
36  ; CHECK-NEXT:   S_ENDPGM 0
37  bb.0:
38    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
39
40  bb.1:
41    %0:sgpr_128 = IMPLICIT_DEF
42    %1:sgpr_32 = S_MOV_B32 0
43    S_BRANCH %bb.3
44
45  bb.2:
46    undef %0.sub0:sgpr_128 = IMPLICIT_DEF
47    %1:sgpr_32 = COPY %0.sub0
48
49  bb.3:
50    S_NOP 0, implicit %0
51    S_NOP 0, implicit %1
52    S_ENDPGM 0
53
54...
55
56
57# Redef of sub0 is a meaningful value.
58---
59name: liveout_implicit_def_redefine_sub0_undef_other
60tracksRegLiveness: true
61body:             |
62  ; CHECK-LABEL: name: liveout_implicit_def_redefine_sub0_undef_other
63  ; CHECK: bb.0:
64  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
65  ; CHECK-NEXT: {{  $}}
66  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit undef $scc
67  ; CHECK-NEXT: {{  $}}
68  ; CHECK-NEXT: bb.1:
69  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
70  ; CHECK-NEXT: {{  $}}
71  ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0
72  ; CHECK-NEXT:   S_BRANCH %bb.3
73  ; CHECK-NEXT: {{  $}}
74  ; CHECK-NEXT: bb.2:
75  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
76  ; CHECK-NEXT: {{  $}}
77  ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 9
78  ; CHECK-NEXT: {{  $}}
79  ; CHECK-NEXT: bb.3:
80  ; CHECK-NEXT:   S_NOP 0, implicit [[S_MOV_B32_]]
81  ; CHECK-NEXT:   S_NOP 0, implicit [[S_MOV_B32_]].sub0
82  ; CHECK-NEXT:   S_ENDPGM 0
83  bb.0:
84    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
85
86  bb.1:
87    %0:sgpr_128 = IMPLICIT_DEF
88    %1:sgpr_32 = S_MOV_B32 0
89    S_BRANCH %bb.3
90
91  bb.2:
92    undef %0.sub0:sgpr_128 = S_MOV_B32 9
93    %1:sgpr_32 = COPY %0.sub0
94
95  bb.3:
96    S_NOP 0, implicit %0
97    S_NOP 0, implicit %1
98    S_ENDPGM 0
99
100...
101
102# The initial def of the register doesn't doesn't cover the redefined
103# lanes. This had no error but was useful to compare against the
104# failing cases.
105---
106name: only_redefine_undefined_lanes
107tracksRegLiveness: true
108body:             |
109  ; CHECK-LABEL: name: only_redefine_undefined_lanes
110  ; CHECK: bb.0:
111  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
112  ; CHECK-NEXT: {{  $}}
113  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.2, implicit undef $scc
114  ; CHECK-NEXT: {{  $}}
115  ; CHECK-NEXT: bb.1:
116  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
117  ; CHECK-NEXT: {{  $}}
118  ; CHECK-NEXT:   S_NOP 0, implicit-def undef %0.sub1_sub2_sub3
119  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
120  ; CHECK-NEXT:   S_BRANCH %bb.3
121  ; CHECK-NEXT: {{  $}}
122  ; CHECK-NEXT: bb.2:
123  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
124  ; CHECK-NEXT: {{  $}}
125  ; CHECK-NEXT:   undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec
126  ; CHECK-NEXT: {{  $}}
127  ; CHECK-NEXT: bb.3:
128  ; CHECK-NEXT:   S_NOP 0, implicit [[V_MOV_B32_e32_]]
129  ; CHECK-NEXT:   S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0
130  ; CHECK-NEXT:   S_ENDPGM 0
131  bb.0:
132    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
133
134  bb.1:
135    S_NOP 0, implicit-def undef %0.sub1_sub2_sub3:vreg_128
136    %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
137    S_BRANCH %bb.3
138
139  bb.2:
140    undef %0.sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec
141    %1:vgpr_32 = COPY %0.sub0
142
143  bb.3:
144    S_NOP 0, implicit %0
145    S_NOP 0, implicit %1
146    S_ENDPGM 0
147
148...
149