1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-machinelicm -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s 3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-machinelicm -o - %s | FileCheck -check-prefix=GCN %s 4 5--- 6name: hoist_move 7tracksRegLiveness: true 8body: | 9 ; GCN-LABEL: name: hoist_move 10 ; GCN: bb.0: 11 ; GCN-NEXT: successors: %bb.1(0x80000000) 12 ; GCN-NEXT: {{ $}} 13 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec 14 ; GCN-NEXT: S_BRANCH %bb.1 15 ; GCN-NEXT: {{ $}} 16 ; GCN-NEXT: bb.1: 17 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 18 ; GCN-NEXT: {{ $}} 19 ; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc 20 ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec 21 ; GCN-NEXT: S_BRANCH %bb.2 22 ; GCN-NEXT: {{ $}} 23 ; GCN-NEXT: bb.2: 24 ; GCN-NEXT: S_ENDPGM 0 25 bb.0: 26 S_BRANCH %bb.1 27 28 bb.1: 29 %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec 30 $exec = S_OR_B64 $exec, 1, implicit-def $scc 31 S_CBRANCH_EXECNZ %bb.1, implicit $exec 32 S_BRANCH %bb.2 33 34 bb.2: 35 S_ENDPGM 0 36... 37--- 38name: no_hoist_cmp 39tracksRegLiveness: true 40body: | 41 ; GCN-LABEL: name: no_hoist_cmp 42 ; GCN: bb.0: 43 ; GCN-NEXT: successors: %bb.1(0x80000000) 44 ; GCN-NEXT: {{ $}} 45 ; GCN-NEXT: S_BRANCH %bb.1 46 ; GCN-NEXT: {{ $}} 47 ; GCN-NEXT: bb.1: 48 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 49 ; GCN-NEXT: {{ $}} 50 ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec 51 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[V_CMP_EQ_U32_e64_]], implicit-def $scc 52 ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec 53 ; GCN-NEXT: S_BRANCH %bb.2 54 ; GCN-NEXT: {{ $}} 55 ; GCN-NEXT: bb.2: 56 ; GCN-NEXT: S_ENDPGM 0 57 bb.0: 58 S_BRANCH %bb.1 59 60 bb.1: 61 %0:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec 62 $exec = S_OR_B64 $exec, %0:sreg_64, implicit-def $scc 63 S_CBRANCH_EXECNZ %bb.1, implicit $exec 64 S_BRANCH %bb.2 65 66 bb.2: 67 S_ENDPGM 0 68... 69--- 70name: allowable_hoist_cmp 71tracksRegLiveness: true 72body: | 73 ; GCN-LABEL: name: allowable_hoist_cmp 74 ; GCN: bb.0: 75 ; GCN-NEXT: successors: %bb.1(0x80000000) 76 ; GCN-NEXT: {{ $}} 77 ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec 78 ; GCN-NEXT: S_BRANCH %bb.1 79 ; GCN-NEXT: {{ $}} 80 ; GCN-NEXT: bb.1: 81 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 82 ; GCN-NEXT: {{ $}} 83 ; GCN-NEXT: $exec = S_AND_B64 $exec, [[V_CMP_EQ_U32_e64_]], implicit-def $scc 84 ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec 85 ; GCN-NEXT: S_BRANCH %bb.2 86 ; GCN-NEXT: {{ $}} 87 ; GCN-NEXT: bb.2: 88 ; GCN-NEXT: S_ENDPGM 0 89 bb.0: 90 S_BRANCH %bb.1 91 92 bb.1: 93 %0:sreg_64 = V_CMP_EQ_U32_e64 1, 2, implicit $exec 94 $exec = S_AND_B64 $exec, %0:sreg_64, implicit-def $scc 95 S_CBRANCH_EXECNZ %bb.1, implicit $exec 96 S_BRANCH %bb.2 97 98 bb.2: 99 S_ENDPGM 0 100... 101--- 102name: no_hoist_readfirstlane 103tracksRegLiveness: true 104body: | 105 ; GCN-LABEL: name: no_hoist_readfirstlane 106 ; GCN: bb.0: 107 ; GCN-NEXT: successors: %bb.1(0x80000000) 108 ; GCN-NEXT: {{ $}} 109 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF 110 ; GCN-NEXT: S_BRANCH %bb.1 111 ; GCN-NEXT: {{ $}} 112 ; GCN-NEXT: bb.1: 113 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) 114 ; GCN-NEXT: {{ $}} 115 ; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[DEF]], implicit $exec 116 ; GCN-NEXT: $exec = S_OR_B64 $exec, 1, implicit-def $scc 117 ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec 118 ; GCN-NEXT: S_BRANCH %bb.2 119 ; GCN-NEXT: {{ $}} 120 ; GCN-NEXT: bb.2: 121 ; GCN-NEXT: S_ENDPGM 0 122 bb.0: 123 %0:vgpr_32 = IMPLICIT_DEF 124 S_BRANCH %bb.1 125 126 bb.1: 127 %1:sgpr_32 = V_READFIRSTLANE_B32 %0:vgpr_32, implicit $exec 128 $exec = S_OR_B64 $exec, 1, implicit-def $scc 129 S_CBRANCH_EXECNZ %bb.1, implicit $exec 130 S_BRANCH %bb.2 131 132 bb.2: 133 S_ENDPGM 0 134... 135