xref: /llvm-project/llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll (revision a82032918cd445e5750e171f57d4f3d7096c021a)
1; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH128K %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH128K %s
3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH256K %s
4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH128K %s
5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH256K %s
6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH1024K %s
7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH2048K %s
8
9; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo16:
10; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
11; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xfffc, [[FI]]
12; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
13define amdgpu_kernel void @scratch_buffer_known_high_masklo16() {
14  %alloca = alloca i32, align 4, addrspace(5)
15  store volatile i32 15, ptr addrspace(5) %alloca
16  %toint = ptrtoint ptr addrspace(5) %alloca to i32
17  %masked = and i32 %toint, 65535
18  store volatile i32 %masked, ptr addrspace(1) undef
19  ret void
20}
21
22; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo17:
23; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
24; SCRATCH128K-NOT: v_and_b32
25; SCRATCH256K: v_and_b32_e32 v{{[0-9]+}}, 0x1fffc, [[FI]]
26; SCRATCH1024K: v_and_b32_e32 v{{[0-9]+}}, 0x1fffc, [[FI]]
27; SCRATCH2048K: v_and_b32_e32 v{{[0-9]+}}, 0x1fffc, [[FI]]
28; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
29define amdgpu_kernel void @scratch_buffer_known_high_masklo17() {
30  %alloca = alloca i32, align 4, addrspace(5)
31  store volatile i32 15, ptr addrspace(5) %alloca
32  %toint = ptrtoint ptr addrspace(5) %alloca to i32
33  %masked = and i32 %toint, 131071
34  store volatile i32 %masked, ptr addrspace(1) undef
35  ret void
36}
37
38; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo18:
39; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
40; SCRATCH128K-NOT: v_and_b32
41; SCRATCH256K-NOT: v_and_b32
42; SCRATCH1024K: v_and_b32_e32 v{{[0-9]+}}, 0x3fffc, [[FI]]
43; SCRATCH2048K: v_and_b32_e32 v{{[0-9]+}}, 0x3fffc, [[FI]]
44; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
45define amdgpu_kernel void @scratch_buffer_known_high_masklo18() {
46  %alloca = alloca i32, align 4, addrspace(5)
47  store volatile i32 15, ptr addrspace(5) %alloca
48  %toint = ptrtoint ptr addrspace(5) %alloca to i32
49  %masked = and i32 %toint, 262143
50  store volatile i32 %masked, ptr addrspace(1) undef
51  ret void
52}
53
54; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo20:
55; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
56; SCRATCH128K-NOT: v_and_b32
57; SCRATCH256K-NOT: v_and_b32
58; SCRATCH1024K-NOT: v_and_b32
59; SCRATCH2048K: v_and_b32_e32 v{{[0-9]+}}, 0xffffc, [[FI]]
60; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
61define amdgpu_kernel void @scratch_buffer_known_high_masklo20() {
62  %alloca = alloca i32, align 4, addrspace(5)
63  store volatile i32 15, ptr addrspace(5) %alloca
64  %toint = ptrtoint ptr addrspace(5) %alloca to i32
65  %masked = and i32 %toint, 1048575
66  store volatile i32 %masked, ptr addrspace(1) undef
67  ret void
68}
69
70; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo21:
71; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
72; GCN-NOT: v_and_b32
73; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
74define amdgpu_kernel void @scratch_buffer_known_high_masklo21() {
75  %alloca = alloca i32, align 4, addrspace(5)
76  store volatile i32 15, ptr addrspace(5) %alloca
77  %toint = ptrtoint ptr addrspace(5) %alloca to i32
78  %masked = and i32 %toint, 2097151
79  store volatile i32 %masked, ptr addrspace(1) undef
80  ret void
81}
82