xref: /llvm-project/llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll (revision b1bcb7ca460fcd317bbc8309e14c8761bf8394e0)
1; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=amdgpu-attributor -o %t.gfx7.bc %s
2; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -passes=amdgpu-attributor -o %t.gfx8.bc %s
3; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-attributor -o %t.gfx9.bc %s
4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj < %t.gfx7.bc | llvm-readelf --notes - | FileCheck --check-prefix=CHECK  %s
5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj < %t.gfx8.bc | llvm-readelf --notes - | FileCheck --check-prefix=CHECK  %s
6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %t.gfx9.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,GFX9  %s
7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %t.gfx7.bc | FileCheck --check-prefix=CHECK %s
8; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %t.gfx8.bc | FileCheck --check-prefix=CHECK %s
9; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %t.gfx9.bc | FileCheck --check-prefixes=CHECK,GFX9 %s
10
11
12; On gfx8, the queue ptr is required for this addrspacecast.
13; CHECK: - .args:
14; PRE-GFX9:		hidden_queue_ptr
15; GFX9-NOT:		hidden_queue_ptr
16; CHECK-LABEL:		.name:           addrspacecast_requires_queue_ptr
17define amdgpu_kernel void @addrspacecast_requires_queue_ptr(ptr addrspace(5) %ptr.private, ptr addrspace(3) %ptr.local) {
18  %flat.private = addrspacecast ptr addrspace(5) %ptr.private to ptr
19  %flat.local = addrspacecast ptr addrspace(3) %ptr.local to ptr
20  store volatile i32 1, ptr %flat.private
21  store volatile i32 2, ptr %flat.local
22  ret void
23}
24
25; CHECK: - .args:
26; PRE-GFX9:		hidden_shared_base
27; GFX9-NOT:		hidden_shared_base
28; CHECK-LABEL:		.name:          is_shared_requires_queue_ptr
29define amdgpu_kernel void @is_shared_requires_queue_ptr(ptr %ptr) {
30  %is.shared = call i1 @llvm.amdgcn.is.shared(ptr %ptr)
31  %zext = zext i1 %is.shared to i32
32  store volatile i32 %zext, ptr addrspace(1) undef
33  ret void
34}
35
36; CHECK: - .args:
37; PRE-GFX9:		hidden_private_base
38; GFX9-NOT:		hidden_private_base
39; CHECK-LABEL:		.name:           is_private_requires_queue_ptr
40define amdgpu_kernel void @is_private_requires_queue_ptr(ptr %ptr) {
41  %is.private = call i1 @llvm.amdgcn.is.private(ptr %ptr)
42  %zext = zext i1 %is.private to i32
43  store volatile i32 %zext, ptr addrspace(1) undef
44  ret void
45}
46
47; CHECK: - .args:
48
49; PRE-GFX9:		hidden_queue_ptr
50; GFX9-NOT:		hidden_queue_ptr
51; CHECK-LABEL:		.name:           trap_requires_queue_ptr
52define amdgpu_kernel void @trap_requires_queue_ptr() {
53  call void @llvm.trap()
54  unreachable
55}
56
57; CHECK: - .args:
58; CHECK:		hidden_queue_ptr
59; CHECK-LABEL:		.name:           amdgcn_queue_ptr_requires_queue_ptr
60define amdgpu_kernel void @amdgcn_queue_ptr_requires_queue_ptr(ptr addrspace(1) %ptr)  {
61  %queue.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
62  %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
63  %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
64  %dispatch.id = call i64 @llvm.amdgcn.dispatch.id()
65  %queue.load = load volatile i8, ptr addrspace(4) %queue.ptr
66  %implicitarg.load = load volatile i8, ptr addrspace(4) %implicitarg.ptr
67  %dispatch.load = load volatile i8, ptr addrspace(4) %dispatch.ptr
68  store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
69  ret void
70}
71
72
73declare noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr()
74declare noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
75declare i64 @llvm.amdgcn.dispatch.id()
76declare noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
77declare i1 @llvm.amdgcn.is.shared(ptr)
78declare i1 @llvm.amdgcn.is.private(ptr)
79declare void @llvm.trap()
80declare void @llvm.debugtrap()
81
82!llvm.module.flags = !{!0}
83!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
84