1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck --check-prefix=GCN %s 3 4; -------------------------------------------------------------------------------- 5; amdgcn atomic csub 6; -------------------------------------------------------------------------------- 7 8define amdgpu_ps float @global_csub_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) { 9; GCN-LABEL: global_csub_saddr_i32_rtn: 10; GCN: ; %bb.0: 11; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] glc 12; GCN-NEXT: s_waitcnt vmcnt(0) 13; GCN-NEXT: ; return to shader part epilog 14 %zext.offset = zext i32 %voffset to i64 15 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset 16 %rtn = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %gep0, i32 %data) 17 %cast.rtn = bitcast i32 %rtn to float 18 ret float %cast.rtn 19} 20 21define amdgpu_ps float @global_csub_saddr_i32_rtn_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) { 22; GCN-LABEL: global_csub_saddr_i32_rtn_neg128: 23; GCN: ; %bb.0: 24; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:-128 glc 25; GCN-NEXT: s_waitcnt vmcnt(0) 26; GCN-NEXT: ; return to shader part epilog 27 %zext.offset = zext i32 %voffset to i64 28 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset 29 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128 30 %rtn = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %gep1, i32 %data) 31 %cast.rtn = bitcast i32 %rtn to float 32 ret float %cast.rtn 33} 34 35define amdgpu_ps void @global_csub_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) { 36; GCN-LABEL: global_csub_saddr_i32_nortn: 37; GCN: ; %bb.0: 38; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] glc 39; GCN-NEXT: s_endpgm 40 %zext.offset = zext i32 %voffset to i64 41 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset 42 %unused = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %gep0, i32 %data) 43 ret void 44} 45 46define amdgpu_ps void @global_csub_saddr_i32_nortn_neg128(ptr addrspace(1) inreg %sbase, i32 %voffset, i32 %data) { 47; GCN-LABEL: global_csub_saddr_i32_nortn_neg128: 48; GCN: ; %bb.0: 49; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:-128 glc 50; GCN-NEXT: s_endpgm 51 %zext.offset = zext i32 %voffset to i64 52 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset 53 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128 54 %unused = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %gep1, i32 %data) 55 ret void 56} 57 58declare i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) nocapture, i32) #0 59 60attributes #0 = { argmemonly nounwind willreturn } 61