xref: /llvm-project/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir (revision ef91cd3f018411e0ba7989003d7617041e35f650) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination  %s -o - | FileCheck -check-prefix=GCN %s
3
4---
5
6# First operand is FI is in a VGPR, other operand is a VGPR
7name: shrink_vgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
8tracksRegLiveness: true
9stack:
10  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
11body:             |
12  bb.0:
13    liveins: $vgpr0
14
15    ; GCN-LABEL: name: shrink_vgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
16    ; GCN: liveins: $vgpr0
17    ; GCN-NEXT: {{  $}}
18    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
19    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20    ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], [[COPY]], implicit-def $vcc, implicit $exec
21    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
22    %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
23    %1:vgpr_32 = COPY $vgpr0
24    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
25    S_ENDPGM 0, implicit %2
26
27...
28
29---
30
31# First operand is a VGPR, other operand FI is in a VGPR
32name: shrink_vgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
33tracksRegLiveness: true
34stack:
35  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
36body:             |
37  bb.0:
38    liveins: $vgpr0
39
40    ; GCN-LABEL: name: shrink_vgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
41    ; GCN: liveins: $vgpr0
42    ; GCN-NEXT: {{  $}}
43    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
44    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
45    ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[COPY]], [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
46    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
47    %0:vgpr_32 = COPY $vgpr0
48    %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
49    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
50    S_ENDPGM 0, implicit %2
51
52...
53
54---
55
56# First operand is FI is in an SGPR, other operand is a VGPR
57name: shrink_vgpr_fi_sgpr_v_add_i32_e64_no_carry_out_use
58tracksRegLiveness: true
59stack:
60  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
61body:             |
62  bb.0:
63    liveins: $sgpr0
64
65    ; GCN-LABEL: name: shrink_vgpr_fi_sgpr_v_add_i32_e64_no_carry_out_use
66    ; GCN: liveins: $sgpr0
67    ; GCN-NEXT: {{  $}}
68    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
69    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
70    ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
71    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
72    %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
73    %1:sreg_32_xm0 = COPY $sgpr0
74    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
75    S_ENDPGM 0, implicit %2
76
77...
78
79---
80
81# First operand is an SGPR, other operand FI is in a VGPR
82name: shrink_sgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
83tracksRegLiveness: true
84stack:
85  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
86body:             |
87  bb.0:
88    liveins: $sgpr0
89
90    ; GCN-LABEL: name: shrink_sgpr_vgpr_fi_v_add_i32_e64_no_carry_out_use
91    ; GCN: liveins: $sgpr0
92    ; GCN-NEXT: {{  $}}
93    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
94    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
95    ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], [[COPY]], 0, implicit $exec
96    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
97    %0:sreg_32_xm0 = COPY $sgpr0
98    %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
99    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
100    S_ENDPGM 0, implicit %2
101
102...
103
104---
105
106# First operand is FI is in an SGPR, other operand is a VGPR
107name: shrink_sgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
108tracksRegLiveness: true
109stack:
110  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
111body:             |
112  bb.0:
113    liveins: $vgpr0
114
115    ; GCN-LABEL: name: shrink_sgpr_fi_vgpr_v_add_i32_e64_no_carry_out_use
116    ; GCN: liveins: $vgpr0
117    ; GCN-NEXT: {{  $}}
118    ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
119    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
120    ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def $vcc, implicit $exec
121    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
122    %0:sreg_32_xm0 = S_MOV_B32 %stack.0
123    %1:vgpr_32 = COPY $vgpr0
124    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
125    S_ENDPGM 0, implicit %2
126
127...
128
129---
130
131# First operand is a VGPR, other operand FI is in an SGPR
132name: shrink_vgpr_sgpr_fi_v_add_i32_e64_no_carry_out_use
133tracksRegLiveness: true
134stack:
135  - { id: 0, type: default, offset: 0, size: 64, alignment: 16}
136body:             |
137  bb.0:
138    liveins: $vgpr0
139
140    ; GCN-LABEL: name: shrink_vgpr_sgpr_fi_v_add_i32_e64_no_carry_out_use
141    ; GCN: liveins: $vgpr0
142    ; GCN-NEXT: {{  $}}
143    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
144    ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
145    ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def $vcc, implicit $exec
146    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
147    %0:vgpr_32 = COPY $vgpr0
148    %1:sreg_32_xm0 = S_MOV_B32 %stack.0
149    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
150    S_ENDPGM 0, implicit %2
151
152...
153
154---
155
156# First operand is FI is in a VGPR, other operand is an inline imm in a VGPR
157name: shrink_vgpr_imm_fi_vgpr_v_add_i32_e64_no_carry_out_use
158tracksRegLiveness: true
159stack:
160  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
161body:             |
162  bb.0:
163
164    ; GCN-LABEL: name: shrink_vgpr_imm_fi_vgpr_v_add_i32_e64_no_carry_out_use
165    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
166    ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 16, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
167    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
168    %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
169    %1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
170    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
171    S_ENDPGM 0, implicit %2
172
173...
174
175---
176
177# First operand is an inline imm in a VGPR, other operand FI is in a VGPR
178name: shrink_vgpr_imm_vgpr_fi_v_add_i32_e64_no_carry_out_use
179tracksRegLiveness: true
180stack:
181  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
182body:             |
183  bb.0:
184
185    ; GCN-LABEL: name: shrink_vgpr_imm_vgpr_fi_v_add_i32_e64_no_carry_out_use
186    ; GCN: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
187    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
188    %0:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
189    %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
190    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
191    S_ENDPGM 0, implicit %2
192
193...
194
195---
196
197# First operand is FI is in a VGPR, other operand is an literal constant in a VGPR
198name: shrink_vgpr_k_fi_vgpr_v_add_i32_e64_no_carry_out_use
199tracksRegLiveness: true
200stack:
201  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
202body:             |
203  bb.0:
204
205    ; GCN-LABEL: name: shrink_vgpr_k_fi_vgpr_v_add_i32_e64_no_carry_out_use
206    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
207    ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 1234, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
208    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
209    %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
210    %1:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
211    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
212    S_ENDPGM 0, implicit %2
213
214...
215
216---
217
218# First operand is a literal constant in a VGPR, other operand FI is in a VGPR
219name: shrink_vgpr_k_vgpr_fi_v_add_i32_e64_no_carry_out_use
220tracksRegLiveness: true
221stack:
222  - { id: 0, type: default, offset: 0, size: 64, alignment: 16 }
223body:             |
224  bb.0:
225
226    ; GCN-LABEL: name: shrink_vgpr_k_vgpr_fi_v_add_i32_e64_no_carry_out_use
227    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
228    ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %stack.0, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
229    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
230    %0:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
231    %1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
232    %2:vgpr_32, %3:sreg_64 = V_ADD_CO_U32_e64 %0, %1, 0, implicit $exec
233    S_ENDPGM 0, implicit %2
234
235...
236