1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI-SAFE,GCN %s 2; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s 3 4; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-SAFE,GCN %s 5; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,VI-NNAN %s 6 7; GCN-LABEL: {{^}}min_fneg_select_regression_0: 8; GCN-NOT: v_mul 9 10; SI: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0 11 12; VI-SAFE: v_cmp_nle_f32_e32 vcc, 1.0, v0 13; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc 14define amdgpu_ps float @min_fneg_select_regression_0(float %a, float %b) #0 { 15 %fneg.a = fsub float -0.0, %a 16 %cmp.a = fcmp ult float %a, 1.0 17 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0 18 ret float %min.a 19} 20 21; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0: 22; GCN-NOT: v_mul 23 24; SI: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0 25 26; VI-SAFE: v_cmp_nle_f32_e32 vcc, -1.0, v0 27; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc 28 29; VI-NNAN: v_max_f32_e64 v{{[0-9]+}}, -v0, 1.0 30define amdgpu_ps float @min_fneg_select_regression_posk_0(float %a, float %b) #0 { 31 %fneg.a = fsub float -0.0, %a 32 %cmp.a = fcmp ult float %a, -1.0 33 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 34 ret float %min.a 35} 36 37; GCN-LABEL: {{^}}max_fneg_select_regression_0: 38; GCN-NOT: v_mul 39 40; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0 41 42; VI-SAFE: v_cmp_nge_f32_e32 vcc, 1.0, v0 43; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc 44 45; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, -1.0 46define amdgpu_ps float @max_fneg_select_regression_0(float %a) #0 { 47 %fneg.a = fsub float -0.0, %a 48 %cmp.a = fcmp ugt float %a, 1.0 49 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0 50 ret float %min.a 51} 52 53; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0: 54; GCN-NOT: v_mul 55 56; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0 57 58; VI-SAFE: v_cmp_nge_f32_e32 vcc, -1.0, v0 59; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc 60 61; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, 1.0 62define amdgpu_ps float @max_fneg_select_regression_posk_0(float %a) #0 { 63 %fneg.a = fsub float -0.0, %a 64 %cmp.a = fcmp ugt float %a, -1.0 65 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 66 ret float %min.a 67} 68 69; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg1: 70; SI: v_min_legacy_f32_e64 v0, 1.0, -v0 71 72; VI-SAFE: v_cmp_nge_f32_e32 vcc, -1.0, v0 73; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc 74 75; VI-NNAN: v_min_f32_e64 v0, -v0, 1.0 76define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg1(float %a, float %b) #0 { 77 %fneg.a = fneg float %a 78 %cmp.a = fcmp ugt float %a, -1.0 79 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 80 ret float %min.a 81} 82 83; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg1: 84; SI: v_max_legacy_f32_e64 v0, 1.0, -v0 85 86; VI-SAFE: v_cmp_nle_f32_e32 vcc, -1.0, v0 87; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc 88 89; VI-NNAN: v_max_f32_e64 v0, -v0, 1.0 90define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg1(float %a, float %b) #0 { 91 %fneg.a = fneg float %a 92 %cmp.a = fcmp ult float %a, -1.0 93 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 94 ret float %min.a 95} 96 97; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg1: 98; SI: v_min_legacy_f32_e64 v0, -v0, 1.0 99 100; VI-SAFE: v_cmp_lt_f32_e32 vcc, -1.0, v0 101; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc 102 103; VI-NNAN: v_min_f32_e64 v0, -v0, 1.0 104define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg1(float %a, float %b) #0 { 105 %fneg.a = fneg float %a 106 %cmp.a = fcmp ogt float %a, -1.0 107 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 108 ret float %min.a 109} 110 111; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg1: 112; SI: v_max_legacy_f32_e64 v0, -v0, 1.0 113 114; VI-SAFE: v_cmp_gt_f32_e32 vcc, -1.0, v0 115; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc 116 117; VI-NANN: v_max_f32_e64 v0, -v0, 1.0 118define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1(float %a, float %b) #0 { 119 %fneg.a = fneg float %a 120 %cmp.a = fcmp olt float %a, -1.0 121 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0 122 ret float %min.a 123} 124 125; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ugt_a_neg8: 126; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000 127; SI-NEXT: v_min_legacy_f32_e64 v0, [[K]], -v0 128 129; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000 130; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000 131; VI-SAFE: v_cmp_nge_f32_e32 vcc, [[K0]], v0 132; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc 133 134; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000 135; VI-NNAN-NEXT: v_min_f32_e64 v0, -v0, [[K]] 136define amdgpu_ps float @select_fneg_a_or_q_cmp_ugt_a_neg8(float %a, float %b) #0 { 137 %fneg.a = fneg float %a 138 %cmp.a = fcmp ugt float %a, -8.0 139 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0 140 ret float %min.a 141} 142 143; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ult_a_neg8: 144; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000 145; SI-NEXT: v_max_legacy_f32_e64 v0, [[K]], -v0 146 147; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000 148; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000 149; VI-SAFE: v_cmp_nle_f32_e32 vcc, [[K0]], v0 150; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc 151 152; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000 153; VI-NNAN-NEXT: v_max_f32_e64 v0, -v0, [[K]] 154define amdgpu_ps float @select_fneg_a_or_q_cmp_ult_a_neg8(float %a, float %b) #0 { 155 %fneg.a = fneg float %a 156 %cmp.a = fcmp ult float %a, -8.0 157 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0 158 ret float %min.a 159} 160 161; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_ogt_a_neg8: 162; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000 163; SI-NEXT: v_min_legacy_f32_e64 v0, -v0, [[K]] 164 165; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000 166; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000 167; VI-SAFE: v_cmp_lt_f32_e32 vcc, [[K0]], v0 168; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc 169 170; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000 171; VI-NNAN-NEXT: v_min_f32_e64 v0, -v0, [[K]] 172define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg8(float %a, float %b) #0 { 173 %fneg.a = fneg float %a 174 %cmp.a = fcmp ogt float %a, -8.0 175 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0 176 ret float %min.a 177} 178 179; GCN-LABEL: {{^}}select_fneg_a_or_q_cmp_olt_a_neg8: 180; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000 181; SI-NEXT: v_max_legacy_f32_e64 v0, -v0, [[K]] 182 183 184; VI-SAFE-DAG: s_mov_b32 [[K0:s[0-9]+]], 0xc1000000 185; VI-SAFE-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x41000000 186; VI-SAFE: v_cmp_gt_f32_e32 vcc, [[K0]], v0 187; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, [[K1]], -v0, vcc 188 189; VI-NNAN: s_mov_b32 [[K:s[0-9]+]], 0x41000000 190; VI-NNAN-NEXT: v_max_f32_e64 v0, -v0, [[K]] 191define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg8(float %a, float %b) #0 { 192 %fneg.a = fneg float %a 193 %cmp.a = fcmp olt float %a, -8.0 194 %min.a = select i1 %cmp.a, float %fneg.a, float 8.0 195 ret float %min.a 196} 197 198; GCN-LABEL: {{^}}select_fneg_a_or_neg1_cmp_olt_a_1: 199; SI: v_max_legacy_f32_e64 v0, -v0, -1.0 200 201; VI-SAFE: v_cmp_gt_f32_e32 vcc, 1.0, v0 202; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, -1.0, -v0, vcc 203 204; VI-NNAN: v_max_f32_e64 v0, -v0, -1.0 205define amdgpu_ps float @select_fneg_a_or_neg1_cmp_olt_a_1(float %a, float %b) #0 { 206 %fneg.a = fneg float %a 207 %cmp.a = fcmp olt float %a, 1.0 208 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0 209 ret float %min.a 210} 211 212; GCN-LABEL: {{^}}ult_a_select_fneg_a_b: 213; SI: v_cmp_nge_f32_e32 vcc, v0, v1 214; SI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc 215 216; VI-SAFE: v_cmp_nge_f32_e32 vcc, v0, v1 217; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc 218 219; VI-NNAN: v_cmp_lt_f32_e32 vcc, v0, v1 220; VI-NNAN-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc 221define amdgpu_ps float @ult_a_select_fneg_a_b(float %a, float %b) #0 { 222 %fneg.a = fneg float %a 223 %cmp.a = fcmp ult float %a, %b 224 %min.a = select i1 %cmp.a, float %fneg.a, float %b 225 ret float %min.a 226} 227 228; GCN-LABEL: {{^}}ugt_a_select_fneg_a_b: 229; SI: v_cmp_nle_f32_e32 vcc, v0, v1 230; SI-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc 231 232; VI-SAFE: v_cmp_nle_f32_e32 vcc, v0, v1 233; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc 234 235; VI-NNAN: v_cmp_gt_f32_e32 vcc, v0, v1 236; VI-NNAN-NEXT: v_cndmask_b32_e64 v0, v1, -v0, vcc 237define amdgpu_ps float @ugt_a_select_fneg_a_b(float %a, float %b) #0 { 238 %fneg.a = fneg float %a 239 %cmp.a = fcmp ugt float %a, %b 240 %min.a = select i1 %cmp.a, float %fneg.a, float %b 241 ret float %min.a 242} 243 244attributes #0 = { nounwind } 245attributes #1 = { nounwind readnone } 246