1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s 2; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs | FileCheck --check-prefix=GCN %s 3 4declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 5declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 6declare i32 @llvm.amdgcn.workitem.id.x() 7declare i32 @llvm.amdgcn.workgroup.id.x() 8declare void @llvm.amdgcn.s.barrier() 9 10@test_local.temp = internal addrspace(3) global [1 x i32] undef, align 4 11@test_global_local.temp = internal addrspace(3) global [1 x i32] undef, align 4 12 13 14; GCN-LABEL: {{^}}test_local 15; GCN: v_mov_b32_e32 v[[VAL:[0-9]+]], 0x777 16; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]] 17; GCN: s_waitcnt lgkmcnt(0){{$}} 18; GCN-NEXT: s_barrier 19; GCN: flat_store_dword 20define amdgpu_kernel void @test_local(ptr addrspace(1) %arg) { 21bb: 22 %i = alloca ptr addrspace(1), align 4, addrspace(5) 23 store ptr addrspace(1) %arg, ptr addrspace(5) %i, align 4 24 %i1 = call i32 @llvm.amdgcn.workitem.id.x() 25 %i2 = zext i32 %i1 to i64 26 %i3 = icmp eq i64 %i2, 0 27 br i1 %i3, label %bb4, label %bb5 28 29bb4: ; preds = %bb 30 store i32 1911, ptr addrspace(3) @test_local.temp, align 4 31 br label %bb5 32 33bb5: ; preds = %bb4, %bb 34 fence syncscope("workgroup") release 35 call void @llvm.amdgcn.s.barrier() 36 fence syncscope("workgroup") acquire 37 %i6 = load i32, ptr addrspace(3) @test_local.temp, align 4 38 %i7 = load ptr addrspace(1), ptr addrspace(5) %i, align 4 39 %i8 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 40 %i9 = call i32 @llvm.amdgcn.workitem.id.x() 41 %i10 = call i32 @llvm.amdgcn.workgroup.id.x() 42 %i11 = getelementptr inbounds i8, ptr addrspace(4) %i8, i64 4 43 %i13 = load i16, ptr addrspace(4) %i11, align 4 44 %i14 = zext i16 %i13 to i32 45 %i15 = mul i32 %i10, %i14 46 %i16 = add i32 %i15, %i9 47 %i17 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 48 %i18 = zext i32 %i16 to i64 49 %i20 = load i64, ptr addrspace(4) %i17, align 8 50 %i21 = add i64 %i20, %i18 51 %i22 = getelementptr inbounds i32, ptr addrspace(1) %i7, i64 %i21 52 store i32 %i6, ptr addrspace(1) %i22, align 4 53 ret void 54} 55 56; GCN-LABEL: {{^}}test_global 57; GCN: v_add_u32_e32 v{{[0-9]+}}, vcc, 0x888, v{{[0-9]+}} 58; GCN: flat_store_dword 59; GCN: s_waitcnt vmcnt(0){{$}} 60; GCN-NEXT: s_barrier 61define amdgpu_kernel void @test_global(ptr addrspace(1) %arg) { 62bb: 63 %i = alloca ptr addrspace(1), align 4, addrspace(5) 64 %i1 = alloca i32, align 4, addrspace(5) 65 store ptr addrspace(1) %arg, ptr addrspace(5) %i, align 4 66 store i32 0, ptr addrspace(5) %i1, align 4 67 br label %bb2 68 69bb2: ; preds = %bb56, %bb 70 %i3 = load i32, ptr addrspace(5) %i1, align 4 71 %i4 = sext i32 %i3 to i64 72 %i5 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 73 %i6 = call i32 @llvm.amdgcn.workitem.id.x() 74 %i7 = call i32 @llvm.amdgcn.workgroup.id.x() 75 %i8 = getelementptr inbounds i8, ptr addrspace(4) %i5, i64 4 76 %i10 = load i16, ptr addrspace(4) %i8, align 4 77 %i11 = zext i16 %i10 to i32 78 %i12 = mul i32 %i7, %i11 79 %i13 = add i32 %i12, %i6 80 %i14 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 81 %i15 = zext i32 %i13 to i64 82 %i17 = load i64, ptr addrspace(4) %i14, align 8 83 %i18 = add i64 %i17, %i15 84 %i19 = icmp ult i64 %i4, %i18 85 br i1 %i19, label %bb20, label %bb59 86 87bb20: ; preds = %bb2 88 %i21 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 89 %i22 = call i32 @llvm.amdgcn.workitem.id.x() 90 %i23 = call i32 @llvm.amdgcn.workgroup.id.x() 91 %i24 = getelementptr inbounds i8, ptr addrspace(4) %i21, i64 4 92 %i26 = load i16, ptr addrspace(4) %i24, align 4 93 %i27 = zext i16 %i26 to i32 94 %i28 = mul i32 %i23, %i27 95 %i29 = add i32 %i28, %i22 96 %i30 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 97 %i31 = zext i32 %i29 to i64 98 %i33 = load i64, ptr addrspace(4) %i30, align 8 99 %i34 = add i64 %i33, %i31 100 %i35 = add i64 %i34, 2184 101 %i36 = trunc i64 %i35 to i32 102 %i37 = load ptr addrspace(1), ptr addrspace(5) %i, align 4 103 %i38 = load i32, ptr addrspace(5) %i1, align 4 104 %i39 = sext i32 %i38 to i64 105 %i40 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 106 %i41 = call i32 @llvm.amdgcn.workitem.id.x() 107 %i42 = call i32 @llvm.amdgcn.workgroup.id.x() 108 %i43 = getelementptr inbounds i8, ptr addrspace(4) %i40, i64 4 109 %i45 = load i16, ptr addrspace(4) %i43, align 4 110 %i46 = zext i16 %i45 to i32 111 %i47 = mul i32 %i42, %i46 112 %i48 = add i32 %i47, %i41 113 %i49 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 114 %i50 = zext i32 %i48 to i64 115 %i52 = load i64, ptr addrspace(4) %i49, align 8 116 %i53 = add i64 %i52, %i50 117 %i54 = add i64 %i39, %i53 118 %i55 = getelementptr inbounds i32, ptr addrspace(1) %i37, i64 %i54 119 store i32 %i36, ptr addrspace(1) %i55, align 4 120 fence syncscope("workgroup") release 121 call void @llvm.amdgcn.s.barrier() 122 fence syncscope("workgroup") acquire 123 br label %bb56 124 125bb56: ; preds = %bb20 126 %i57 = load i32, ptr addrspace(5) %i1, align 4 127 %i58 = add nsw i32 %i57, 1 128 store i32 %i58, ptr addrspace(5) %i1, align 4 129 br label %bb2 130 131bb59: ; preds = %bb2 132 ret void 133} 134 135; GCN-LABEL: {{^}}test_global_local 136; GCN: v_mov_b32_e32 v[[VAL:[0-9]+]], 0x999 137; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]] 138; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}} 139; GCN-NEXT: s_barrier 140; GCN: flat_store_dword 141define amdgpu_kernel void @test_global_local(ptr addrspace(1) %arg) { 142bb: 143 %i = alloca ptr addrspace(1), align 4, addrspace(5) 144 store ptr addrspace(1) %arg, ptr addrspace(5) %i, align 4 145 %i1 = load ptr addrspace(1), ptr addrspace(5) %i, align 4 146 %i2 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 147 %i3 = call i32 @llvm.amdgcn.workitem.id.x() 148 %i4 = call i32 @llvm.amdgcn.workgroup.id.x() 149 %i5 = getelementptr inbounds i8, ptr addrspace(4) %i2, i64 4 150 %i7 = load i16, ptr addrspace(4) %i5, align 4 151 %i8 = zext i16 %i7 to i32 152 %i9 = mul i32 %i4, %i8 153 %i10 = add i32 %i9, %i3 154 %i11 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 155 %i12 = zext i32 %i10 to i64 156 %i14 = load i64, ptr addrspace(4) %i11, align 8 157 %i15 = add i64 %i14, %i12 158 %i16 = getelementptr inbounds i32, ptr addrspace(1) %i1, i64 %i15 159 store i32 1, ptr addrspace(1) %i16, align 4 160 %i17 = call i32 @llvm.amdgcn.workitem.id.x() 161 %i18 = zext i32 %i17 to i64 162 %i19 = icmp eq i64 %i18, 0 163 br i1 %i19, label %bb20, label %bb21 164 165bb20: ; preds = %bb 166 store i32 2457, ptr addrspace(3) @test_global_local.temp, align 4 167 br label %bb21 168 169bb21: ; preds = %bb20, %bb 170 fence syncscope("workgroup") release 171 call void @llvm.amdgcn.s.barrier() 172 fence syncscope("workgroup") acquire 173 %i22 = load i32, ptr addrspace(3) @test_global_local.temp, align 4 174 %i23 = load ptr addrspace(1), ptr addrspace(5) %i, align 4 175 %i24 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() 176 %i25 = call i32 @llvm.amdgcn.workitem.id.x() 177 %i26 = call i32 @llvm.amdgcn.workgroup.id.x() 178 %i27 = getelementptr inbounds i8, ptr addrspace(4) %i24, i64 4 179 %i29 = load i16, ptr addrspace(4) %i27, align 4 180 %i30 = zext i16 %i29 to i32 181 %i31 = mul i32 %i26, %i30 182 %i32 = add i32 %i31, %i25 183 %i33 = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() 184 %i34 = zext i32 %i32 to i64 185 %i36 = load i64, ptr addrspace(4) %i33, align 8 186 %i37 = add i64 %i36, %i34 187 %i38 = getelementptr inbounds i32, ptr addrspace(1) %i23, i64 %i37 188 store i32 %i22, ptr addrspace(1) %i38, align 4 189 ret void 190} 191