xref: /llvm-project/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll (revision ceb68eea8c5cfd7893d55afaef93932762bbebaa)
1; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
3
4; GCN-LABEL: {{^}}extract_vector_elt_v3f64_2:
5; GCN: buffer_load_dwordx4
6; GCN: buffer_load_dwordx2
7; GCN: buffer_store_dwordx2
8define amdgpu_kernel void @extract_vector_elt_v3f64_2(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
9  %ld = load volatile <3 x double>, ptr addrspace(1) %in
10  %elt = extractelement <3 x double> %ld, i32 2
11  store volatile double %elt, ptr addrspace(1) %out
12  ret void
13}
14
15; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3f64:
16; GCN-NOT: buffer_load
17; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 1
18; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
19; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
20; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 2
21; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
22; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
23; GCN: store_dwordx2 v[{{[0-9:]+}}]
24define amdgpu_kernel void @dyn_extract_vector_elt_v3f64(ptr addrspace(1) %out, <3 x double> %foo, i32 %elt) #0 {
25  %dynelt = extractelement <3 x double> %foo, i32 %elt
26  store volatile double %dynelt, ptr addrspace(1) %out
27  ret void
28}
29
30; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4f64:
31; GCN-NOT: buffer_load
32; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 1
33; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
34; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
35; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 2
36; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
37; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
38; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 3
39; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
40; GCN-DAG: s_cselect_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
41; GCN: store_dwordx2 v[{{[0-9:]+}}]
42define amdgpu_kernel void @dyn_extract_vector_elt_v4f64(ptr addrspace(1) %out, <4 x double> %foo, i32 %elt) #0 {
43  %dynelt = extractelement <4 x double> %foo, i32 %elt
44  store volatile double %dynelt, ptr addrspace(1) %out
45  ret void
46}
47
48attributes #0 = { nounwind }
49