xref: /llvm-project/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9)
1; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
2; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
3
4@lds = addrspace(3) global [512 x float] undef, align 4
5
6; offset0 is larger than offset1
7
8; SI-LABEL: {{^}}offset_order:
9; SI-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
10; SI-DAG: ds_read_b64 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:8
11; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:12
12; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:6 offset1:248
13define amdgpu_kernel void @offset_order(ptr addrspace(1) %out) {
14entry:
15  %val0 = load float, ptr addrspace(3) @lds
16
17  %ptr1 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 256
18  %val1 = load float, ptr addrspace(3) %ptr1
19  %add1 = fadd float %val0, %val1
20
21  %ptr2 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 3
22  %val2 = load float, ptr addrspace(3) %ptr2
23  %add2 = fadd float %add1, %val2
24
25  %ptr3 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 2
26  %val3 = load float, ptr addrspace(3) %ptr3
27  %add3 = fadd float %add2, %val3
28
29  %ptr4 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 12
30  %val4 = load float, ptr addrspace(3) %ptr4
31  %add4 = fadd float %add3, %val4
32
33  %ptr5 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 14
34  %val5 = load float, ptr addrspace(3) %ptr5
35  %add5 = fadd float %add4, %val5
36
37  %ptr6 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 11
38  %val6 = load float, ptr addrspace(3) %ptr6
39  %add6 = fadd float %add5, %val6
40  store float %add6, ptr addrspace(1) %out
41  ret void
42}
43