1# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN 2# RUN: llc -mtriple=amdgcn -mcpu=gfx940 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=GCN 3 4--- 5# GCN-LABEL: name: dpp64_old_impdef 6# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %1, 0, %0, 337, 15, 15, 1, implicit $mode, implicit $exec 7--- 8name: dpp64_old_impdef 9tracksRegLiveness: true 10body: | 11 bb.0: 12 %0:vreg_64_align2 = IMPLICIT_DEF 13 %1:vreg_64_align2 = IMPLICIT_DEF 14 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO %1, %0, 337, 15, 15, 1, implicit $exec 15 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec 16... 17 18# GCN-LABEL: name: dpp64_old_undef 19# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp undef %1:vreg_64_align2, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec 20--- 21name: dpp64_old_undef 22tracksRegLiveness: true 23body: | 24 bb.0: 25 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec 26 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec 27... 28 29# GCN-LABEL: name: dpp64_old_is_0 30# GCN: %3:vreg_64_align2 = V_CEIL_F64_dpp %4, 0, undef %2:vreg_64_align2, 337, 15, 15, 1, implicit $mode, implicit $exec 31name: dpp64_old_is_0 32tracksRegLiveness: true 33body: | 34 bb.0: 35 %1:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec 36 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1, undef %0:vreg_64_align2, 337, 15, 15, 1, implicit $exec 37 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec 38... 39 40# DPP64 does not support all control values and must be split to become legal 41# GCN-LABEL: name: dpp64_illegal_ctrl 42# GCN: %4:vgpr_32 = V_MOV_B32_dpp undef %1.sub0:vreg_64_align2, undef %2.sub0:vreg_64_align2, 1, 15, 15, 1, implicit $exec 43# GCN: %5:vgpr_32 = V_MOV_B32_dpp undef %1.sub1:vreg_64_align2, undef %2.sub1:vreg_64_align2, 1, 15, 15, 1, implicit $exec 44# GCN: %0:vreg_64_align2 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1 45# GCN: %3:vreg_64_align2 = V_CEIL_F64_e32 %0, implicit $mode, implicit $exec 46name: dpp64_illegal_ctrl 47tracksRegLiveness: true 48body: | 49 bb.0: 50 %2:vreg_64_align2 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64_align2, undef %0:vreg_64_align2, 1, 15, 15, 1, implicit $exec 51 %3:vreg_64_align2 = V_CEIL_F64_e32 %2, implicit $mode, implicit $exec 52... 53