xref: /llvm-project/llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll (revision 7652a59407018c057cdc1163c9f64b5b6f0954eb)
1; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
2; RUN: llc -mtriple=amdgcn -enable-new-pm -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
3
4; GCN-LABEL: name:            s_ctpop_i32
5; GCN: S_BCNT1_I32_B32
6define amdgpu_kernel void @s_ctpop_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
7  %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
8  store i32 %ctpop, ptr addrspace(1) %out, align 4
9  ret void
10}
11
12; GCN-LABEL: name:            s_ctpop_i64
13; GCN: %[[BCNT:[0-9]+]]:sreg_32 = S_BCNT1_I32_B64
14; GCN: %[[SREG1:[0-9]+]]:sreg_32 = COPY %[[BCNT]]
15; GCN: %[[SREG2:[0-9]+]]:sreg_32 = S_MOV_B32 0
16; GCN: REG_SEQUENCE killed %[[SREG1]], %subreg.sub0, killed %[[SREG2]], %subreg.sub1
17define amdgpu_kernel void @s_ctpop_i64(ptr addrspace(1) noalias %out, i64 %val) nounwind {
18  %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
19  %truncctpop = trunc i64 %ctpop to i32
20  store i32 %truncctpop, ptr addrspace(1) %out, align 4
21  ret void
22}
23
24; GCN-LABEL: name:            v_ctpop_i32
25; GCN: V_BCNT_U32_B32_e64
26define amdgpu_kernel void @v_ctpop_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
27  %tid = call i32 @llvm.amdgcn.workitem.id.x()
28  %in.gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid
29  %val = load i32, ptr addrspace(1) %in.gep, align 4
30  %ctpop = call i32 @llvm.ctpop.i32(i32 %val) nounwind readnone
31  store i32 %ctpop, ptr addrspace(1) %out, align 4
32  ret void
33}
34
35; GCN-LABEL: name:            v_ctpop_i64
36; GCN: %[[BCNT1:[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 killed %{{[0-9]+}}, 0, implicit $exec
37; GCN: %[[BCNT2:[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 killed %{{[0-9]+}}, killed %[[BCNT1]], implicit $exec
38; GCN: %[[VGPR1:[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
39; GCN: REG_SEQUENCE killed %[[BCNT2]], %subreg.sub0, killed %[[VGPR1]], %subreg.sub1
40define amdgpu_kernel void @v_ctpop_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
41  %tid = call i32 @llvm.amdgcn.workitem.id.x()
42  %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
43  %val = load i64, ptr addrspace(1) %in.gep, align 8
44  %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
45  %truncctpop = trunc i64 %ctpop to i32
46  store i32 %truncctpop, ptr addrspace(1) %out, align 4
47  ret void
48}
49
50declare i64 @llvm.ctpop.i64(i64) nounwind readnone
51
52declare i32 @llvm.ctpop.i32(i32) nounwind readnone
53
54declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
55