1; RUN: llc -mtriple=amdgcn -mcpu=gfx902 -verify-machineinstrs -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s 2 3; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause 4; GCN: S_LOAD_DWORDX4 5; GCN: GLOBAL_LOAD_DWORDX4_SADDR 6; GCN: GLOBAL_LOAD_DWORDX4_SADDR 7; GCN: GLOBAL_LOAD_DWORDX4_SADDR 8; GCN: GLOBAL_LOAD_DWORDX4_SADDR 9; GCN-NEXT: KILL 10define amdgpu_kernel void @vector_clause(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1) { 11bb: 12 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 13 %tmp2 = zext i32 %tmp to i64 14 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2 15 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16 16 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2 17 %tmp6 = add nuw nsw i64 %tmp2, 1 18 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp6 19 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 16 20 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp6 21 %tmp10 = add nuw nsw i64 %tmp2, 2 22 %tmp11 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp10 23 %tmp12 = load <4 x i32>, ptr addrspace(1) %tmp11, align 16 24 %tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp10 25 %tmp14 = add nuw nsw i64 %tmp2, 3 26 %tmp15 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp14 27 %tmp16 = load <4 x i32>, ptr addrspace(1) %tmp15, align 16 28 %tmp17 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp14 29 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 16 30 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 16 31 store <4 x i32> %tmp12, ptr addrspace(1) %tmp13, align 16 32 store <4 x i32> %tmp16, ptr addrspace(1) %tmp17, align 16 33 ret void 34} 35 36; GCN-LABEL: {{^}}name:{{[ ]*}}no_vector_clause 37; GCN-NOT: BUNDLE 38; GCN-NOT: KILL 39define amdgpu_kernel void @no_vector_clause(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1) #0 { 40bb: 41 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 42 %tmp2 = zext i32 %tmp to i64 43 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2 44 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16 45 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2 46 %tmp6 = add nuw nsw i64 %tmp2, 1 47 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp6 48 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 16 49 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp6 50 %tmp10 = add nuw nsw i64 %tmp2, 2 51 %tmp11 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp10 52 %tmp12 = load <4 x i32>, ptr addrspace(1) %tmp11, align 16 53 %tmp13 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp10 54 %tmp14 = add nuw nsw i64 %tmp2, 3 55 %tmp15 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp14 56 %tmp16 = load <4 x i32>, ptr addrspace(1) %tmp15, align 16 57 %tmp17 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp14 58 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 16 59 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 16 60 store <4 x i32> %tmp12, ptr addrspace(1) %tmp13, align 16 61 store <4 x i32> %tmp16, ptr addrspace(1) %tmp17, align 16 62 ret void 63} 64 65declare i32 @llvm.amdgcn.workitem.id.x() 66 67attributes #0 = { "amdgpu-max-memory-clause"="1" } 68 69