1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4define amdgpu_kernel void @vectorLoadCombine(ptr %in, ptr %out) { 5; GCN-LABEL: vectorLoadCombine: 6; GCN: ; %bb.0: ; %entry 7; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 8; GCN-NEXT: s_waitcnt lgkmcnt(0) 9; GCN-NEXT: v_mov_b32_e32 v0, s0 10; GCN-NEXT: v_mov_b32_e32 v1, s1 11; GCN-NEXT: flat_load_dword v2, v[0:1] 12; GCN-NEXT: v_mov_b32_e32 v0, s2 13; GCN-NEXT: v_mov_b32_e32 v1, s3 14; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 15; GCN-NEXT: flat_store_dword v[0:1], v2 16; GCN-NEXT: s_endpgm 17entry: 18 %0 = load <4 x i8>, ptr %in, align 4 19 %1 = extractelement <4 x i8> %0, i32 0 20 %2 = extractelement <4 x i8> %0, i32 1 21 %3 = extractelement <4 x i8> %0, i32 2 22 %4 = extractelement <4 x i8> %0, i32 3 23 %zext0 = zext i8 %1 to i32 24 %zext1 = zext i8 %2 to i32 25 %shift1 = shl nuw nsw i32 %zext1, 8 26 %insert1 = or i32 %shift1, %zext0 27 %zext2 = zext i8 %3 to i32 28 %shift2 = shl nuw nsw i32 %zext2, 16 29 %insert2 = or i32 %insert1, %shift2 30 %zext3 = zext i8 %4 to i32 31 %shift3 = shl nuw i32 %zext3, 24 32 %insert3 = or i32 %insert2, %shift3 33 store i32 %insert3, ptr %out 34 ret void 35} 36 37define amdgpu_kernel void @vectorLoadShuffle(ptr %in, ptr %out) { 38; GCN-LABEL: vectorLoadShuffle: 39; GCN: ; %bb.0: ; %entry 40; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 41; GCN-NEXT: s_waitcnt lgkmcnt(0) 42; GCN-NEXT: v_mov_b32_e32 v0, s0 43; GCN-NEXT: v_mov_b32_e32 v1, s1 44; GCN-NEXT: flat_load_dword v2, v[0:1] 45; GCN-NEXT: s_mov_b32 s0, 0x7050604 46; GCN-NEXT: v_mov_b32_e32 v0, s2 47; GCN-NEXT: v_mov_b32_e32 v1, s3 48; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 49; GCN-NEXT: v_perm_b32 v2, v2, v2, s0 50; GCN-NEXT: flat_store_dword v[0:1], v2 51; GCN-NEXT: s_endpgm 52entry: 53 %0 = load <4 x i8>, ptr %in, align 4 54 %1 = extractelement <4 x i8> %0, i32 0 55 %2 = extractelement <4 x i8> %0, i32 1 56 %3 = extractelement <4 x i8> %0, i32 2 57 %4 = extractelement <4 x i8> %0, i32 3 58 %zext0 = zext i8 %1 to i32 59 %zext1 = zext i8 %3 to i32 60 %shift1 = shl nuw nsw i32 %zext1, 8 61 %insert1 = or i32 %shift1, %zext0 62 %zext2 = zext i8 %2 to i32 63 %shift2 = shl nuw nsw i32 %zext2, 16 64 %insert2 = or i32 %insert1, %shift2 65 %zext3 = zext i8 %4 to i32 66 %shift3 = shl nuw i32 %zext3, 24 67 %insert3 = or i32 %insert2, %shift3 68 store i32 %insert3, ptr %out 69 ret void 70} 71define i32 @load_2xi16_combine(ptr addrspace(1) %p) #0 { 72; GCN-LABEL: load_2xi16_combine: 73; GCN: ; %bb.0: 74; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 75; GCN-NEXT: global_load_dword v0, v[0:1], off 76; GCN-NEXT: s_waitcnt vmcnt(0) 77; GCN-NEXT: s_setpc_b64 s[30:31] 78 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 1 79 %p.0 = load i16, ptr addrspace(1) %p, align 4 80 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4 81 %zext.0 = zext i16 %p.0 to i32 82 %zext.1 = zext i16 %p.1 to i32 83 %shl.1 = shl i32 %zext.1, 16 84 %or = or i32 %zext.0, %shl.1 85 ret i32 %or 86} 87 88define i32 @load_2xi16_noncombine(ptr addrspace(1) %p) #0 { 89; GCN-LABEL: load_2xi16_noncombine: 90; GCN: ; %bb.0: 91; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 92; GCN-NEXT: global_load_ushort v2, v[0:1], off 93; GCN-NEXT: global_load_ushort v3, v[0:1], off offset:4 94; GCN-NEXT: s_waitcnt vmcnt(0) 95; GCN-NEXT: v_lshl_or_b32 v0, v3, 16, v2 96; GCN-NEXT: s_setpc_b64 s[30:31] 97 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 2 98 %p.0 = load i16, ptr addrspace(1) %p, align 4 99 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4 100 %zext.0 = zext i16 %p.0 to i32 101 %zext.1 = zext i16 %p.1 to i32 102 %shl.1 = shl i32 %zext.1, 16 103 %or = or i32 %zext.0, %shl.1 104 ret i32 %or 105} 106 107define i64 @load_2xi32_combine(ptr addrspace(1) %p) #0 { 108; GCN-LABEL: load_2xi32_combine: 109; GCN: ; %bb.0: 110; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 111; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off 112; GCN-NEXT: s_waitcnt vmcnt(0) 113; GCN-NEXT: s_setpc_b64 s[30:31] 114 %gep.p = getelementptr i32, ptr addrspace(1) %p, i32 1 115 %p.0 = load i32, ptr addrspace(1) %p, align 4 116 %p.1 = load i32, ptr addrspace(1) %gep.p, align 4 117 %zext.0 = zext i32 %p.0 to i64 118 %zext.1 = zext i32 %p.1 to i64 119 %shl.1 = shl i64 %zext.1, 32 120 %or = or i64 %zext.0, %shl.1 121 ret i64 %or 122} 123 124define i64 @load_2xi32_noncombine(ptr addrspace(1) %p) #0 { 125; GCN-LABEL: load_2xi32_noncombine: 126; GCN: ; %bb.0: 127; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 128; GCN-NEXT: global_load_dword v2, v[0:1], off 129; GCN-NEXT: global_load_dword v3, v[0:1], off offset:8 130; GCN-NEXT: s_waitcnt vmcnt(1) 131; GCN-NEXT: v_mov_b32_e32 v0, v2 132; GCN-NEXT: s_waitcnt vmcnt(0) 133; GCN-NEXT: v_mov_b32_e32 v1, v3 134; GCN-NEXT: s_setpc_b64 s[30:31] 135 %gep.p = getelementptr i32, ptr addrspace(1) %p, i32 2 136 %p.0 = load i32, ptr addrspace(1) %p, align 4 137 %p.1 = load i32, ptr addrspace(1) %gep.p, align 4 138 %zext.0 = zext i32 %p.0 to i64 139 %zext.1 = zext i32 %p.1 to i64 140 %shl.1 = shl i64 %zext.1, 32 141 %or = or i64 %zext.0, %shl.1 142 ret i64 %or 143} 144 145define i64 @load_4xi16_combine(ptr addrspace(1) %p) #0 { 146; GCN-LABEL: load_4xi16_combine: 147; GCN: ; %bb.0: 148; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 149; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off 150; GCN-NEXT: s_waitcnt vmcnt(0) 151; GCN-NEXT: s_setpc_b64 s[30:31] 152 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 1 153 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2 154 %gep.3p = getelementptr i16, ptr addrspace(1) %p, i32 3 155 %p.0 = load i16, ptr addrspace(1) %p, align 4 156 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4 157 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4 158 %p.3 = load i16, ptr addrspace(1) %gep.3p, align 4 159 %zext.0 = zext i16 %p.0 to i64 160 %zext.1 = zext i16 %p.1 to i64 161 %zext.2 = zext i16 %p.2 to i64 162 %zext.3 = zext i16 %p.3 to i64 163 %shl.1 = shl i64 %zext.1, 16 164 %or.1 = or i64 %zext.0, %shl.1 165 %shl.2 = shl i64 %zext.2, 32 166 %or.2 = or i64 %or.1, %shl.2 167 %shl.3 = shl i64 %zext.3, 48 168 %or.3 = or i64 %or.2, %shl.3 169 ret i64 %or.3 170} 171 172 173define i64 @load_4xi16_noncombine(ptr addrspace(1) %p) #0 { 174; GCN-LABEL: load_4xi16_noncombine: 175; GCN: ; %bb.0: 176; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 177; GCN-NEXT: global_load_dwordx2 v[2:3], v[0:1], off 178; GCN-NEXT: s_mov_b32 s4, 0xffff 179; GCN-NEXT: s_waitcnt vmcnt(0) 180; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 181; GCN-NEXT: v_bfi_b32 v0, s4, v2, v3 182; GCN-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 183; GCN-NEXT: s_setpc_b64 s[30:31] 184 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 3 185 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2 186 %gep.3p = getelementptr i16, ptr addrspace(1) %p, i32 1 187 %p.0 = load i16, ptr addrspace(1) %p, align 4 188 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4 189 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4 190 %p.3 = load i16, ptr addrspace(1) %gep.3p, align 4 191 %zext.0 = zext i16 %p.0 to i64 192 %zext.1 = zext i16 %p.1 to i64 193 %zext.2 = zext i16 %p.2 to i64 194 %zext.3 = zext i16 %p.3 to i64 195 %shl.1 = shl i64 %zext.1, 16 196 %or.1 = or i64 %zext.0, %shl.1 197 %shl.2 = shl i64 %zext.2, 32 198 %or.2 = or i64 %or.1, %shl.2 199 %shl.3 = shl i64 %zext.3, 48 200 %or.3 = or i64 %or.2, %shl.3 201 ret i64 %or.3 202} 203 204define i64 @load_3xi16_combine(ptr addrspace(1) %p) #0 { 205; GCN-LABEL: load_3xi16_combine: 206; GCN: ; %bb.0: 207; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 208; GCN-NEXT: global_load_dword v2, v[0:1], off 209; GCN-NEXT: global_load_ushort v3, v[0:1], off offset:4 210; GCN-NEXT: s_waitcnt vmcnt(1) 211; GCN-NEXT: v_mov_b32_e32 v0, v2 212; GCN-NEXT: s_waitcnt vmcnt(0) 213; GCN-NEXT: v_mov_b32_e32 v1, v3 214; GCN-NEXT: s_setpc_b64 s[30:31] 215 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 1 216 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2 217 %p.0 = load i16, ptr addrspace(1) %p, align 4 218 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4 219 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4 220 %zext.0 = zext i16 %p.0 to i64 221 %zext.1 = zext i16 %p.1 to i64 222 %zext.2 = zext i16 %p.2 to i64 223 %shl.1 = shl i64 %zext.1, 16 224 %or.1 = or i64 %zext.0, %shl.1 225 %shl.2 = shl i64 %zext.2, 32 226 %or.2 = or i64 %or.1, %shl.2 227 ret i64 %or.2 228} 229 230define i64 @load_3xi16_noncombine(ptr addrspace(1) %p) #0 { 231; GCN-LABEL: load_3xi16_noncombine: 232; GCN: ; %bb.0: 233; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 234; GCN-NEXT: global_load_ushort v2, v[0:1], off 235; GCN-NEXT: global_load_dword v3, v[0:1], off offset:4 236; GCN-NEXT: s_mov_b32 s4, 0x3020504 237; GCN-NEXT: s_waitcnt vmcnt(0) 238; GCN-NEXT: v_perm_b32 v0, v2, v3, s4 239; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v3 240; GCN-NEXT: s_setpc_b64 s[30:31] 241 %gep.p = getelementptr i16, ptr addrspace(1) %p, i32 3 242 %gep.2p = getelementptr i16, ptr addrspace(1) %p, i32 2 243 %p.0 = load i16, ptr addrspace(1) %p, align 4 244 %p.1 = load i16, ptr addrspace(1) %gep.p, align 4 245 %p.2 = load i16, ptr addrspace(1) %gep.2p, align 4 246 %zext.0 = zext i16 %p.0 to i64 247 %zext.1 = zext i16 %p.1 to i64 248 %zext.2 = zext i16 %p.2 to i64 249 %shl.1 = shl i64 %zext.1, 16 250 %or.1 = or i64 %zext.0, %shl.1 251 %shl.2 = shl i64 %zext.2, 32 252 %or.2 = or i64 %or.1, %shl.2 253 ret i64 %or.2 254} 255 256