xref: /llvm-project/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll (revision 6206f5444fc0732e6495703c75a67f1f90f5b418) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 -amdgpu-long-branch-factor=0 -o - %s | FileCheck %s
3
4define amdgpu_kernel void @spill(ptr addrspace(1) %arg, i32 %cnd) #0 {
5; CHECK-LABEL: spill:
6; CHECK:       ; %bb.0: ; %entry
7; CHECK-NEXT:    s_load_dword s27, s[8:9], 0x2
8; CHECK-NEXT:    s_mov_b64 s[98:99], s[2:3]
9; CHECK-NEXT:    s_mov_b64 s[96:97], s[0:1]
10; CHECK-NEXT:    s_add_u32 s96, s96, s15
11; CHECK-NEXT:    s_addc_u32 s97, s97, 0
12; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
13; CHECK-NEXT:    s_cmp_eq_u32 s27, 0
14; CHECK-NEXT:    ;;#ASMSTART
15; CHECK-NEXT:    s_mov_b32 s0, 0
16; CHECK-NEXT:    ;;#ASMEND
17; CHECK-NEXT:    ;;#ASMSTART
18; CHECK-NEXT:    s_mov_b32 s1, 0
19; CHECK-NEXT:    ;;#ASMEND
20; CHECK-NEXT:    ;;#ASMSTART
21; CHECK-NEXT:    s_mov_b32 s2, 0
22; CHECK-NEXT:    ;;#ASMEND
23; CHECK-NEXT:    ;;#ASMSTART
24; CHECK-NEXT:    s_mov_b32 s3, 0
25; CHECK-NEXT:    ;;#ASMEND
26; CHECK-NEXT:    ;;#ASMSTART
27; CHECK-NEXT:    s_mov_b32 s4, 0
28; CHECK-NEXT:    ;;#ASMEND
29; CHECK-NEXT:    ;;#ASMSTART
30; CHECK-NEXT:    s_mov_b32 s5, 0
31; CHECK-NEXT:    ;;#ASMEND
32; CHECK-NEXT:    ;;#ASMSTART
33; CHECK-NEXT:    s_mov_b32 s6, 0
34; CHECK-NEXT:    ;;#ASMEND
35; CHECK-NEXT:    ;;#ASMSTART
36; CHECK-NEXT:    s_mov_b32 s7, 0
37; CHECK-NEXT:    ;;#ASMEND
38; CHECK-NEXT:    ;;#ASMSTART
39; CHECK-NEXT:    s_mov_b32 s8, 0
40; CHECK-NEXT:    ;;#ASMEND
41; CHECK-NEXT:    ;;#ASMSTART
42; CHECK-NEXT:    s_mov_b32 s9, 0
43; CHECK-NEXT:    ;;#ASMEND
44; CHECK-NEXT:    ;;#ASMSTART
45; CHECK-NEXT:    s_mov_b32 s10, 0
46; CHECK-NEXT:    ;;#ASMEND
47; CHECK-NEXT:    ;;#ASMSTART
48; CHECK-NEXT:    s_mov_b32 s11, 0
49; CHECK-NEXT:    ;;#ASMEND
50; CHECK-NEXT:    ;;#ASMSTART
51; CHECK-NEXT:    s_mov_b32 s12, 0
52; CHECK-NEXT:    ;;#ASMEND
53; CHECK-NEXT:    ;;#ASMSTART
54; CHECK-NEXT:    s_mov_b32 s13, 0
55; CHECK-NEXT:    ;;#ASMEND
56; CHECK-NEXT:    ;;#ASMSTART
57; CHECK-NEXT:    s_mov_b32 s14, 0
58; CHECK-NEXT:    ;;#ASMEND
59; CHECK-NEXT:    ;;#ASMSTART
60; CHECK-NEXT:    s_mov_b32 s15, 0
61; CHECK-NEXT:    ;;#ASMEND
62; CHECK-NEXT:    ;;#ASMSTART
63; CHECK-NEXT:    s_mov_b32 s16, 0
64; CHECK-NEXT:    ;;#ASMEND
65; CHECK-NEXT:    ;;#ASMSTART
66; CHECK-NEXT:    s_mov_b32 s17, 0
67; CHECK-NEXT:    ;;#ASMEND
68; CHECK-NEXT:    ;;#ASMSTART
69; CHECK-NEXT:    s_mov_b32 s18, 0
70; CHECK-NEXT:    ;;#ASMEND
71; CHECK-NEXT:    ;;#ASMSTART
72; CHECK-NEXT:    s_mov_b32 s19, 0
73; CHECK-NEXT:    ;;#ASMEND
74; CHECK-NEXT:    ;;#ASMSTART
75; CHECK-NEXT:    s_mov_b32 s20, 0
76; CHECK-NEXT:    ;;#ASMEND
77; CHECK-NEXT:    ;;#ASMSTART
78; CHECK-NEXT:    s_mov_b32 s21, 0
79; CHECK-NEXT:    ;;#ASMEND
80; CHECK-NEXT:    ;;#ASMSTART
81; CHECK-NEXT:    s_mov_b32 s22, 0
82; CHECK-NEXT:    ;;#ASMEND
83; CHECK-NEXT:    ;;#ASMSTART
84; CHECK-NEXT:    s_mov_b32 s23, 0
85; CHECK-NEXT:    ;;#ASMEND
86; CHECK-NEXT:    ;;#ASMSTART
87; CHECK-NEXT:    s_mov_b32 s24, 0
88; CHECK-NEXT:    ;;#ASMEND
89; CHECK-NEXT:    ;;#ASMSTART
90; CHECK-NEXT:    s_mov_b32 s25, 0
91; CHECK-NEXT:    ;;#ASMEND
92; CHECK-NEXT:    ;;#ASMSTART
93; CHECK-NEXT:    s_mov_b32 s26, 0
94; CHECK-NEXT:    ;;#ASMEND
95; CHECK-NEXT:    ;;#ASMSTART
96; CHECK-NEXT:    s_mov_b32 s27, 0
97; CHECK-NEXT:    ;;#ASMEND
98; CHECK-NEXT:    ;;#ASMSTART
99; CHECK-NEXT:    s_mov_b32 s28, 0
100; CHECK-NEXT:    ;;#ASMEND
101; CHECK-NEXT:    ;;#ASMSTART
102; CHECK-NEXT:    s_mov_b32 s29, 0
103; CHECK-NEXT:    ;;#ASMEND
104; CHECK-NEXT:    ;;#ASMSTART
105; CHECK-NEXT:    s_mov_b32 s30, 0
106; CHECK-NEXT:    ;;#ASMEND
107; CHECK-NEXT:    ;;#ASMSTART
108; CHECK-NEXT:    s_mov_b32 s31, 0
109; CHECK-NEXT:    ;;#ASMEND
110; CHECK-NEXT:    ;;#ASMSTART
111; CHECK-NEXT:    s_mov_b32 s32, 0
112; CHECK-NEXT:    ;;#ASMEND
113; CHECK-NEXT:    ;;#ASMSTART
114; CHECK-NEXT:    s_mov_b32 s33, 0
115; CHECK-NEXT:    ;;#ASMEND
116; CHECK-NEXT:    ;;#ASMSTART
117; CHECK-NEXT:    s_mov_b32 s34, 0
118; CHECK-NEXT:    ;;#ASMEND
119; CHECK-NEXT:    ;;#ASMSTART
120; CHECK-NEXT:    s_mov_b32 s35, 0
121; CHECK-NEXT:    ;;#ASMEND
122; CHECK-NEXT:    ;;#ASMSTART
123; CHECK-NEXT:    s_mov_b32 s36, 0
124; CHECK-NEXT:    ;;#ASMEND
125; CHECK-NEXT:    ;;#ASMSTART
126; CHECK-NEXT:    s_mov_b32 s37, 0
127; CHECK-NEXT:    ;;#ASMEND
128; CHECK-NEXT:    ;;#ASMSTART
129; CHECK-NEXT:    s_mov_b32 s38, 0
130; CHECK-NEXT:    ;;#ASMEND
131; CHECK-NEXT:    ;;#ASMSTART
132; CHECK-NEXT:    s_mov_b32 s39, 0
133; CHECK-NEXT:    ;;#ASMEND
134; CHECK-NEXT:    ;;#ASMSTART
135; CHECK-NEXT:    s_mov_b32 s40, 0
136; CHECK-NEXT:    ;;#ASMEND
137; CHECK-NEXT:    ;;#ASMSTART
138; CHECK-NEXT:    s_mov_b32 s41, 0
139; CHECK-NEXT:    ;;#ASMEND
140; CHECK-NEXT:    ;;#ASMSTART
141; CHECK-NEXT:    s_mov_b32 s42, 0
142; CHECK-NEXT:    ;;#ASMEND
143; CHECK-NEXT:    ;;#ASMSTART
144; CHECK-NEXT:    s_mov_b32 s43, 0
145; CHECK-NEXT:    ;;#ASMEND
146; CHECK-NEXT:    ;;#ASMSTART
147; CHECK-NEXT:    s_mov_b32 s44, 0
148; CHECK-NEXT:    ;;#ASMEND
149; CHECK-NEXT:    ;;#ASMSTART
150; CHECK-NEXT:    s_mov_b32 s45, 0
151; CHECK-NEXT:    ;;#ASMEND
152; CHECK-NEXT:    ;;#ASMSTART
153; CHECK-NEXT:    s_mov_b32 s46, 0
154; CHECK-NEXT:    ;;#ASMEND
155; CHECK-NEXT:    ;;#ASMSTART
156; CHECK-NEXT:    s_mov_b32 s47, 0
157; CHECK-NEXT:    ;;#ASMEND
158; CHECK-NEXT:    ;;#ASMSTART
159; CHECK-NEXT:    s_mov_b32 s48, 0
160; CHECK-NEXT:    ;;#ASMEND
161; CHECK-NEXT:    ;;#ASMSTART
162; CHECK-NEXT:    s_mov_b32 s49, 0
163; CHECK-NEXT:    ;;#ASMEND
164; CHECK-NEXT:    ;;#ASMSTART
165; CHECK-NEXT:    s_mov_b32 s50, 0
166; CHECK-NEXT:    ;;#ASMEND
167; CHECK-NEXT:    ;;#ASMSTART
168; CHECK-NEXT:    s_mov_b32 s51, 0
169; CHECK-NEXT:    ;;#ASMEND
170; CHECK-NEXT:    ;;#ASMSTART
171; CHECK-NEXT:    s_mov_b32 s52, 0
172; CHECK-NEXT:    ;;#ASMEND
173; CHECK-NEXT:    ;;#ASMSTART
174; CHECK-NEXT:    s_mov_b32 s53, 0
175; CHECK-NEXT:    ;;#ASMEND
176; CHECK-NEXT:    ;;#ASMSTART
177; CHECK-NEXT:    s_mov_b32 s54, 0
178; CHECK-NEXT:    ;;#ASMEND
179; CHECK-NEXT:    ;;#ASMSTART
180; CHECK-NEXT:    s_mov_b32 s55, 0
181; CHECK-NEXT:    ;;#ASMEND
182; CHECK-NEXT:    ;;#ASMSTART
183; CHECK-NEXT:    s_mov_b32 s56, 0
184; CHECK-NEXT:    ;;#ASMEND
185; CHECK-NEXT:    ;;#ASMSTART
186; CHECK-NEXT:    s_mov_b32 s57, 0
187; CHECK-NEXT:    ;;#ASMEND
188; CHECK-NEXT:    ;;#ASMSTART
189; CHECK-NEXT:    s_mov_b32 s58, 0
190; CHECK-NEXT:    ;;#ASMEND
191; CHECK-NEXT:    ;;#ASMSTART
192; CHECK-NEXT:    s_mov_b32 s59, 0
193; CHECK-NEXT:    ;;#ASMEND
194; CHECK-NEXT:    ;;#ASMSTART
195; CHECK-NEXT:    s_mov_b32 s60, 0
196; CHECK-NEXT:    ;;#ASMEND
197; CHECK-NEXT:    ;;#ASMSTART
198; CHECK-NEXT:    s_mov_b32 s61, 0
199; CHECK-NEXT:    ;;#ASMEND
200; CHECK-NEXT:    ;;#ASMSTART
201; CHECK-NEXT:    s_mov_b32 s62, 0
202; CHECK-NEXT:    ;;#ASMEND
203; CHECK-NEXT:    ;;#ASMSTART
204; CHECK-NEXT:    s_mov_b32 s63, 0
205; CHECK-NEXT:    ;;#ASMEND
206; CHECK-NEXT:    ;;#ASMSTART
207; CHECK-NEXT:    s_mov_b32 s64, 0
208; CHECK-NEXT:    ;;#ASMEND
209; CHECK-NEXT:    ;;#ASMSTART
210; CHECK-NEXT:    s_mov_b32 s65, 0
211; CHECK-NEXT:    ;;#ASMEND
212; CHECK-NEXT:    ;;#ASMSTART
213; CHECK-NEXT:    s_mov_b32 s66, 0
214; CHECK-NEXT:    ;;#ASMEND
215; CHECK-NEXT:    ;;#ASMSTART
216; CHECK-NEXT:    s_mov_b32 s67, 0
217; CHECK-NEXT:    ;;#ASMEND
218; CHECK-NEXT:    ;;#ASMSTART
219; CHECK-NEXT:    s_mov_b32 s68, 0
220; CHECK-NEXT:    ;;#ASMEND
221; CHECK-NEXT:    ;;#ASMSTART
222; CHECK-NEXT:    s_mov_b32 s69, 0
223; CHECK-NEXT:    ;;#ASMEND
224; CHECK-NEXT:    ;;#ASMSTART
225; CHECK-NEXT:    s_mov_b32 s70, 0
226; CHECK-NEXT:    ;;#ASMEND
227; CHECK-NEXT:    ;;#ASMSTART
228; CHECK-NEXT:    s_mov_b32 s71, 0
229; CHECK-NEXT:    ;;#ASMEND
230; CHECK-NEXT:    ;;#ASMSTART
231; CHECK-NEXT:    s_mov_b32 s72, 0
232; CHECK-NEXT:    ;;#ASMEND
233; CHECK-NEXT:    ;;#ASMSTART
234; CHECK-NEXT:    s_mov_b32 s73, 0
235; CHECK-NEXT:    ;;#ASMEND
236; CHECK-NEXT:    ;;#ASMSTART
237; CHECK-NEXT:    s_mov_b32 s74, 0
238; CHECK-NEXT:    ;;#ASMEND
239; CHECK-NEXT:    ;;#ASMSTART
240; CHECK-NEXT:    s_mov_b32 s75, 0
241; CHECK-NEXT:    ;;#ASMEND
242; CHECK-NEXT:    ;;#ASMSTART
243; CHECK-NEXT:    s_mov_b32 s76, 0
244; CHECK-NEXT:    ;;#ASMEND
245; CHECK-NEXT:    ;;#ASMSTART
246; CHECK-NEXT:    s_mov_b32 s77, 0
247; CHECK-NEXT:    ;;#ASMEND
248; CHECK-NEXT:    ;;#ASMSTART
249; CHECK-NEXT:    s_mov_b32 s78, 0
250; CHECK-NEXT:    ;;#ASMEND
251; CHECK-NEXT:    ;;#ASMSTART
252; CHECK-NEXT:    s_mov_b32 s79, 0
253; CHECK-NEXT:    ;;#ASMEND
254; CHECK-NEXT:    ;;#ASMSTART
255; CHECK-NEXT:    s_mov_b32 s80, 0
256; CHECK-NEXT:    ;;#ASMEND
257; CHECK-NEXT:    ;;#ASMSTART
258; CHECK-NEXT:    s_mov_b32 s81, 0
259; CHECK-NEXT:    ;;#ASMEND
260; CHECK-NEXT:    ;;#ASMSTART
261; CHECK-NEXT:    s_mov_b32 s82, 0
262; CHECK-NEXT:    ;;#ASMEND
263; CHECK-NEXT:    ;;#ASMSTART
264; CHECK-NEXT:    s_mov_b32 s83, 0
265; CHECK-NEXT:    ;;#ASMEND
266; CHECK-NEXT:    ;;#ASMSTART
267; CHECK-NEXT:    s_mov_b32 s84, 0
268; CHECK-NEXT:    ;;#ASMEND
269; CHECK-NEXT:    ;;#ASMSTART
270; CHECK-NEXT:    s_mov_b32 s85, 0
271; CHECK-NEXT:    ;;#ASMEND
272; CHECK-NEXT:    ;;#ASMSTART
273; CHECK-NEXT:    s_mov_b32 s86, 0
274; CHECK-NEXT:    ;;#ASMEND
275; CHECK-NEXT:    ;;#ASMSTART
276; CHECK-NEXT:    s_mov_b32 s87, 0
277; CHECK-NEXT:    ;;#ASMEND
278; CHECK-NEXT:    ;;#ASMSTART
279; CHECK-NEXT:    s_mov_b32 s88, 0
280; CHECK-NEXT:    ;;#ASMEND
281; CHECK-NEXT:    ;;#ASMSTART
282; CHECK-NEXT:    s_mov_b32 s89, 0
283; CHECK-NEXT:    ;;#ASMEND
284; CHECK-NEXT:    ;;#ASMSTART
285; CHECK-NEXT:    s_mov_b32 s90, 0
286; CHECK-NEXT:    ;;#ASMEND
287; CHECK-NEXT:    ;;#ASMSTART
288; CHECK-NEXT:    s_mov_b32 s91, 0
289; CHECK-NEXT:    ;;#ASMEND
290; CHECK-NEXT:    ;;#ASMSTART
291; CHECK-NEXT:    s_mov_b32 s92, 0
292; CHECK-NEXT:    ;;#ASMEND
293; CHECK-NEXT:    ;;#ASMSTART
294; CHECK-NEXT:    s_mov_b32 s93, 0
295; CHECK-NEXT:    ;;#ASMEND
296; CHECK-NEXT:    ;;#ASMSTART
297; CHECK-NEXT:    s_mov_b32 s94, 0
298; CHECK-NEXT:    ;;#ASMEND
299; CHECK-NEXT:    ;;#ASMSTART
300; CHECK-NEXT:    s_mov_b32 s95, 0
301; CHECK-NEXT:    ;;#ASMEND
302; CHECK-NEXT:    ;;#ASMSTART
303; CHECK-NEXT:    s_mov_b32 s96, 0
304; CHECK-NEXT:    ;;#ASMEND
305; CHECK-NEXT:    ;;#ASMSTART
306; CHECK-NEXT:    s_mov_b32 s97, 0
307; CHECK-NEXT:    ;;#ASMEND
308; CHECK-NEXT:    ;;#ASMSTART
309; CHECK-NEXT:    s_mov_b32 s98, 0
310; CHECK-NEXT:    ;;#ASMEND
311; CHECK-NEXT:    ;;#ASMSTART
312; CHECK-NEXT:    s_mov_b32 s99, 0
313; CHECK-NEXT:    ;;#ASMEND
314; CHECK-NEXT:    ;;#ASMSTART
315; CHECK-NEXT:    s_mov_b32 s100, 0
316; CHECK-NEXT:    ;;#ASMEND
317; CHECK-NEXT:    ;;#ASMSTART
318; CHECK-NEXT:    s_mov_b32 s101, 0
319; CHECK-NEXT:    ;;#ASMEND
320; CHECK-NEXT:    ;;#ASMSTART
321; CHECK-NEXT:    s_mov_b32 vcc_lo, 0
322; CHECK-NEXT:    ;;#ASMEND
323; CHECK-NEXT:    ;;#ASMSTART
324; CHECK-NEXT:    s_mov_b32 vcc_hi, 0
325; CHECK-NEXT:    ;;#ASMEND
326; CHECK-NEXT:    s_cbranch_scc0 .LBB0_1
327; CHECK-NEXT:  ; %bb.3: ; %entry
328; CHECK-NEXT:    s_not_b64 exec, exec
329; CHECK-NEXT:    buffer_store_dword v0, off, s[96:99], 0
330; CHECK-NEXT:    v_writelane_b32 v0, s0, 0
331; CHECK-NEXT:    v_writelane_b32 v0, s1, 1
332; CHECK-NEXT:    s_getpc_b64 s[0:1]
333; CHECK-NEXT:  .Lpost_getpc0:
334; CHECK-NEXT:    s_add_u32 s0, s0, (.LBB0_4-.Lpost_getpc0)&4294967295
335; CHECK-NEXT:    s_addc_u32 s1, s1, (.LBB0_4-.Lpost_getpc0)>>32
336; CHECK-NEXT:    s_setpc_b64 s[0:1]
337; CHECK-NEXT:  .LBB0_1: ; %bb2
338; CHECK-NEXT:    ;;#ASMSTART
339; CHECK-NEXT:    v_nop_e64
340; CHECK-NEXT:    v_nop_e64
341; CHECK-NEXT:    v_nop_e64
342; CHECK-NEXT:    v_nop_e64
343; CHECK-NEXT:    v_nop_e64
344; CHECK-NEXT:    v_nop_e64
345; CHECK-NEXT:    v_nop_e64
346; CHECK-NEXT:    v_nop_e64
347; CHECK-NEXT:    ;;#ASMEND
348; CHECK-NEXT:    s_branch .LBB0_2
349; CHECK-NEXT:  .LBB0_4: ; %bb3
350; CHECK-NEXT:    v_readlane_b32 s0, v0, 0
351; CHECK-NEXT:    v_readlane_b32 s1, v0, 1
352; CHECK-NEXT:    buffer_load_dword v0, off, s[96:99], 0
353; CHECK-NEXT:    s_not_b64 exec, exec
354; CHECK-NEXT:  .LBB0_2: ; %bb3
355; CHECK-NEXT:    ;;#ASMSTART
356; CHECK-NEXT:    ; reg use s0
357; CHECK-NEXT:    ;;#ASMEND
358; CHECK-NEXT:    ;;#ASMSTART
359; CHECK-NEXT:    ; reg use s1
360; CHECK-NEXT:    ;;#ASMEND
361; CHECK-NEXT:    ;;#ASMSTART
362; CHECK-NEXT:    ; reg use s2
363; CHECK-NEXT:    ;;#ASMEND
364; CHECK-NEXT:    ;;#ASMSTART
365; CHECK-NEXT:    ; reg use s3
366; CHECK-NEXT:    ;;#ASMEND
367; CHECK-NEXT:    ;;#ASMSTART
368; CHECK-NEXT:    ; reg use s4
369; CHECK-NEXT:    ;;#ASMEND
370; CHECK-NEXT:    ;;#ASMSTART
371; CHECK-NEXT:    ; reg use s5
372; CHECK-NEXT:    ;;#ASMEND
373; CHECK-NEXT:    ;;#ASMSTART
374; CHECK-NEXT:    ; reg use s6
375; CHECK-NEXT:    ;;#ASMEND
376; CHECK-NEXT:    ;;#ASMSTART
377; CHECK-NEXT:    ; reg use s7
378; CHECK-NEXT:    ;;#ASMEND
379; CHECK-NEXT:    ;;#ASMSTART
380; CHECK-NEXT:    ; reg use s8
381; CHECK-NEXT:    ;;#ASMEND
382; CHECK-NEXT:    ;;#ASMSTART
383; CHECK-NEXT:    ; reg use s9
384; CHECK-NEXT:    ;;#ASMEND
385; CHECK-NEXT:    ;;#ASMSTART
386; CHECK-NEXT:    ; reg use s10
387; CHECK-NEXT:    ;;#ASMEND
388; CHECK-NEXT:    ;;#ASMSTART
389; CHECK-NEXT:    ; reg use s11
390; CHECK-NEXT:    ;;#ASMEND
391; CHECK-NEXT:    ;;#ASMSTART
392; CHECK-NEXT:    ; reg use s12
393; CHECK-NEXT:    ;;#ASMEND
394; CHECK-NEXT:    ;;#ASMSTART
395; CHECK-NEXT:    ; reg use s13
396; CHECK-NEXT:    ;;#ASMEND
397; CHECK-NEXT:    ;;#ASMSTART
398; CHECK-NEXT:    ; reg use s14
399; CHECK-NEXT:    ;;#ASMEND
400; CHECK-NEXT:    ;;#ASMSTART
401; CHECK-NEXT:    ; reg use s15
402; CHECK-NEXT:    ;;#ASMEND
403; CHECK-NEXT:    ;;#ASMSTART
404; CHECK-NEXT:    ; reg use s16
405; CHECK-NEXT:    ;;#ASMEND
406; CHECK-NEXT:    ;;#ASMSTART
407; CHECK-NEXT:    ; reg use s17
408; CHECK-NEXT:    ;;#ASMEND
409; CHECK-NEXT:    ;;#ASMSTART
410; CHECK-NEXT:    ; reg use s18
411; CHECK-NEXT:    ;;#ASMEND
412; CHECK-NEXT:    ;;#ASMSTART
413; CHECK-NEXT:    ; reg use s19
414; CHECK-NEXT:    ;;#ASMEND
415; CHECK-NEXT:    ;;#ASMSTART
416; CHECK-NEXT:    ; reg use s20
417; CHECK-NEXT:    ;;#ASMEND
418; CHECK-NEXT:    ;;#ASMSTART
419; CHECK-NEXT:    ; reg use s21
420; CHECK-NEXT:    ;;#ASMEND
421; CHECK-NEXT:    ;;#ASMSTART
422; CHECK-NEXT:    ; reg use s22
423; CHECK-NEXT:    ;;#ASMEND
424; CHECK-NEXT:    ;;#ASMSTART
425; CHECK-NEXT:    ; reg use s23
426; CHECK-NEXT:    ;;#ASMEND
427; CHECK-NEXT:    ;;#ASMSTART
428; CHECK-NEXT:    ; reg use s24
429; CHECK-NEXT:    ;;#ASMEND
430; CHECK-NEXT:    ;;#ASMSTART
431; CHECK-NEXT:    ; reg use s25
432; CHECK-NEXT:    ;;#ASMEND
433; CHECK-NEXT:    ;;#ASMSTART
434; CHECK-NEXT:    ; reg use s26
435; CHECK-NEXT:    ;;#ASMEND
436; CHECK-NEXT:    ;;#ASMSTART
437; CHECK-NEXT:    ; reg use s27
438; CHECK-NEXT:    ;;#ASMEND
439; CHECK-NEXT:    ;;#ASMSTART
440; CHECK-NEXT:    ; reg use s28
441; CHECK-NEXT:    ;;#ASMEND
442; CHECK-NEXT:    ;;#ASMSTART
443; CHECK-NEXT:    ; reg use s29
444; CHECK-NEXT:    ;;#ASMEND
445; CHECK-NEXT:    ;;#ASMSTART
446; CHECK-NEXT:    ; reg use s30
447; CHECK-NEXT:    ;;#ASMEND
448; CHECK-NEXT:    ;;#ASMSTART
449; CHECK-NEXT:    ; reg use s31
450; CHECK-NEXT:    ;;#ASMEND
451; CHECK-NEXT:    ;;#ASMSTART
452; CHECK-NEXT:    ; reg use s32
453; CHECK-NEXT:    ;;#ASMEND
454; CHECK-NEXT:    ;;#ASMSTART
455; CHECK-NEXT:    ; reg use s33
456; CHECK-NEXT:    ;;#ASMEND
457; CHECK-NEXT:    ;;#ASMSTART
458; CHECK-NEXT:    ; reg use s34
459; CHECK-NEXT:    ;;#ASMEND
460; CHECK-NEXT:    ;;#ASMSTART
461; CHECK-NEXT:    ; reg use s35
462; CHECK-NEXT:    ;;#ASMEND
463; CHECK-NEXT:    ;;#ASMSTART
464; CHECK-NEXT:    ; reg use s36
465; CHECK-NEXT:    ;;#ASMEND
466; CHECK-NEXT:    ;;#ASMSTART
467; CHECK-NEXT:    ; reg use s37
468; CHECK-NEXT:    ;;#ASMEND
469; CHECK-NEXT:    ;;#ASMSTART
470; CHECK-NEXT:    ; reg use s38
471; CHECK-NEXT:    ;;#ASMEND
472; CHECK-NEXT:    ;;#ASMSTART
473; CHECK-NEXT:    ; reg use s39
474; CHECK-NEXT:    ;;#ASMEND
475; CHECK-NEXT:    ;;#ASMSTART
476; CHECK-NEXT:    ; reg use s40
477; CHECK-NEXT:    ;;#ASMEND
478; CHECK-NEXT:    ;;#ASMSTART
479; CHECK-NEXT:    ; reg use s41
480; CHECK-NEXT:    ;;#ASMEND
481; CHECK-NEXT:    ;;#ASMSTART
482; CHECK-NEXT:    ; reg use s42
483; CHECK-NEXT:    ;;#ASMEND
484; CHECK-NEXT:    ;;#ASMSTART
485; CHECK-NEXT:    ; reg use s43
486; CHECK-NEXT:    ;;#ASMEND
487; CHECK-NEXT:    ;;#ASMSTART
488; CHECK-NEXT:    ; reg use s44
489; CHECK-NEXT:    ;;#ASMEND
490; CHECK-NEXT:    ;;#ASMSTART
491; CHECK-NEXT:    ; reg use s45
492; CHECK-NEXT:    ;;#ASMEND
493; CHECK-NEXT:    ;;#ASMSTART
494; CHECK-NEXT:    ; reg use s46
495; CHECK-NEXT:    ;;#ASMEND
496; CHECK-NEXT:    ;;#ASMSTART
497; CHECK-NEXT:    ; reg use s47
498; CHECK-NEXT:    ;;#ASMEND
499; CHECK-NEXT:    ;;#ASMSTART
500; CHECK-NEXT:    ; reg use s48
501; CHECK-NEXT:    ;;#ASMEND
502; CHECK-NEXT:    ;;#ASMSTART
503; CHECK-NEXT:    ; reg use s49
504; CHECK-NEXT:    ;;#ASMEND
505; CHECK-NEXT:    ;;#ASMSTART
506; CHECK-NEXT:    ; reg use s50
507; CHECK-NEXT:    ;;#ASMEND
508; CHECK-NEXT:    ;;#ASMSTART
509; CHECK-NEXT:    ; reg use s51
510; CHECK-NEXT:    ;;#ASMEND
511; CHECK-NEXT:    ;;#ASMSTART
512; CHECK-NEXT:    ; reg use s52
513; CHECK-NEXT:    ;;#ASMEND
514; CHECK-NEXT:    ;;#ASMSTART
515; CHECK-NEXT:    ; reg use s53
516; CHECK-NEXT:    ;;#ASMEND
517; CHECK-NEXT:    ;;#ASMSTART
518; CHECK-NEXT:    ; reg use s54
519; CHECK-NEXT:    ;;#ASMEND
520; CHECK-NEXT:    ;;#ASMSTART
521; CHECK-NEXT:    ; reg use s55
522; CHECK-NEXT:    ;;#ASMEND
523; CHECK-NEXT:    ;;#ASMSTART
524; CHECK-NEXT:    ; reg use s56
525; CHECK-NEXT:    ;;#ASMEND
526; CHECK-NEXT:    ;;#ASMSTART
527; CHECK-NEXT:    ; reg use s57
528; CHECK-NEXT:    ;;#ASMEND
529; CHECK-NEXT:    ;;#ASMSTART
530; CHECK-NEXT:    ; reg use s58
531; CHECK-NEXT:    ;;#ASMEND
532; CHECK-NEXT:    ;;#ASMSTART
533; CHECK-NEXT:    ; reg use s59
534; CHECK-NEXT:    ;;#ASMEND
535; CHECK-NEXT:    ;;#ASMSTART
536; CHECK-NEXT:    ; reg use s60
537; CHECK-NEXT:    ;;#ASMEND
538; CHECK-NEXT:    ;;#ASMSTART
539; CHECK-NEXT:    ; reg use s61
540; CHECK-NEXT:    ;;#ASMEND
541; CHECK-NEXT:    ;;#ASMSTART
542; CHECK-NEXT:    ; reg use s62
543; CHECK-NEXT:    ;;#ASMEND
544; CHECK-NEXT:    ;;#ASMSTART
545; CHECK-NEXT:    ; reg use s63
546; CHECK-NEXT:    ;;#ASMEND
547; CHECK-NEXT:    ;;#ASMSTART
548; CHECK-NEXT:    ; reg use s64
549; CHECK-NEXT:    ;;#ASMEND
550; CHECK-NEXT:    ;;#ASMSTART
551; CHECK-NEXT:    ; reg use s65
552; CHECK-NEXT:    ;;#ASMEND
553; CHECK-NEXT:    ;;#ASMSTART
554; CHECK-NEXT:    ; reg use s66
555; CHECK-NEXT:    ;;#ASMEND
556; CHECK-NEXT:    ;;#ASMSTART
557; CHECK-NEXT:    ; reg use s67
558; CHECK-NEXT:    ;;#ASMEND
559; CHECK-NEXT:    ;;#ASMSTART
560; CHECK-NEXT:    ; reg use s68
561; CHECK-NEXT:    ;;#ASMEND
562; CHECK-NEXT:    ;;#ASMSTART
563; CHECK-NEXT:    ; reg use s69
564; CHECK-NEXT:    ;;#ASMEND
565; CHECK-NEXT:    ;;#ASMSTART
566; CHECK-NEXT:    ; reg use s70
567; CHECK-NEXT:    ;;#ASMEND
568; CHECK-NEXT:    ;;#ASMSTART
569; CHECK-NEXT:    ; reg use s71
570; CHECK-NEXT:    ;;#ASMEND
571; CHECK-NEXT:    ;;#ASMSTART
572; CHECK-NEXT:    ; reg use s72
573; CHECK-NEXT:    ;;#ASMEND
574; CHECK-NEXT:    ;;#ASMSTART
575; CHECK-NEXT:    ; reg use s73
576; CHECK-NEXT:    ;;#ASMEND
577; CHECK-NEXT:    ;;#ASMSTART
578; CHECK-NEXT:    ; reg use s74
579; CHECK-NEXT:    ;;#ASMEND
580; CHECK-NEXT:    ;;#ASMSTART
581; CHECK-NEXT:    ; reg use s75
582; CHECK-NEXT:    ;;#ASMEND
583; CHECK-NEXT:    ;;#ASMSTART
584; CHECK-NEXT:    ; reg use s76
585; CHECK-NEXT:    ;;#ASMEND
586; CHECK-NEXT:    ;;#ASMSTART
587; CHECK-NEXT:    ; reg use s77
588; CHECK-NEXT:    ;;#ASMEND
589; CHECK-NEXT:    ;;#ASMSTART
590; CHECK-NEXT:    ; reg use s78
591; CHECK-NEXT:    ;;#ASMEND
592; CHECK-NEXT:    ;;#ASMSTART
593; CHECK-NEXT:    ; reg use s79
594; CHECK-NEXT:    ;;#ASMEND
595; CHECK-NEXT:    ;;#ASMSTART
596; CHECK-NEXT:    ; reg use s80
597; CHECK-NEXT:    ;;#ASMEND
598; CHECK-NEXT:    ;;#ASMSTART
599; CHECK-NEXT:    ; reg use s81
600; CHECK-NEXT:    ;;#ASMEND
601; CHECK-NEXT:    ;;#ASMSTART
602; CHECK-NEXT:    ; reg use s82
603; CHECK-NEXT:    ;;#ASMEND
604; CHECK-NEXT:    ;;#ASMSTART
605; CHECK-NEXT:    ; reg use s83
606; CHECK-NEXT:    ;;#ASMEND
607; CHECK-NEXT:    ;;#ASMSTART
608; CHECK-NEXT:    ; reg use s84
609; CHECK-NEXT:    ;;#ASMEND
610; CHECK-NEXT:    ;;#ASMSTART
611; CHECK-NEXT:    ; reg use s85
612; CHECK-NEXT:    ;;#ASMEND
613; CHECK-NEXT:    ;;#ASMSTART
614; CHECK-NEXT:    ; reg use s86
615; CHECK-NEXT:    ;;#ASMEND
616; CHECK-NEXT:    ;;#ASMSTART
617; CHECK-NEXT:    ; reg use s87
618; CHECK-NEXT:    ;;#ASMEND
619; CHECK-NEXT:    ;;#ASMSTART
620; CHECK-NEXT:    ; reg use s88
621; CHECK-NEXT:    ;;#ASMEND
622; CHECK-NEXT:    ;;#ASMSTART
623; CHECK-NEXT:    ; reg use s89
624; CHECK-NEXT:    ;;#ASMEND
625; CHECK-NEXT:    ;;#ASMSTART
626; CHECK-NEXT:    ; reg use s90
627; CHECK-NEXT:    ;;#ASMEND
628; CHECK-NEXT:    ;;#ASMSTART
629; CHECK-NEXT:    ; reg use s91
630; CHECK-NEXT:    ;;#ASMEND
631; CHECK-NEXT:    ;;#ASMSTART
632; CHECK-NEXT:    ; reg use s92
633; CHECK-NEXT:    ;;#ASMEND
634; CHECK-NEXT:    ;;#ASMSTART
635; CHECK-NEXT:    ; reg use s93
636; CHECK-NEXT:    ;;#ASMEND
637; CHECK-NEXT:    ;;#ASMSTART
638; CHECK-NEXT:    ; reg use s94
639; CHECK-NEXT:    ;;#ASMEND
640; CHECK-NEXT:    ;;#ASMSTART
641; CHECK-NEXT:    ; reg use s95
642; CHECK-NEXT:    ;;#ASMEND
643; CHECK-NEXT:    ;;#ASMSTART
644; CHECK-NEXT:    ; reg use s96
645; CHECK-NEXT:    ;;#ASMEND
646; CHECK-NEXT:    ;;#ASMSTART
647; CHECK-NEXT:    ; reg use s97
648; CHECK-NEXT:    ;;#ASMEND
649; CHECK-NEXT:    ;;#ASMSTART
650; CHECK-NEXT:    ; reg use s98
651; CHECK-NEXT:    ;;#ASMEND
652; CHECK-NEXT:    ;;#ASMSTART
653; CHECK-NEXT:    ; reg use s99
654; CHECK-NEXT:    ;;#ASMEND
655; CHECK-NEXT:    ;;#ASMSTART
656; CHECK-NEXT:    ; reg use s100
657; CHECK-NEXT:    ;;#ASMEND
658; CHECK-NEXT:    ;;#ASMSTART
659; CHECK-NEXT:    ; reg use s101
660; CHECK-NEXT:    ;;#ASMEND
661; CHECK-NEXT:    ;;#ASMSTART
662; CHECK-NEXT:    ; reg use vcc_lo
663; CHECK-NEXT:    ;;#ASMEND
664; CHECK-NEXT:    ;;#ASMSTART
665; CHECK-NEXT:    ; reg use vcc_hi
666; CHECK-NEXT:    ;;#ASMEND
667; CHECK-NEXT:    s_endpgm
668entry:
669  %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
670  %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
671  %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
672  %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
673  %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
674  %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
675  %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
676  %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
677  %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
678  %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
679  %sgpr10 = tail call i32 asm sideeffect "s_mov_b32 s10, 0", "={s10}"() #0
680  %sgpr11 = tail call i32 asm sideeffect "s_mov_b32 s11, 0", "={s11}"() #0
681  %sgpr12 = tail call i32 asm sideeffect "s_mov_b32 s12, 0", "={s12}"() #0
682  %sgpr13 = tail call i32 asm sideeffect "s_mov_b32 s13, 0", "={s13}"() #0
683  %sgpr14 = tail call i32 asm sideeffect "s_mov_b32 s14, 0", "={s14}"() #0
684  %sgpr15 = tail call i32 asm sideeffect "s_mov_b32 s15, 0", "={s15}"() #0
685  %sgpr16 = tail call i32 asm sideeffect "s_mov_b32 s16, 0", "={s16}"() #0
686  %sgpr17 = tail call i32 asm sideeffect "s_mov_b32 s17, 0", "={s17}"() #0
687  %sgpr18 = tail call i32 asm sideeffect "s_mov_b32 s18, 0", "={s18}"() #0
688  %sgpr19 = tail call i32 asm sideeffect "s_mov_b32 s19, 0", "={s19}"() #0
689  %sgpr20 = tail call i32 asm sideeffect "s_mov_b32 s20, 0", "={s20}"() #0
690  %sgpr21 = tail call i32 asm sideeffect "s_mov_b32 s21, 0", "={s21}"() #0
691  %sgpr22 = tail call i32 asm sideeffect "s_mov_b32 s22, 0", "={s22}"() #0
692  %sgpr23 = tail call i32 asm sideeffect "s_mov_b32 s23, 0", "={s23}"() #0
693  %sgpr24 = tail call i32 asm sideeffect "s_mov_b32 s24, 0", "={s24}"() #0
694  %sgpr25 = tail call i32 asm sideeffect "s_mov_b32 s25, 0", "={s25}"() #0
695  %sgpr26 = tail call i32 asm sideeffect "s_mov_b32 s26, 0", "={s26}"() #0
696  %sgpr27 = tail call i32 asm sideeffect "s_mov_b32 s27, 0", "={s27}"() #0
697  %sgpr28 = tail call i32 asm sideeffect "s_mov_b32 s28, 0", "={s28}"() #0
698  %sgpr29 = tail call i32 asm sideeffect "s_mov_b32 s29, 0", "={s29}"() #0
699  %sgpr30 = tail call i32 asm sideeffect "s_mov_b32 s30, 0", "={s30}"() #0
700  %sgpr31 = tail call i32 asm sideeffect "s_mov_b32 s31, 0", "={s31}"() #0
701  %sgpr32 = tail call i32 asm sideeffect "s_mov_b32 s32, 0", "={s32}"() #0
702  %sgpr33 = tail call i32 asm sideeffect "s_mov_b32 s33, 0", "={s33}"() #0
703  %sgpr34 = tail call i32 asm sideeffect "s_mov_b32 s34, 0", "={s34}"() #0
704  %sgpr35 = tail call i32 asm sideeffect "s_mov_b32 s35, 0", "={s35}"() #0
705  %sgpr36 = tail call i32 asm sideeffect "s_mov_b32 s36, 0", "={s36}"() #0
706  %sgpr37 = tail call i32 asm sideeffect "s_mov_b32 s37, 0", "={s37}"() #0
707  %sgpr38 = tail call i32 asm sideeffect "s_mov_b32 s38, 0", "={s38}"() #0
708  %sgpr39 = tail call i32 asm sideeffect "s_mov_b32 s39, 0", "={s39}"() #0
709  %sgpr40 = tail call i32 asm sideeffect "s_mov_b32 s40, 0", "={s40}"() #0
710  %sgpr41 = tail call i32 asm sideeffect "s_mov_b32 s41, 0", "={s41}"() #0
711  %sgpr42 = tail call i32 asm sideeffect "s_mov_b32 s42, 0", "={s42}"() #0
712  %sgpr43 = tail call i32 asm sideeffect "s_mov_b32 s43, 0", "={s43}"() #0
713  %sgpr44 = tail call i32 asm sideeffect "s_mov_b32 s44, 0", "={s44}"() #0
714  %sgpr45 = tail call i32 asm sideeffect "s_mov_b32 s45, 0", "={s45}"() #0
715  %sgpr46 = tail call i32 asm sideeffect "s_mov_b32 s46, 0", "={s46}"() #0
716  %sgpr47 = tail call i32 asm sideeffect "s_mov_b32 s47, 0", "={s47}"() #0
717  %sgpr48 = tail call i32 asm sideeffect "s_mov_b32 s48, 0", "={s48}"() #0
718  %sgpr49 = tail call i32 asm sideeffect "s_mov_b32 s49, 0", "={s49}"() #0
719  %sgpr50 = tail call i32 asm sideeffect "s_mov_b32 s50, 0", "={s50}"() #0
720  %sgpr51 = tail call i32 asm sideeffect "s_mov_b32 s51, 0", "={s51}"() #0
721  %sgpr52 = tail call i32 asm sideeffect "s_mov_b32 s52, 0", "={s52}"() #0
722  %sgpr53 = tail call i32 asm sideeffect "s_mov_b32 s53, 0", "={s53}"() #0
723  %sgpr54 = tail call i32 asm sideeffect "s_mov_b32 s54, 0", "={s54}"() #0
724  %sgpr55 = tail call i32 asm sideeffect "s_mov_b32 s55, 0", "={s55}"() #0
725  %sgpr56 = tail call i32 asm sideeffect "s_mov_b32 s56, 0", "={s56}"() #0
726  %sgpr57 = tail call i32 asm sideeffect "s_mov_b32 s57, 0", "={s57}"() #0
727  %sgpr58 = tail call i32 asm sideeffect "s_mov_b32 s58, 0", "={s58}"() #0
728  %sgpr59 = tail call i32 asm sideeffect "s_mov_b32 s59, 0", "={s59}"() #0
729  %sgpr60 = tail call i32 asm sideeffect "s_mov_b32 s60, 0", "={s60}"() #0
730  %sgpr61 = tail call i32 asm sideeffect "s_mov_b32 s61, 0", "={s61}"() #0
731  %sgpr62 = tail call i32 asm sideeffect "s_mov_b32 s62, 0", "={s62}"() #0
732  %sgpr63 = tail call i32 asm sideeffect "s_mov_b32 s63, 0", "={s63}"() #0
733  %sgpr64 = tail call i32 asm sideeffect "s_mov_b32 s64, 0", "={s64}"() #0
734  %sgpr65 = tail call i32 asm sideeffect "s_mov_b32 s65, 0", "={s65}"() #0
735  %sgpr66 = tail call i32 asm sideeffect "s_mov_b32 s66, 0", "={s66}"() #0
736  %sgpr67 = tail call i32 asm sideeffect "s_mov_b32 s67, 0", "={s67}"() #0
737  %sgpr68 = tail call i32 asm sideeffect "s_mov_b32 s68, 0", "={s68}"() #0
738  %sgpr69 = tail call i32 asm sideeffect "s_mov_b32 s69, 0", "={s69}"() #0
739  %sgpr70 = tail call i32 asm sideeffect "s_mov_b32 s70, 0", "={s70}"() #0
740  %sgpr71 = tail call i32 asm sideeffect "s_mov_b32 s71, 0", "={s71}"() #0
741  %sgpr72 = tail call i32 asm sideeffect "s_mov_b32 s72, 0", "={s72}"() #0
742  %sgpr73 = tail call i32 asm sideeffect "s_mov_b32 s73, 0", "={s73}"() #0
743  %sgpr74 = tail call i32 asm sideeffect "s_mov_b32 s74, 0", "={s74}"() #0
744  %sgpr75 = tail call i32 asm sideeffect "s_mov_b32 s75, 0", "={s75}"() #0
745  %sgpr76 = tail call i32 asm sideeffect "s_mov_b32 s76, 0", "={s76}"() #0
746  %sgpr77 = tail call i32 asm sideeffect "s_mov_b32 s77, 0", "={s77}"() #0
747  %sgpr78 = tail call i32 asm sideeffect "s_mov_b32 s78, 0", "={s78}"() #0
748  %sgpr79 = tail call i32 asm sideeffect "s_mov_b32 s79, 0", "={s79}"() #0
749  %sgpr80 = tail call i32 asm sideeffect "s_mov_b32 s80, 0", "={s80}"() #0
750  %sgpr81 = tail call i32 asm sideeffect "s_mov_b32 s81, 0", "={s81}"() #0
751  %sgpr82 = tail call i32 asm sideeffect "s_mov_b32 s82, 0", "={s82}"() #0
752  %sgpr83 = tail call i32 asm sideeffect "s_mov_b32 s83, 0", "={s83}"() #0
753  %sgpr84 = tail call i32 asm sideeffect "s_mov_b32 s84, 0", "={s84}"() #0
754  %sgpr85 = tail call i32 asm sideeffect "s_mov_b32 s85, 0", "={s85}"() #0
755  %sgpr86 = tail call i32 asm sideeffect "s_mov_b32 s86, 0", "={s86}"() #0
756  %sgpr87 = tail call i32 asm sideeffect "s_mov_b32 s87, 0", "={s87}"() #0
757  %sgpr88 = tail call i32 asm sideeffect "s_mov_b32 s88, 0", "={s88}"() #0
758  %sgpr89 = tail call i32 asm sideeffect "s_mov_b32 s89, 0", "={s89}"() #0
759  %sgpr90 = tail call i32 asm sideeffect "s_mov_b32 s90, 0", "={s90}"() #0
760  %sgpr91 = tail call i32 asm sideeffect "s_mov_b32 s91, 0", "={s91}"() #0
761  %sgpr92 = tail call i32 asm sideeffect "s_mov_b32 s92, 0", "={s92}"() #0
762  %sgpr93 = tail call i32 asm sideeffect "s_mov_b32 s93, 0", "={s93}"() #0
763  %sgpr94 = tail call i32 asm sideeffect "s_mov_b32 s94, 0", "={s94}"() #0
764  %sgpr95 = tail call i32 asm sideeffect "s_mov_b32 s95, 0", "={s95}"() #0
765  %sgpr96 = tail call i32 asm sideeffect "s_mov_b32 s96, 0", "={s96}"() #0
766  %sgpr97 = tail call i32 asm sideeffect "s_mov_b32 s97, 0", "={s97}"() #0
767  %sgpr98 = tail call i32 asm sideeffect "s_mov_b32 s98, 0", "={s98}"() #0
768  %sgpr99 = tail call i32 asm sideeffect "s_mov_b32 s99, 0", "={s99}"() #0
769  %sgpr100 = tail call i32 asm sideeffect "s_mov_b32 s100, 0", "={s100}"() #0
770  %sgpr101 = tail call i32 asm sideeffect "s_mov_b32 s101, 0", "={s101}"() #0
771  %vcc_lo = tail call i32 asm sideeffect "s_mov_b32 $0, 0", "={vcc_lo}"() #0
772  %vcc_hi = tail call i32 asm sideeffect "s_mov_b32 $0, 0", "={vcc_hi}"() #0
773  %cmp = icmp eq i32 %cnd, 0
774  br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
775
776bb2: ; 68 bytes
777  ; 64 byte asm
778  call void asm sideeffect
779   "v_nop_e64
780    v_nop_e64
781    v_nop_e64
782    v_nop_e64
783    v_nop_e64
784    v_nop_e64
785    v_nop_e64
786    v_nop_e64",""() #0
787  br label %bb3
788
789bb3:
790  tail call void asm sideeffect "; reg use $0", "{s0}"(i32 %sgpr0) #0
791  tail call void asm sideeffect "; reg use $0", "{s1}"(i32 %sgpr1) #0
792  tail call void asm sideeffect "; reg use $0", "{s2}"(i32 %sgpr2) #0
793  tail call void asm sideeffect "; reg use $0", "{s3}"(i32 %sgpr3) #0
794  tail call void asm sideeffect "; reg use $0", "{s4}"(i32 %sgpr4) #0
795  tail call void asm sideeffect "; reg use $0", "{s5}"(i32 %sgpr5) #0
796  tail call void asm sideeffect "; reg use $0", "{s6}"(i32 %sgpr6) #0
797  tail call void asm sideeffect "; reg use $0", "{s7}"(i32 %sgpr7) #0
798  tail call void asm sideeffect "; reg use $0", "{s8}"(i32 %sgpr8) #0
799  tail call void asm sideeffect "; reg use $0", "{s9}"(i32 %sgpr9) #0
800  tail call void asm sideeffect "; reg use $0", "{s10}"(i32 %sgpr10) #0
801  tail call void asm sideeffect "; reg use $0", "{s11}"(i32 %sgpr11) #0
802  tail call void asm sideeffect "; reg use $0", "{s12}"(i32 %sgpr12) #0
803  tail call void asm sideeffect "; reg use $0", "{s13}"(i32 %sgpr13) #0
804  tail call void asm sideeffect "; reg use $0", "{s14}"(i32 %sgpr14) #0
805  tail call void asm sideeffect "; reg use $0", "{s15}"(i32 %sgpr15) #0
806  tail call void asm sideeffect "; reg use $0", "{s16}"(i32 %sgpr16) #0
807  tail call void asm sideeffect "; reg use $0", "{s17}"(i32 %sgpr17) #0
808  tail call void asm sideeffect "; reg use $0", "{s18}"(i32 %sgpr18) #0
809  tail call void asm sideeffect "; reg use $0", "{s19}"(i32 %sgpr19) #0
810  tail call void asm sideeffect "; reg use $0", "{s20}"(i32 %sgpr20) #0
811  tail call void asm sideeffect "; reg use $0", "{s21}"(i32 %sgpr21) #0
812  tail call void asm sideeffect "; reg use $0", "{s22}"(i32 %sgpr22) #0
813  tail call void asm sideeffect "; reg use $0", "{s23}"(i32 %sgpr23) #0
814  tail call void asm sideeffect "; reg use $0", "{s24}"(i32 %sgpr24) #0
815  tail call void asm sideeffect "; reg use $0", "{s25}"(i32 %sgpr25) #0
816  tail call void asm sideeffect "; reg use $0", "{s26}"(i32 %sgpr26) #0
817  tail call void asm sideeffect "; reg use $0", "{s27}"(i32 %sgpr27) #0
818  tail call void asm sideeffect "; reg use $0", "{s28}"(i32 %sgpr28) #0
819  tail call void asm sideeffect "; reg use $0", "{s29}"(i32 %sgpr29) #0
820  tail call void asm sideeffect "; reg use $0", "{s30}"(i32 %sgpr30) #0
821  tail call void asm sideeffect "; reg use $0", "{s31}"(i32 %sgpr31) #0
822  tail call void asm sideeffect "; reg use $0", "{s32}"(i32 %sgpr32) #0
823  tail call void asm sideeffect "; reg use $0", "{s33}"(i32 %sgpr33) #0
824  tail call void asm sideeffect "; reg use $0", "{s34}"(i32 %sgpr34) #0
825  tail call void asm sideeffect "; reg use $0", "{s35}"(i32 %sgpr35) #0
826  tail call void asm sideeffect "; reg use $0", "{s36}"(i32 %sgpr36) #0
827  tail call void asm sideeffect "; reg use $0", "{s37}"(i32 %sgpr37) #0
828  tail call void asm sideeffect "; reg use $0", "{s38}"(i32 %sgpr38) #0
829  tail call void asm sideeffect "; reg use $0", "{s39}"(i32 %sgpr39) #0
830  tail call void asm sideeffect "; reg use $0", "{s40}"(i32 %sgpr40) #0
831  tail call void asm sideeffect "; reg use $0", "{s41}"(i32 %sgpr41) #0
832  tail call void asm sideeffect "; reg use $0", "{s42}"(i32 %sgpr42) #0
833  tail call void asm sideeffect "; reg use $0", "{s43}"(i32 %sgpr43) #0
834  tail call void asm sideeffect "; reg use $0", "{s44}"(i32 %sgpr44) #0
835  tail call void asm sideeffect "; reg use $0", "{s45}"(i32 %sgpr45) #0
836  tail call void asm sideeffect "; reg use $0", "{s46}"(i32 %sgpr46) #0
837  tail call void asm sideeffect "; reg use $0", "{s47}"(i32 %sgpr47) #0
838  tail call void asm sideeffect "; reg use $0", "{s48}"(i32 %sgpr48) #0
839  tail call void asm sideeffect "; reg use $0", "{s49}"(i32 %sgpr49) #0
840  tail call void asm sideeffect "; reg use $0", "{s50}"(i32 %sgpr50) #0
841  tail call void asm sideeffect "; reg use $0", "{s51}"(i32 %sgpr51) #0
842  tail call void asm sideeffect "; reg use $0", "{s52}"(i32 %sgpr52) #0
843  tail call void asm sideeffect "; reg use $0", "{s53}"(i32 %sgpr53) #0
844  tail call void asm sideeffect "; reg use $0", "{s54}"(i32 %sgpr54) #0
845  tail call void asm sideeffect "; reg use $0", "{s55}"(i32 %sgpr55) #0
846  tail call void asm sideeffect "; reg use $0", "{s56}"(i32 %sgpr56) #0
847  tail call void asm sideeffect "; reg use $0", "{s57}"(i32 %sgpr57) #0
848  tail call void asm sideeffect "; reg use $0", "{s58}"(i32 %sgpr58) #0
849  tail call void asm sideeffect "; reg use $0", "{s59}"(i32 %sgpr59) #0
850  tail call void asm sideeffect "; reg use $0", "{s60}"(i32 %sgpr60) #0
851  tail call void asm sideeffect "; reg use $0", "{s61}"(i32 %sgpr61) #0
852  tail call void asm sideeffect "; reg use $0", "{s62}"(i32 %sgpr62) #0
853  tail call void asm sideeffect "; reg use $0", "{s63}"(i32 %sgpr63) #0
854  tail call void asm sideeffect "; reg use $0", "{s64}"(i32 %sgpr64) #0
855  tail call void asm sideeffect "; reg use $0", "{s65}"(i32 %sgpr65) #0
856  tail call void asm sideeffect "; reg use $0", "{s66}"(i32 %sgpr66) #0
857  tail call void asm sideeffect "; reg use $0", "{s67}"(i32 %sgpr67) #0
858  tail call void asm sideeffect "; reg use $0", "{s68}"(i32 %sgpr68) #0
859  tail call void asm sideeffect "; reg use $0", "{s69}"(i32 %sgpr69) #0
860  tail call void asm sideeffect "; reg use $0", "{s70}"(i32 %sgpr70) #0
861  tail call void asm sideeffect "; reg use $0", "{s71}"(i32 %sgpr71) #0
862  tail call void asm sideeffect "; reg use $0", "{s72}"(i32 %sgpr72) #0
863  tail call void asm sideeffect "; reg use $0", "{s73}"(i32 %sgpr73) #0
864  tail call void asm sideeffect "; reg use $0", "{s74}"(i32 %sgpr74) #0
865  tail call void asm sideeffect "; reg use $0", "{s75}"(i32 %sgpr75) #0
866  tail call void asm sideeffect "; reg use $0", "{s76}"(i32 %sgpr76) #0
867  tail call void asm sideeffect "; reg use $0", "{s77}"(i32 %sgpr77) #0
868  tail call void asm sideeffect "; reg use $0", "{s78}"(i32 %sgpr78) #0
869  tail call void asm sideeffect "; reg use $0", "{s79}"(i32 %sgpr79) #0
870  tail call void asm sideeffect "; reg use $0", "{s80}"(i32 %sgpr80) #0
871  tail call void asm sideeffect "; reg use $0", "{s81}"(i32 %sgpr81) #0
872  tail call void asm sideeffect "; reg use $0", "{s82}"(i32 %sgpr82) #0
873  tail call void asm sideeffect "; reg use $0", "{s83}"(i32 %sgpr83) #0
874  tail call void asm sideeffect "; reg use $0", "{s84}"(i32 %sgpr84) #0
875  tail call void asm sideeffect "; reg use $0", "{s85}"(i32 %sgpr85) #0
876  tail call void asm sideeffect "; reg use $0", "{s86}"(i32 %sgpr86) #0
877  tail call void asm sideeffect "; reg use $0", "{s87}"(i32 %sgpr87) #0
878  tail call void asm sideeffect "; reg use $0", "{s88}"(i32 %sgpr88) #0
879  tail call void asm sideeffect "; reg use $0", "{s89}"(i32 %sgpr89) #0
880  tail call void asm sideeffect "; reg use $0", "{s90}"(i32 %sgpr90) #0
881  tail call void asm sideeffect "; reg use $0", "{s91}"(i32 %sgpr91) #0
882  tail call void asm sideeffect "; reg use $0", "{s92}"(i32 %sgpr92) #0
883  tail call void asm sideeffect "; reg use $0", "{s93}"(i32 %sgpr93) #0
884  tail call void asm sideeffect "; reg use $0", "{s94}"(i32 %sgpr94) #0
885  tail call void asm sideeffect "; reg use $0", "{s95}"(i32 %sgpr95) #0
886  tail call void asm sideeffect "; reg use $0", "{s96}"(i32 %sgpr96) #0
887  tail call void asm sideeffect "; reg use $0", "{s97}"(i32 %sgpr97) #0
888  tail call void asm sideeffect "; reg use $0", "{s98}"(i32 %sgpr98) #0
889  tail call void asm sideeffect "; reg use $0", "{s99}"(i32 %sgpr99) #0
890  tail call void asm sideeffect "; reg use $0", "{s100}"(i32 %sgpr100) #0
891  tail call void asm sideeffect "; reg use $0", "{s101}"(i32 %sgpr101) #0
892  tail call void asm sideeffect "; reg use $0", "{vcc_lo}"(i32 %vcc_lo) #0
893  tail call void asm sideeffect "; reg use $0", "{vcc_hi}"(i32 %vcc_hi) #0
894  ret void
895}
896
897define void @spill_func(ptr addrspace(1) %arg) #0 {
898; CHECK-LABEL: spill_func:
899; CHECK:       ; %bb.0: ; %entry
900; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
901; CHECK-NEXT:    s_xor_saveexec_b64 s[4:5], -1
902; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
903; CHECK-NEXT:    buffer_store_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
904; CHECK-NEXT:    s_mov_b64 exec, s[4:5]
905; CHECK-NEXT:    s_waitcnt expcnt(1)
906; CHECK-NEXT:    v_writelane_b32 v0, s30, 0
907; CHECK-NEXT:    v_writelane_b32 v0, s31, 1
908; CHECK-NEXT:    v_writelane_b32 v0, s33, 2
909; CHECK-NEXT:    v_writelane_b32 v0, s34, 3
910; CHECK-NEXT:    v_writelane_b32 v0, s35, 4
911; CHECK-NEXT:    v_writelane_b32 v0, s36, 5
912; CHECK-NEXT:    v_writelane_b32 v0, s37, 6
913; CHECK-NEXT:    v_writelane_b32 v0, s38, 7
914; CHECK-NEXT:    v_writelane_b32 v0, s39, 8
915; CHECK-NEXT:    v_writelane_b32 v0, s40, 9
916; CHECK-NEXT:    v_writelane_b32 v0, s41, 10
917; CHECK-NEXT:    v_writelane_b32 v0, s42, 11
918; CHECK-NEXT:    v_writelane_b32 v0, s43, 12
919; CHECK-NEXT:    v_writelane_b32 v0, s44, 13
920; CHECK-NEXT:    v_writelane_b32 v0, s45, 14
921; CHECK-NEXT:    v_writelane_b32 v0, s46, 15
922; CHECK-NEXT:    v_writelane_b32 v0, s47, 16
923; CHECK-NEXT:    v_writelane_b32 v0, s48, 17
924; CHECK-NEXT:    v_writelane_b32 v0, s49, 18
925; CHECK-NEXT:    v_writelane_b32 v0, s50, 19
926; CHECK-NEXT:    v_writelane_b32 v0, s51, 20
927; CHECK-NEXT:    v_writelane_b32 v0, s52, 21
928; CHECK-NEXT:    v_writelane_b32 v0, s53, 22
929; CHECK-NEXT:    v_writelane_b32 v0, s54, 23
930; CHECK-NEXT:    v_writelane_b32 v0, s55, 24
931; CHECK-NEXT:    v_writelane_b32 v0, s56, 25
932; CHECK-NEXT:    v_writelane_b32 v0, s57, 26
933; CHECK-NEXT:    v_writelane_b32 v0, s58, 27
934; CHECK-NEXT:    v_writelane_b32 v0, s59, 28
935; CHECK-NEXT:    v_writelane_b32 v0, s60, 29
936; CHECK-NEXT:    v_writelane_b32 v0, s61, 30
937; CHECK-NEXT:    v_writelane_b32 v0, s62, 31
938; CHECK-NEXT:    v_writelane_b32 v0, s63, 32
939; CHECK-NEXT:    v_writelane_b32 v0, s64, 33
940; CHECK-NEXT:    v_writelane_b32 v0, s65, 34
941; CHECK-NEXT:    v_writelane_b32 v0, s66, 35
942; CHECK-NEXT:    v_writelane_b32 v0, s67, 36
943; CHECK-NEXT:    v_writelane_b32 v0, s68, 37
944; CHECK-NEXT:    v_writelane_b32 v0, s69, 38
945; CHECK-NEXT:    v_writelane_b32 v0, s70, 39
946; CHECK-NEXT:    v_writelane_b32 v0, s71, 40
947; CHECK-NEXT:    v_writelane_b32 v0, s72, 41
948; CHECK-NEXT:    v_writelane_b32 v0, s73, 42
949; CHECK-NEXT:    v_writelane_b32 v0, s74, 43
950; CHECK-NEXT:    v_writelane_b32 v0, s75, 44
951; CHECK-NEXT:    v_writelane_b32 v0, s76, 45
952; CHECK-NEXT:    v_writelane_b32 v0, s77, 46
953; CHECK-NEXT:    v_writelane_b32 v0, s78, 47
954; CHECK-NEXT:    v_writelane_b32 v0, s79, 48
955; CHECK-NEXT:    v_writelane_b32 v0, s80, 49
956; CHECK-NEXT:    v_writelane_b32 v0, s81, 50
957; CHECK-NEXT:    v_writelane_b32 v0, s82, 51
958; CHECK-NEXT:    v_writelane_b32 v0, s83, 52
959; CHECK-NEXT:    v_writelane_b32 v0, s84, 53
960; CHECK-NEXT:    v_writelane_b32 v0, s85, 54
961; CHECK-NEXT:    v_writelane_b32 v0, s86, 55
962; CHECK-NEXT:    v_writelane_b32 v0, s87, 56
963; CHECK-NEXT:    v_writelane_b32 v0, s88, 57
964; CHECK-NEXT:    s_waitcnt expcnt(0)
965; CHECK-NEXT:    v_writelane_b32 v1, s95, 0
966; CHECK-NEXT:    v_writelane_b32 v0, s89, 58
967; CHECK-NEXT:    v_writelane_b32 v1, s96, 1
968; CHECK-NEXT:    v_writelane_b32 v0, s90, 59
969; CHECK-NEXT:    v_writelane_b32 v1, s97, 2
970; CHECK-NEXT:    v_writelane_b32 v0, s91, 60
971; CHECK-NEXT:    v_writelane_b32 v1, s98, 3
972; CHECK-NEXT:    v_writelane_b32 v0, s92, 61
973; CHECK-NEXT:    v_writelane_b32 v1, s99, 4
974; CHECK-NEXT:    s_mov_b32 s31, s12
975; CHECK-NEXT:    v_writelane_b32 v0, s93, 62
976; CHECK-NEXT:    v_writelane_b32 v1, s100, 5
977; CHECK-NEXT:    s_cmp_eq_u32 s31, 0
978; CHECK-NEXT:    v_writelane_b32 v0, s94, 63
979; CHECK-NEXT:    v_writelane_b32 v1, s101, 6
980; CHECK-NEXT:    ;;#ASMSTART
981; CHECK-NEXT:    s_mov_b32 s0, 0
982; CHECK-NEXT:    ;;#ASMEND
983; CHECK-NEXT:    ;;#ASMSTART
984; CHECK-NEXT:    s_mov_b32 s1, 0
985; CHECK-NEXT:    ;;#ASMEND
986; CHECK-NEXT:    ;;#ASMSTART
987; CHECK-NEXT:    s_mov_b32 s2, 0
988; CHECK-NEXT:    ;;#ASMEND
989; CHECK-NEXT:    ;;#ASMSTART
990; CHECK-NEXT:    s_mov_b32 s3, 0
991; CHECK-NEXT:    ;;#ASMEND
992; CHECK-NEXT:    ;;#ASMSTART
993; CHECK-NEXT:    s_mov_b32 s4, 0
994; CHECK-NEXT:    ;;#ASMEND
995; CHECK-NEXT:    ;;#ASMSTART
996; CHECK-NEXT:    s_mov_b32 s5, 0
997; CHECK-NEXT:    ;;#ASMEND
998; CHECK-NEXT:    ;;#ASMSTART
999; CHECK-NEXT:    s_mov_b32 s6, 0
1000; CHECK-NEXT:    ;;#ASMEND
1001; CHECK-NEXT:    ;;#ASMSTART
1002; CHECK-NEXT:    s_mov_b32 s7, 0
1003; CHECK-NEXT:    ;;#ASMEND
1004; CHECK-NEXT:    ;;#ASMSTART
1005; CHECK-NEXT:    s_mov_b32 s8, 0
1006; CHECK-NEXT:    ;;#ASMEND
1007; CHECK-NEXT:    ;;#ASMSTART
1008; CHECK-NEXT:    s_mov_b32 s9, 0
1009; CHECK-NEXT:    ;;#ASMEND
1010; CHECK-NEXT:    ;;#ASMSTART
1011; CHECK-NEXT:    s_mov_b32 s10, 0
1012; CHECK-NEXT:    ;;#ASMEND
1013; CHECK-NEXT:    ;;#ASMSTART
1014; CHECK-NEXT:    s_mov_b32 s11, 0
1015; CHECK-NEXT:    ;;#ASMEND
1016; CHECK-NEXT:    ;;#ASMSTART
1017; CHECK-NEXT:    s_mov_b32 s12, 0
1018; CHECK-NEXT:    ;;#ASMEND
1019; CHECK-NEXT:    ;;#ASMSTART
1020; CHECK-NEXT:    s_mov_b32 s13, 0
1021; CHECK-NEXT:    ;;#ASMEND
1022; CHECK-NEXT:    ;;#ASMSTART
1023; CHECK-NEXT:    s_mov_b32 s14, 0
1024; CHECK-NEXT:    ;;#ASMEND
1025; CHECK-NEXT:    ;;#ASMSTART
1026; CHECK-NEXT:    s_mov_b32 s15, 0
1027; CHECK-NEXT:    ;;#ASMEND
1028; CHECK-NEXT:    ;;#ASMSTART
1029; CHECK-NEXT:    s_mov_b32 s16, 0
1030; CHECK-NEXT:    ;;#ASMEND
1031; CHECK-NEXT:    ;;#ASMSTART
1032; CHECK-NEXT:    s_mov_b32 s17, 0
1033; CHECK-NEXT:    ;;#ASMEND
1034; CHECK-NEXT:    ;;#ASMSTART
1035; CHECK-NEXT:    s_mov_b32 s18, 0
1036; CHECK-NEXT:    ;;#ASMEND
1037; CHECK-NEXT:    ;;#ASMSTART
1038; CHECK-NEXT:    s_mov_b32 s19, 0
1039; CHECK-NEXT:    ;;#ASMEND
1040; CHECK-NEXT:    ;;#ASMSTART
1041; CHECK-NEXT:    s_mov_b32 s20, 0
1042; CHECK-NEXT:    ;;#ASMEND
1043; CHECK-NEXT:    ;;#ASMSTART
1044; CHECK-NEXT:    s_mov_b32 s21, 0
1045; CHECK-NEXT:    ;;#ASMEND
1046; CHECK-NEXT:    ;;#ASMSTART
1047; CHECK-NEXT:    s_mov_b32 s22, 0
1048; CHECK-NEXT:    ;;#ASMEND
1049; CHECK-NEXT:    ;;#ASMSTART
1050; CHECK-NEXT:    s_mov_b32 s23, 0
1051; CHECK-NEXT:    ;;#ASMEND
1052; CHECK-NEXT:    ;;#ASMSTART
1053; CHECK-NEXT:    s_mov_b32 s24, 0
1054; CHECK-NEXT:    ;;#ASMEND
1055; CHECK-NEXT:    ;;#ASMSTART
1056; CHECK-NEXT:    s_mov_b32 s25, 0
1057; CHECK-NEXT:    ;;#ASMEND
1058; CHECK-NEXT:    ;;#ASMSTART
1059; CHECK-NEXT:    s_mov_b32 s26, 0
1060; CHECK-NEXT:    ;;#ASMEND
1061; CHECK-NEXT:    ;;#ASMSTART
1062; CHECK-NEXT:    s_mov_b32 s27, 0
1063; CHECK-NEXT:    ;;#ASMEND
1064; CHECK-NEXT:    ;;#ASMSTART
1065; CHECK-NEXT:    s_mov_b32 s28, 0
1066; CHECK-NEXT:    ;;#ASMEND
1067; CHECK-NEXT:    ;;#ASMSTART
1068; CHECK-NEXT:    s_mov_b32 s29, 0
1069; CHECK-NEXT:    ;;#ASMEND
1070; CHECK-NEXT:    ;;#ASMSTART
1071; CHECK-NEXT:    s_mov_b32 s30, 0
1072; CHECK-NEXT:    ;;#ASMEND
1073; CHECK-NEXT:    ;;#ASMSTART
1074; CHECK-NEXT:    s_mov_b32 s31, 0
1075; CHECK-NEXT:    ;;#ASMEND
1076; CHECK-NEXT:    ;;#ASMSTART
1077; CHECK-NEXT:    s_mov_b32 s32, 0
1078; CHECK-NEXT:    ;;#ASMEND
1079; CHECK-NEXT:    ;;#ASMSTART
1080; CHECK-NEXT:    s_mov_b32 s33, 0
1081; CHECK-NEXT:    ;;#ASMEND
1082; CHECK-NEXT:    ;;#ASMSTART
1083; CHECK-NEXT:    s_mov_b32 s34, 0
1084; CHECK-NEXT:    ;;#ASMEND
1085; CHECK-NEXT:    ;;#ASMSTART
1086; CHECK-NEXT:    s_mov_b32 s35, 0
1087; CHECK-NEXT:    ;;#ASMEND
1088; CHECK-NEXT:    ;;#ASMSTART
1089; CHECK-NEXT:    s_mov_b32 s36, 0
1090; CHECK-NEXT:    ;;#ASMEND
1091; CHECK-NEXT:    ;;#ASMSTART
1092; CHECK-NEXT:    s_mov_b32 s37, 0
1093; CHECK-NEXT:    ;;#ASMEND
1094; CHECK-NEXT:    ;;#ASMSTART
1095; CHECK-NEXT:    s_mov_b32 s38, 0
1096; CHECK-NEXT:    ;;#ASMEND
1097; CHECK-NEXT:    ;;#ASMSTART
1098; CHECK-NEXT:    s_mov_b32 s39, 0
1099; CHECK-NEXT:    ;;#ASMEND
1100; CHECK-NEXT:    ;;#ASMSTART
1101; CHECK-NEXT:    s_mov_b32 s40, 0
1102; CHECK-NEXT:    ;;#ASMEND
1103; CHECK-NEXT:    ;;#ASMSTART
1104; CHECK-NEXT:    s_mov_b32 s41, 0
1105; CHECK-NEXT:    ;;#ASMEND
1106; CHECK-NEXT:    ;;#ASMSTART
1107; CHECK-NEXT:    s_mov_b32 s42, 0
1108; CHECK-NEXT:    ;;#ASMEND
1109; CHECK-NEXT:    ;;#ASMSTART
1110; CHECK-NEXT:    s_mov_b32 s43, 0
1111; CHECK-NEXT:    ;;#ASMEND
1112; CHECK-NEXT:    ;;#ASMSTART
1113; CHECK-NEXT:    s_mov_b32 s44, 0
1114; CHECK-NEXT:    ;;#ASMEND
1115; CHECK-NEXT:    ;;#ASMSTART
1116; CHECK-NEXT:    s_mov_b32 s45, 0
1117; CHECK-NEXT:    ;;#ASMEND
1118; CHECK-NEXT:    ;;#ASMSTART
1119; CHECK-NEXT:    s_mov_b32 s46, 0
1120; CHECK-NEXT:    ;;#ASMEND
1121; CHECK-NEXT:    ;;#ASMSTART
1122; CHECK-NEXT:    s_mov_b32 s47, 0
1123; CHECK-NEXT:    ;;#ASMEND
1124; CHECK-NEXT:    ;;#ASMSTART
1125; CHECK-NEXT:    s_mov_b32 s48, 0
1126; CHECK-NEXT:    ;;#ASMEND
1127; CHECK-NEXT:    ;;#ASMSTART
1128; CHECK-NEXT:    s_mov_b32 s49, 0
1129; CHECK-NEXT:    ;;#ASMEND
1130; CHECK-NEXT:    ;;#ASMSTART
1131; CHECK-NEXT:    s_mov_b32 s50, 0
1132; CHECK-NEXT:    ;;#ASMEND
1133; CHECK-NEXT:    ;;#ASMSTART
1134; CHECK-NEXT:    s_mov_b32 s51, 0
1135; CHECK-NEXT:    ;;#ASMEND
1136; CHECK-NEXT:    ;;#ASMSTART
1137; CHECK-NEXT:    s_mov_b32 s52, 0
1138; CHECK-NEXT:    ;;#ASMEND
1139; CHECK-NEXT:    ;;#ASMSTART
1140; CHECK-NEXT:    s_mov_b32 s53, 0
1141; CHECK-NEXT:    ;;#ASMEND
1142; CHECK-NEXT:    ;;#ASMSTART
1143; CHECK-NEXT:    s_mov_b32 s54, 0
1144; CHECK-NEXT:    ;;#ASMEND
1145; CHECK-NEXT:    ;;#ASMSTART
1146; CHECK-NEXT:    s_mov_b32 s55, 0
1147; CHECK-NEXT:    ;;#ASMEND
1148; CHECK-NEXT:    ;;#ASMSTART
1149; CHECK-NEXT:    s_mov_b32 s56, 0
1150; CHECK-NEXT:    ;;#ASMEND
1151; CHECK-NEXT:    ;;#ASMSTART
1152; CHECK-NEXT:    s_mov_b32 s57, 0
1153; CHECK-NEXT:    ;;#ASMEND
1154; CHECK-NEXT:    ;;#ASMSTART
1155; CHECK-NEXT:    s_mov_b32 s58, 0
1156; CHECK-NEXT:    ;;#ASMEND
1157; CHECK-NEXT:    ;;#ASMSTART
1158; CHECK-NEXT:    s_mov_b32 s59, 0
1159; CHECK-NEXT:    ;;#ASMEND
1160; CHECK-NEXT:    ;;#ASMSTART
1161; CHECK-NEXT:    s_mov_b32 s60, 0
1162; CHECK-NEXT:    ;;#ASMEND
1163; CHECK-NEXT:    ;;#ASMSTART
1164; CHECK-NEXT:    s_mov_b32 s61, 0
1165; CHECK-NEXT:    ;;#ASMEND
1166; CHECK-NEXT:    ;;#ASMSTART
1167; CHECK-NEXT:    s_mov_b32 s62, 0
1168; CHECK-NEXT:    ;;#ASMEND
1169; CHECK-NEXT:    ;;#ASMSTART
1170; CHECK-NEXT:    s_mov_b32 s63, 0
1171; CHECK-NEXT:    ;;#ASMEND
1172; CHECK-NEXT:    ;;#ASMSTART
1173; CHECK-NEXT:    s_mov_b32 s64, 0
1174; CHECK-NEXT:    ;;#ASMEND
1175; CHECK-NEXT:    ;;#ASMSTART
1176; CHECK-NEXT:    s_mov_b32 s65, 0
1177; CHECK-NEXT:    ;;#ASMEND
1178; CHECK-NEXT:    ;;#ASMSTART
1179; CHECK-NEXT:    s_mov_b32 s66, 0
1180; CHECK-NEXT:    ;;#ASMEND
1181; CHECK-NEXT:    ;;#ASMSTART
1182; CHECK-NEXT:    s_mov_b32 s67, 0
1183; CHECK-NEXT:    ;;#ASMEND
1184; CHECK-NEXT:    ;;#ASMSTART
1185; CHECK-NEXT:    s_mov_b32 s68, 0
1186; CHECK-NEXT:    ;;#ASMEND
1187; CHECK-NEXT:    ;;#ASMSTART
1188; CHECK-NEXT:    s_mov_b32 s69, 0
1189; CHECK-NEXT:    ;;#ASMEND
1190; CHECK-NEXT:    ;;#ASMSTART
1191; CHECK-NEXT:    s_mov_b32 s70, 0
1192; CHECK-NEXT:    ;;#ASMEND
1193; CHECK-NEXT:    ;;#ASMSTART
1194; CHECK-NEXT:    s_mov_b32 s71, 0
1195; CHECK-NEXT:    ;;#ASMEND
1196; CHECK-NEXT:    ;;#ASMSTART
1197; CHECK-NEXT:    s_mov_b32 s72, 0
1198; CHECK-NEXT:    ;;#ASMEND
1199; CHECK-NEXT:    ;;#ASMSTART
1200; CHECK-NEXT:    s_mov_b32 s73, 0
1201; CHECK-NEXT:    ;;#ASMEND
1202; CHECK-NEXT:    ;;#ASMSTART
1203; CHECK-NEXT:    s_mov_b32 s74, 0
1204; CHECK-NEXT:    ;;#ASMEND
1205; CHECK-NEXT:    ;;#ASMSTART
1206; CHECK-NEXT:    s_mov_b32 s75, 0
1207; CHECK-NEXT:    ;;#ASMEND
1208; CHECK-NEXT:    ;;#ASMSTART
1209; CHECK-NEXT:    s_mov_b32 s76, 0
1210; CHECK-NEXT:    ;;#ASMEND
1211; CHECK-NEXT:    ;;#ASMSTART
1212; CHECK-NEXT:    s_mov_b32 s77, 0
1213; CHECK-NEXT:    ;;#ASMEND
1214; CHECK-NEXT:    ;;#ASMSTART
1215; CHECK-NEXT:    s_mov_b32 s78, 0
1216; CHECK-NEXT:    ;;#ASMEND
1217; CHECK-NEXT:    ;;#ASMSTART
1218; CHECK-NEXT:    s_mov_b32 s79, 0
1219; CHECK-NEXT:    ;;#ASMEND
1220; CHECK-NEXT:    ;;#ASMSTART
1221; CHECK-NEXT:    s_mov_b32 s80, 0
1222; CHECK-NEXT:    ;;#ASMEND
1223; CHECK-NEXT:    ;;#ASMSTART
1224; CHECK-NEXT:    s_mov_b32 s81, 0
1225; CHECK-NEXT:    ;;#ASMEND
1226; CHECK-NEXT:    ;;#ASMSTART
1227; CHECK-NEXT:    s_mov_b32 s82, 0
1228; CHECK-NEXT:    ;;#ASMEND
1229; CHECK-NEXT:    ;;#ASMSTART
1230; CHECK-NEXT:    s_mov_b32 s83, 0
1231; CHECK-NEXT:    ;;#ASMEND
1232; CHECK-NEXT:    ;;#ASMSTART
1233; CHECK-NEXT:    s_mov_b32 s84, 0
1234; CHECK-NEXT:    ;;#ASMEND
1235; CHECK-NEXT:    ;;#ASMSTART
1236; CHECK-NEXT:    s_mov_b32 s85, 0
1237; CHECK-NEXT:    ;;#ASMEND
1238; CHECK-NEXT:    ;;#ASMSTART
1239; CHECK-NEXT:    s_mov_b32 s86, 0
1240; CHECK-NEXT:    ;;#ASMEND
1241; CHECK-NEXT:    ;;#ASMSTART
1242; CHECK-NEXT:    s_mov_b32 s87, 0
1243; CHECK-NEXT:    ;;#ASMEND
1244; CHECK-NEXT:    ;;#ASMSTART
1245; CHECK-NEXT:    s_mov_b32 s88, 0
1246; CHECK-NEXT:    ;;#ASMEND
1247; CHECK-NEXT:    ;;#ASMSTART
1248; CHECK-NEXT:    s_mov_b32 s89, 0
1249; CHECK-NEXT:    ;;#ASMEND
1250; CHECK-NEXT:    ;;#ASMSTART
1251; CHECK-NEXT:    s_mov_b32 s90, 0
1252; CHECK-NEXT:    ;;#ASMEND
1253; CHECK-NEXT:    ;;#ASMSTART
1254; CHECK-NEXT:    s_mov_b32 s91, 0
1255; CHECK-NEXT:    ;;#ASMEND
1256; CHECK-NEXT:    ;;#ASMSTART
1257; CHECK-NEXT:    s_mov_b32 s92, 0
1258; CHECK-NEXT:    ;;#ASMEND
1259; CHECK-NEXT:    ;;#ASMSTART
1260; CHECK-NEXT:    s_mov_b32 s93, 0
1261; CHECK-NEXT:    ;;#ASMEND
1262; CHECK-NEXT:    ;;#ASMSTART
1263; CHECK-NEXT:    s_mov_b32 s94, 0
1264; CHECK-NEXT:    ;;#ASMEND
1265; CHECK-NEXT:    ;;#ASMSTART
1266; CHECK-NEXT:    s_mov_b32 s95, 0
1267; CHECK-NEXT:    ;;#ASMEND
1268; CHECK-NEXT:    ;;#ASMSTART
1269; CHECK-NEXT:    s_mov_b32 s96, 0
1270; CHECK-NEXT:    ;;#ASMEND
1271; CHECK-NEXT:    ;;#ASMSTART
1272; CHECK-NEXT:    s_mov_b32 s97, 0
1273; CHECK-NEXT:    ;;#ASMEND
1274; CHECK-NEXT:    ;;#ASMSTART
1275; CHECK-NEXT:    s_mov_b32 s98, 0
1276; CHECK-NEXT:    ;;#ASMEND
1277; CHECK-NEXT:    ;;#ASMSTART
1278; CHECK-NEXT:    s_mov_b32 s99, 0
1279; CHECK-NEXT:    ;;#ASMEND
1280; CHECK-NEXT:    ;;#ASMSTART
1281; CHECK-NEXT:    s_mov_b32 s100, 0
1282; CHECK-NEXT:    ;;#ASMEND
1283; CHECK-NEXT:    ;;#ASMSTART
1284; CHECK-NEXT:    s_mov_b32 s101, 0
1285; CHECK-NEXT:    ;;#ASMEND
1286; CHECK-NEXT:    ;;#ASMSTART
1287; CHECK-NEXT:    s_mov_b32 vcc_lo, 0
1288; CHECK-NEXT:    ;;#ASMEND
1289; CHECK-NEXT:    ;;#ASMSTART
1290; CHECK-NEXT:    s_mov_b32 vcc_hi, 0
1291; CHECK-NEXT:    ;;#ASMEND
1292; CHECK-NEXT:    s_cbranch_scc0 .LBB1_1
1293; CHECK-NEXT:  ; %bb.3: ; %entry
1294; CHECK-NEXT:    s_not_b64 exec, exec
1295; CHECK-NEXT:    buffer_store_dword v2, off, s[0:3], s32 offset:8
1296; CHECK-NEXT:    v_writelane_b32 v2, s0, 0
1297; CHECK-NEXT:    v_writelane_b32 v2, s1, 1
1298; CHECK-NEXT:    s_getpc_b64 s[0:1]
1299; CHECK-NEXT:  .Lpost_getpc1:
1300; CHECK-NEXT:    s_add_u32 s0, s0, (.LBB1_4-.Lpost_getpc1)&4294967295
1301; CHECK-NEXT:    s_addc_u32 s1, s1, (.LBB1_4-.Lpost_getpc1)>>32
1302; CHECK-NEXT:    s_setpc_b64 s[0:1]
1303; CHECK-NEXT:  .LBB1_1: ; %bb2
1304; CHECK-NEXT:    ;;#ASMSTART
1305; CHECK-NEXT:    v_nop_e64
1306; CHECK-NEXT:    v_nop_e64
1307; CHECK-NEXT:    v_nop_e64
1308; CHECK-NEXT:    v_nop_e64
1309; CHECK-NEXT:    v_nop_e64
1310; CHECK-NEXT:    v_nop_e64
1311; CHECK-NEXT:    v_nop_e64
1312; CHECK-NEXT:    v_nop_e64
1313; CHECK-NEXT:    ;;#ASMEND
1314; CHECK-NEXT:    s_branch .LBB1_2
1315; CHECK-NEXT:  .LBB1_4: ; %bb3
1316; CHECK-NEXT:    v_readlane_b32 s0, v2, 0
1317; CHECK-NEXT:    v_readlane_b32 s1, v2, 1
1318; CHECK-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:8
1319; CHECK-NEXT:    s_not_b64 exec, exec
1320; CHECK-NEXT:  .LBB1_2: ; %bb3
1321; CHECK-NEXT:    ;;#ASMSTART
1322; CHECK-NEXT:    ; reg use s0
1323; CHECK-NEXT:    ;;#ASMEND
1324; CHECK-NEXT:    ;;#ASMSTART
1325; CHECK-NEXT:    ; reg use s1
1326; CHECK-NEXT:    ;;#ASMEND
1327; CHECK-NEXT:    ;;#ASMSTART
1328; CHECK-NEXT:    ; reg use s2
1329; CHECK-NEXT:    ;;#ASMEND
1330; CHECK-NEXT:    ;;#ASMSTART
1331; CHECK-NEXT:    ; reg use s3
1332; CHECK-NEXT:    ;;#ASMEND
1333; CHECK-NEXT:    ;;#ASMSTART
1334; CHECK-NEXT:    ; reg use s4
1335; CHECK-NEXT:    ;;#ASMEND
1336; CHECK-NEXT:    ;;#ASMSTART
1337; CHECK-NEXT:    ; reg use s5
1338; CHECK-NEXT:    ;;#ASMEND
1339; CHECK-NEXT:    ;;#ASMSTART
1340; CHECK-NEXT:    ; reg use s6
1341; CHECK-NEXT:    ;;#ASMEND
1342; CHECK-NEXT:    ;;#ASMSTART
1343; CHECK-NEXT:    ; reg use s7
1344; CHECK-NEXT:    ;;#ASMEND
1345; CHECK-NEXT:    ;;#ASMSTART
1346; CHECK-NEXT:    ; reg use s8
1347; CHECK-NEXT:    ;;#ASMEND
1348; CHECK-NEXT:    ;;#ASMSTART
1349; CHECK-NEXT:    ; reg use s9
1350; CHECK-NEXT:    ;;#ASMEND
1351; CHECK-NEXT:    ;;#ASMSTART
1352; CHECK-NEXT:    ; reg use s10
1353; CHECK-NEXT:    ;;#ASMEND
1354; CHECK-NEXT:    ;;#ASMSTART
1355; CHECK-NEXT:    ; reg use s11
1356; CHECK-NEXT:    ;;#ASMEND
1357; CHECK-NEXT:    ;;#ASMSTART
1358; CHECK-NEXT:    ; reg use s12
1359; CHECK-NEXT:    ;;#ASMEND
1360; CHECK-NEXT:    ;;#ASMSTART
1361; CHECK-NEXT:    ; reg use s13
1362; CHECK-NEXT:    ;;#ASMEND
1363; CHECK-NEXT:    ;;#ASMSTART
1364; CHECK-NEXT:    ; reg use s14
1365; CHECK-NEXT:    ;;#ASMEND
1366; CHECK-NEXT:    ;;#ASMSTART
1367; CHECK-NEXT:    ; reg use s15
1368; CHECK-NEXT:    ;;#ASMEND
1369; CHECK-NEXT:    ;;#ASMSTART
1370; CHECK-NEXT:    ; reg use s16
1371; CHECK-NEXT:    ;;#ASMEND
1372; CHECK-NEXT:    ;;#ASMSTART
1373; CHECK-NEXT:    ; reg use s17
1374; CHECK-NEXT:    ;;#ASMEND
1375; CHECK-NEXT:    ;;#ASMSTART
1376; CHECK-NEXT:    ; reg use s18
1377; CHECK-NEXT:    ;;#ASMEND
1378; CHECK-NEXT:    ;;#ASMSTART
1379; CHECK-NEXT:    ; reg use s19
1380; CHECK-NEXT:    ;;#ASMEND
1381; CHECK-NEXT:    ;;#ASMSTART
1382; CHECK-NEXT:    ; reg use s20
1383; CHECK-NEXT:    ;;#ASMEND
1384; CHECK-NEXT:    ;;#ASMSTART
1385; CHECK-NEXT:    ; reg use s21
1386; CHECK-NEXT:    ;;#ASMEND
1387; CHECK-NEXT:    ;;#ASMSTART
1388; CHECK-NEXT:    ; reg use s22
1389; CHECK-NEXT:    ;;#ASMEND
1390; CHECK-NEXT:    ;;#ASMSTART
1391; CHECK-NEXT:    ; reg use s23
1392; CHECK-NEXT:    ;;#ASMEND
1393; CHECK-NEXT:    ;;#ASMSTART
1394; CHECK-NEXT:    ; reg use s24
1395; CHECK-NEXT:    ;;#ASMEND
1396; CHECK-NEXT:    ;;#ASMSTART
1397; CHECK-NEXT:    ; reg use s25
1398; CHECK-NEXT:    ;;#ASMEND
1399; CHECK-NEXT:    ;;#ASMSTART
1400; CHECK-NEXT:    ; reg use s26
1401; CHECK-NEXT:    ;;#ASMEND
1402; CHECK-NEXT:    ;;#ASMSTART
1403; CHECK-NEXT:    ; reg use s27
1404; CHECK-NEXT:    ;;#ASMEND
1405; CHECK-NEXT:    ;;#ASMSTART
1406; CHECK-NEXT:    ; reg use s28
1407; CHECK-NEXT:    ;;#ASMEND
1408; CHECK-NEXT:    ;;#ASMSTART
1409; CHECK-NEXT:    ; reg use s29
1410; CHECK-NEXT:    ;;#ASMEND
1411; CHECK-NEXT:    ;;#ASMSTART
1412; CHECK-NEXT:    ; reg use s30
1413; CHECK-NEXT:    ;;#ASMEND
1414; CHECK-NEXT:    ;;#ASMSTART
1415; CHECK-NEXT:    ; reg use s31
1416; CHECK-NEXT:    ;;#ASMEND
1417; CHECK-NEXT:    ;;#ASMSTART
1418; CHECK-NEXT:    ; reg use s32
1419; CHECK-NEXT:    ;;#ASMEND
1420; CHECK-NEXT:    ;;#ASMSTART
1421; CHECK-NEXT:    ; reg use s33
1422; CHECK-NEXT:    ;;#ASMEND
1423; CHECK-NEXT:    ;;#ASMSTART
1424; CHECK-NEXT:    ; reg use s34
1425; CHECK-NEXT:    ;;#ASMEND
1426; CHECK-NEXT:    ;;#ASMSTART
1427; CHECK-NEXT:    ; reg use s35
1428; CHECK-NEXT:    ;;#ASMEND
1429; CHECK-NEXT:    ;;#ASMSTART
1430; CHECK-NEXT:    ; reg use s36
1431; CHECK-NEXT:    ;;#ASMEND
1432; CHECK-NEXT:    ;;#ASMSTART
1433; CHECK-NEXT:    ; reg use s37
1434; CHECK-NEXT:    ;;#ASMEND
1435; CHECK-NEXT:    ;;#ASMSTART
1436; CHECK-NEXT:    ; reg use s38
1437; CHECK-NEXT:    ;;#ASMEND
1438; CHECK-NEXT:    ;;#ASMSTART
1439; CHECK-NEXT:    ; reg use s39
1440; CHECK-NEXT:    ;;#ASMEND
1441; CHECK-NEXT:    ;;#ASMSTART
1442; CHECK-NEXT:    ; reg use s40
1443; CHECK-NEXT:    ;;#ASMEND
1444; CHECK-NEXT:    ;;#ASMSTART
1445; CHECK-NEXT:    ; reg use s41
1446; CHECK-NEXT:    ;;#ASMEND
1447; CHECK-NEXT:    ;;#ASMSTART
1448; CHECK-NEXT:    ; reg use s42
1449; CHECK-NEXT:    ;;#ASMEND
1450; CHECK-NEXT:    ;;#ASMSTART
1451; CHECK-NEXT:    ; reg use s43
1452; CHECK-NEXT:    ;;#ASMEND
1453; CHECK-NEXT:    ;;#ASMSTART
1454; CHECK-NEXT:    ; reg use s44
1455; CHECK-NEXT:    ;;#ASMEND
1456; CHECK-NEXT:    ;;#ASMSTART
1457; CHECK-NEXT:    ; reg use s45
1458; CHECK-NEXT:    ;;#ASMEND
1459; CHECK-NEXT:    ;;#ASMSTART
1460; CHECK-NEXT:    ; reg use s46
1461; CHECK-NEXT:    ;;#ASMEND
1462; CHECK-NEXT:    ;;#ASMSTART
1463; CHECK-NEXT:    ; reg use s47
1464; CHECK-NEXT:    ;;#ASMEND
1465; CHECK-NEXT:    ;;#ASMSTART
1466; CHECK-NEXT:    ; reg use s48
1467; CHECK-NEXT:    ;;#ASMEND
1468; CHECK-NEXT:    ;;#ASMSTART
1469; CHECK-NEXT:    ; reg use s49
1470; CHECK-NEXT:    ;;#ASMEND
1471; CHECK-NEXT:    ;;#ASMSTART
1472; CHECK-NEXT:    ; reg use s50
1473; CHECK-NEXT:    ;;#ASMEND
1474; CHECK-NEXT:    ;;#ASMSTART
1475; CHECK-NEXT:    ; reg use s51
1476; CHECK-NEXT:    ;;#ASMEND
1477; CHECK-NEXT:    ;;#ASMSTART
1478; CHECK-NEXT:    ; reg use s52
1479; CHECK-NEXT:    ;;#ASMEND
1480; CHECK-NEXT:    ;;#ASMSTART
1481; CHECK-NEXT:    ; reg use s53
1482; CHECK-NEXT:    ;;#ASMEND
1483; CHECK-NEXT:    ;;#ASMSTART
1484; CHECK-NEXT:    ; reg use s54
1485; CHECK-NEXT:    ;;#ASMEND
1486; CHECK-NEXT:    ;;#ASMSTART
1487; CHECK-NEXT:    ; reg use s55
1488; CHECK-NEXT:    ;;#ASMEND
1489; CHECK-NEXT:    ;;#ASMSTART
1490; CHECK-NEXT:    ; reg use s56
1491; CHECK-NEXT:    ;;#ASMEND
1492; CHECK-NEXT:    ;;#ASMSTART
1493; CHECK-NEXT:    ; reg use s57
1494; CHECK-NEXT:    ;;#ASMEND
1495; CHECK-NEXT:    ;;#ASMSTART
1496; CHECK-NEXT:    ; reg use s58
1497; CHECK-NEXT:    ;;#ASMEND
1498; CHECK-NEXT:    ;;#ASMSTART
1499; CHECK-NEXT:    ; reg use s59
1500; CHECK-NEXT:    ;;#ASMEND
1501; CHECK-NEXT:    ;;#ASMSTART
1502; CHECK-NEXT:    ; reg use s60
1503; CHECK-NEXT:    ;;#ASMEND
1504; CHECK-NEXT:    ;;#ASMSTART
1505; CHECK-NEXT:    ; reg use s61
1506; CHECK-NEXT:    ;;#ASMEND
1507; CHECK-NEXT:    ;;#ASMSTART
1508; CHECK-NEXT:    ; reg use s62
1509; CHECK-NEXT:    ;;#ASMEND
1510; CHECK-NEXT:    ;;#ASMSTART
1511; CHECK-NEXT:    ; reg use s63
1512; CHECK-NEXT:    ;;#ASMEND
1513; CHECK-NEXT:    ;;#ASMSTART
1514; CHECK-NEXT:    ; reg use s64
1515; CHECK-NEXT:    ;;#ASMEND
1516; CHECK-NEXT:    ;;#ASMSTART
1517; CHECK-NEXT:    ; reg use s65
1518; CHECK-NEXT:    ;;#ASMEND
1519; CHECK-NEXT:    ;;#ASMSTART
1520; CHECK-NEXT:    ; reg use s66
1521; CHECK-NEXT:    ;;#ASMEND
1522; CHECK-NEXT:    ;;#ASMSTART
1523; CHECK-NEXT:    ; reg use s67
1524; CHECK-NEXT:    ;;#ASMEND
1525; CHECK-NEXT:    ;;#ASMSTART
1526; CHECK-NEXT:    ; reg use s68
1527; CHECK-NEXT:    ;;#ASMEND
1528; CHECK-NEXT:    ;;#ASMSTART
1529; CHECK-NEXT:    ; reg use s69
1530; CHECK-NEXT:    ;;#ASMEND
1531; CHECK-NEXT:    ;;#ASMSTART
1532; CHECK-NEXT:    ; reg use s70
1533; CHECK-NEXT:    ;;#ASMEND
1534; CHECK-NEXT:    ;;#ASMSTART
1535; CHECK-NEXT:    ; reg use s71
1536; CHECK-NEXT:    ;;#ASMEND
1537; CHECK-NEXT:    ;;#ASMSTART
1538; CHECK-NEXT:    ; reg use s72
1539; CHECK-NEXT:    ;;#ASMEND
1540; CHECK-NEXT:    ;;#ASMSTART
1541; CHECK-NEXT:    ; reg use s73
1542; CHECK-NEXT:    ;;#ASMEND
1543; CHECK-NEXT:    ;;#ASMSTART
1544; CHECK-NEXT:    ; reg use s74
1545; CHECK-NEXT:    ;;#ASMEND
1546; CHECK-NEXT:    ;;#ASMSTART
1547; CHECK-NEXT:    ; reg use s75
1548; CHECK-NEXT:    ;;#ASMEND
1549; CHECK-NEXT:    ;;#ASMSTART
1550; CHECK-NEXT:    ; reg use s76
1551; CHECK-NEXT:    ;;#ASMEND
1552; CHECK-NEXT:    ;;#ASMSTART
1553; CHECK-NEXT:    ; reg use s77
1554; CHECK-NEXT:    ;;#ASMEND
1555; CHECK-NEXT:    ;;#ASMSTART
1556; CHECK-NEXT:    ; reg use s78
1557; CHECK-NEXT:    ;;#ASMEND
1558; CHECK-NEXT:    ;;#ASMSTART
1559; CHECK-NEXT:    ; reg use s79
1560; CHECK-NEXT:    ;;#ASMEND
1561; CHECK-NEXT:    ;;#ASMSTART
1562; CHECK-NEXT:    ; reg use s80
1563; CHECK-NEXT:    ;;#ASMEND
1564; CHECK-NEXT:    ;;#ASMSTART
1565; CHECK-NEXT:    ; reg use s81
1566; CHECK-NEXT:    ;;#ASMEND
1567; CHECK-NEXT:    ;;#ASMSTART
1568; CHECK-NEXT:    ; reg use s82
1569; CHECK-NEXT:    ;;#ASMEND
1570; CHECK-NEXT:    ;;#ASMSTART
1571; CHECK-NEXT:    ; reg use s83
1572; CHECK-NEXT:    ;;#ASMEND
1573; CHECK-NEXT:    ;;#ASMSTART
1574; CHECK-NEXT:    ; reg use s84
1575; CHECK-NEXT:    ;;#ASMEND
1576; CHECK-NEXT:    ;;#ASMSTART
1577; CHECK-NEXT:    ; reg use s85
1578; CHECK-NEXT:    ;;#ASMEND
1579; CHECK-NEXT:    ;;#ASMSTART
1580; CHECK-NEXT:    ; reg use s86
1581; CHECK-NEXT:    ;;#ASMEND
1582; CHECK-NEXT:    ;;#ASMSTART
1583; CHECK-NEXT:    ; reg use s87
1584; CHECK-NEXT:    ;;#ASMEND
1585; CHECK-NEXT:    ;;#ASMSTART
1586; CHECK-NEXT:    ; reg use s88
1587; CHECK-NEXT:    ;;#ASMEND
1588; CHECK-NEXT:    ;;#ASMSTART
1589; CHECK-NEXT:    ; reg use s89
1590; CHECK-NEXT:    ;;#ASMEND
1591; CHECK-NEXT:    ;;#ASMSTART
1592; CHECK-NEXT:    ; reg use s90
1593; CHECK-NEXT:    ;;#ASMEND
1594; CHECK-NEXT:    ;;#ASMSTART
1595; CHECK-NEXT:    ; reg use s91
1596; CHECK-NEXT:    ;;#ASMEND
1597; CHECK-NEXT:    ;;#ASMSTART
1598; CHECK-NEXT:    ; reg use s92
1599; CHECK-NEXT:    ;;#ASMEND
1600; CHECK-NEXT:    ;;#ASMSTART
1601; CHECK-NEXT:    ; reg use s93
1602; CHECK-NEXT:    ;;#ASMEND
1603; CHECK-NEXT:    ;;#ASMSTART
1604; CHECK-NEXT:    ; reg use s94
1605; CHECK-NEXT:    ;;#ASMEND
1606; CHECK-NEXT:    ;;#ASMSTART
1607; CHECK-NEXT:    ; reg use s95
1608; CHECK-NEXT:    ;;#ASMEND
1609; CHECK-NEXT:    ;;#ASMSTART
1610; CHECK-NEXT:    ; reg use s96
1611; CHECK-NEXT:    ;;#ASMEND
1612; CHECK-NEXT:    ;;#ASMSTART
1613; CHECK-NEXT:    ; reg use s97
1614; CHECK-NEXT:    ;;#ASMEND
1615; CHECK-NEXT:    ;;#ASMSTART
1616; CHECK-NEXT:    ; reg use s98
1617; CHECK-NEXT:    ;;#ASMEND
1618; CHECK-NEXT:    ;;#ASMSTART
1619; CHECK-NEXT:    ; reg use s99
1620; CHECK-NEXT:    ;;#ASMEND
1621; CHECK-NEXT:    ;;#ASMSTART
1622; CHECK-NEXT:    ; reg use s100
1623; CHECK-NEXT:    ;;#ASMEND
1624; CHECK-NEXT:    ;;#ASMSTART
1625; CHECK-NEXT:    ; reg use s101
1626; CHECK-NEXT:    ;;#ASMEND
1627; CHECK-NEXT:    ;;#ASMSTART
1628; CHECK-NEXT:    ; reg use vcc_lo
1629; CHECK-NEXT:    ;;#ASMEND
1630; CHECK-NEXT:    ;;#ASMSTART
1631; CHECK-NEXT:    ; reg use vcc_hi
1632; CHECK-NEXT:    ;;#ASMEND
1633; CHECK-NEXT:    v_readlane_b32 s101, v1, 6
1634; CHECK-NEXT:    v_readlane_b32 s100, v1, 5
1635; CHECK-NEXT:    v_readlane_b32 s99, v1, 4
1636; CHECK-NEXT:    v_readlane_b32 s98, v1, 3
1637; CHECK-NEXT:    v_readlane_b32 s97, v1, 2
1638; CHECK-NEXT:    v_readlane_b32 s96, v1, 1
1639; CHECK-NEXT:    v_readlane_b32 s95, v1, 0
1640; CHECK-NEXT:    v_readlane_b32 s94, v0, 63
1641; CHECK-NEXT:    v_readlane_b32 s93, v0, 62
1642; CHECK-NEXT:    v_readlane_b32 s92, v0, 61
1643; CHECK-NEXT:    v_readlane_b32 s91, v0, 60
1644; CHECK-NEXT:    v_readlane_b32 s90, v0, 59
1645; CHECK-NEXT:    v_readlane_b32 s89, v0, 58
1646; CHECK-NEXT:    v_readlane_b32 s88, v0, 57
1647; CHECK-NEXT:    v_readlane_b32 s87, v0, 56
1648; CHECK-NEXT:    v_readlane_b32 s86, v0, 55
1649; CHECK-NEXT:    v_readlane_b32 s85, v0, 54
1650; CHECK-NEXT:    v_readlane_b32 s84, v0, 53
1651; CHECK-NEXT:    v_readlane_b32 s83, v0, 52
1652; CHECK-NEXT:    v_readlane_b32 s82, v0, 51
1653; CHECK-NEXT:    v_readlane_b32 s81, v0, 50
1654; CHECK-NEXT:    v_readlane_b32 s80, v0, 49
1655; CHECK-NEXT:    v_readlane_b32 s79, v0, 48
1656; CHECK-NEXT:    v_readlane_b32 s78, v0, 47
1657; CHECK-NEXT:    v_readlane_b32 s77, v0, 46
1658; CHECK-NEXT:    v_readlane_b32 s76, v0, 45
1659; CHECK-NEXT:    v_readlane_b32 s75, v0, 44
1660; CHECK-NEXT:    v_readlane_b32 s74, v0, 43
1661; CHECK-NEXT:    v_readlane_b32 s73, v0, 42
1662; CHECK-NEXT:    v_readlane_b32 s72, v0, 41
1663; CHECK-NEXT:    v_readlane_b32 s71, v0, 40
1664; CHECK-NEXT:    v_readlane_b32 s70, v0, 39
1665; CHECK-NEXT:    v_readlane_b32 s69, v0, 38
1666; CHECK-NEXT:    v_readlane_b32 s68, v0, 37
1667; CHECK-NEXT:    v_readlane_b32 s67, v0, 36
1668; CHECK-NEXT:    v_readlane_b32 s66, v0, 35
1669; CHECK-NEXT:    v_readlane_b32 s65, v0, 34
1670; CHECK-NEXT:    v_readlane_b32 s64, v0, 33
1671; CHECK-NEXT:    v_readlane_b32 s63, v0, 32
1672; CHECK-NEXT:    v_readlane_b32 s62, v0, 31
1673; CHECK-NEXT:    v_readlane_b32 s61, v0, 30
1674; CHECK-NEXT:    v_readlane_b32 s60, v0, 29
1675; CHECK-NEXT:    v_readlane_b32 s59, v0, 28
1676; CHECK-NEXT:    v_readlane_b32 s58, v0, 27
1677; CHECK-NEXT:    v_readlane_b32 s57, v0, 26
1678; CHECK-NEXT:    v_readlane_b32 s56, v0, 25
1679; CHECK-NEXT:    v_readlane_b32 s55, v0, 24
1680; CHECK-NEXT:    v_readlane_b32 s54, v0, 23
1681; CHECK-NEXT:    v_readlane_b32 s53, v0, 22
1682; CHECK-NEXT:    v_readlane_b32 s52, v0, 21
1683; CHECK-NEXT:    v_readlane_b32 s51, v0, 20
1684; CHECK-NEXT:    v_readlane_b32 s50, v0, 19
1685; CHECK-NEXT:    v_readlane_b32 s49, v0, 18
1686; CHECK-NEXT:    v_readlane_b32 s48, v0, 17
1687; CHECK-NEXT:    v_readlane_b32 s47, v0, 16
1688; CHECK-NEXT:    v_readlane_b32 s46, v0, 15
1689; CHECK-NEXT:    v_readlane_b32 s45, v0, 14
1690; CHECK-NEXT:    v_readlane_b32 s44, v0, 13
1691; CHECK-NEXT:    v_readlane_b32 s43, v0, 12
1692; CHECK-NEXT:    v_readlane_b32 s42, v0, 11
1693; CHECK-NEXT:    v_readlane_b32 s41, v0, 10
1694; CHECK-NEXT:    v_readlane_b32 s40, v0, 9
1695; CHECK-NEXT:    v_readlane_b32 s39, v0, 8
1696; CHECK-NEXT:    v_readlane_b32 s38, v0, 7
1697; CHECK-NEXT:    v_readlane_b32 s37, v0, 6
1698; CHECK-NEXT:    v_readlane_b32 s36, v0, 5
1699; CHECK-NEXT:    v_readlane_b32 s35, v0, 4
1700; CHECK-NEXT:    v_readlane_b32 s34, v0, 3
1701; CHECK-NEXT:    v_readlane_b32 s33, v0, 2
1702; CHECK-NEXT:    v_readlane_b32 s31, v0, 1
1703; CHECK-NEXT:    v_readlane_b32 s30, v0, 0
1704; CHECK-NEXT:    s_xor_saveexec_b64 s[4:5], -1
1705; CHECK-NEXT:    buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
1706; CHECK-NEXT:    buffer_load_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
1707; CHECK-NEXT:    s_mov_b64 exec, s[4:5]
1708; CHECK-NEXT:    s_waitcnt vmcnt(0)
1709; CHECK-NEXT:    s_setpc_b64 s[30:31]
1710entry:
1711  %cnd = tail call i32 @llvm.amdgcn.workgroup.id.x() #0
1712  %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
1713  %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
1714  %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
1715  %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
1716  %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
1717  %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
1718  %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
1719  %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
1720  %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
1721  %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
1722  %sgpr10 = tail call i32 asm sideeffect "s_mov_b32 s10, 0", "={s10}"() #0
1723  %sgpr11 = tail call i32 asm sideeffect "s_mov_b32 s11, 0", "={s11}"() #0
1724  %sgpr12 = tail call i32 asm sideeffect "s_mov_b32 s12, 0", "={s12}"() #0
1725  %sgpr13 = tail call i32 asm sideeffect "s_mov_b32 s13, 0", "={s13}"() #0
1726  %sgpr14 = tail call i32 asm sideeffect "s_mov_b32 s14, 0", "={s14}"() #0
1727  %sgpr15 = tail call i32 asm sideeffect "s_mov_b32 s15, 0", "={s15}"() #0
1728  %sgpr16 = tail call i32 asm sideeffect "s_mov_b32 s16, 0", "={s16}"() #0
1729  %sgpr17 = tail call i32 asm sideeffect "s_mov_b32 s17, 0", "={s17}"() #0
1730  %sgpr18 = tail call i32 asm sideeffect "s_mov_b32 s18, 0", "={s18}"() #0
1731  %sgpr19 = tail call i32 asm sideeffect "s_mov_b32 s19, 0", "={s19}"() #0
1732  %sgpr20 = tail call i32 asm sideeffect "s_mov_b32 s20, 0", "={s20}"() #0
1733  %sgpr21 = tail call i32 asm sideeffect "s_mov_b32 s21, 0", "={s21}"() #0
1734  %sgpr22 = tail call i32 asm sideeffect "s_mov_b32 s22, 0", "={s22}"() #0
1735  %sgpr23 = tail call i32 asm sideeffect "s_mov_b32 s23, 0", "={s23}"() #0
1736  %sgpr24 = tail call i32 asm sideeffect "s_mov_b32 s24, 0", "={s24}"() #0
1737  %sgpr25 = tail call i32 asm sideeffect "s_mov_b32 s25, 0", "={s25}"() #0
1738  %sgpr26 = tail call i32 asm sideeffect "s_mov_b32 s26, 0", "={s26}"() #0
1739  %sgpr27 = tail call i32 asm sideeffect "s_mov_b32 s27, 0", "={s27}"() #0
1740  %sgpr28 = tail call i32 asm sideeffect "s_mov_b32 s28, 0", "={s28}"() #0
1741  %sgpr29 = tail call i32 asm sideeffect "s_mov_b32 s29, 0", "={s29}"() #0
1742  %sgpr30 = tail call i32 asm sideeffect "s_mov_b32 s30, 0", "={s30}"() #0
1743  %sgpr31 = tail call i32 asm sideeffect "s_mov_b32 s31, 0", "={s31}"() #0
1744  %sgpr32 = tail call i32 asm sideeffect "s_mov_b32 s32, 0", "={s32}"() #0
1745  %sgpr33 = tail call i32 asm sideeffect "s_mov_b32 s33, 0", "={s33}"() #0
1746  %sgpr34 = tail call i32 asm sideeffect "s_mov_b32 s34, 0", "={s34}"() #0
1747  %sgpr35 = tail call i32 asm sideeffect "s_mov_b32 s35, 0", "={s35}"() #0
1748  %sgpr36 = tail call i32 asm sideeffect "s_mov_b32 s36, 0", "={s36}"() #0
1749  %sgpr37 = tail call i32 asm sideeffect "s_mov_b32 s37, 0", "={s37}"() #0
1750  %sgpr38 = tail call i32 asm sideeffect "s_mov_b32 s38, 0", "={s38}"() #0
1751  %sgpr39 = tail call i32 asm sideeffect "s_mov_b32 s39, 0", "={s39}"() #0
1752  %sgpr40 = tail call i32 asm sideeffect "s_mov_b32 s40, 0", "={s40}"() #0
1753  %sgpr41 = tail call i32 asm sideeffect "s_mov_b32 s41, 0", "={s41}"() #0
1754  %sgpr42 = tail call i32 asm sideeffect "s_mov_b32 s42, 0", "={s42}"() #0
1755  %sgpr43 = tail call i32 asm sideeffect "s_mov_b32 s43, 0", "={s43}"() #0
1756  %sgpr44 = tail call i32 asm sideeffect "s_mov_b32 s44, 0", "={s44}"() #0
1757  %sgpr45 = tail call i32 asm sideeffect "s_mov_b32 s45, 0", "={s45}"() #0
1758  %sgpr46 = tail call i32 asm sideeffect "s_mov_b32 s46, 0", "={s46}"() #0
1759  %sgpr47 = tail call i32 asm sideeffect "s_mov_b32 s47, 0", "={s47}"() #0
1760  %sgpr48 = tail call i32 asm sideeffect "s_mov_b32 s48, 0", "={s48}"() #0
1761  %sgpr49 = tail call i32 asm sideeffect "s_mov_b32 s49, 0", "={s49}"() #0
1762  %sgpr50 = tail call i32 asm sideeffect "s_mov_b32 s50, 0", "={s50}"() #0
1763  %sgpr51 = tail call i32 asm sideeffect "s_mov_b32 s51, 0", "={s51}"() #0
1764  %sgpr52 = tail call i32 asm sideeffect "s_mov_b32 s52, 0", "={s52}"() #0
1765  %sgpr53 = tail call i32 asm sideeffect "s_mov_b32 s53, 0", "={s53}"() #0
1766  %sgpr54 = tail call i32 asm sideeffect "s_mov_b32 s54, 0", "={s54}"() #0
1767  %sgpr55 = tail call i32 asm sideeffect "s_mov_b32 s55, 0", "={s55}"() #0
1768  %sgpr56 = tail call i32 asm sideeffect "s_mov_b32 s56, 0", "={s56}"() #0
1769  %sgpr57 = tail call i32 asm sideeffect "s_mov_b32 s57, 0", "={s57}"() #0
1770  %sgpr58 = tail call i32 asm sideeffect "s_mov_b32 s58, 0", "={s58}"() #0
1771  %sgpr59 = tail call i32 asm sideeffect "s_mov_b32 s59, 0", "={s59}"() #0
1772  %sgpr60 = tail call i32 asm sideeffect "s_mov_b32 s60, 0", "={s60}"() #0
1773  %sgpr61 = tail call i32 asm sideeffect "s_mov_b32 s61, 0", "={s61}"() #0
1774  %sgpr62 = tail call i32 asm sideeffect "s_mov_b32 s62, 0", "={s62}"() #0
1775  %sgpr63 = tail call i32 asm sideeffect "s_mov_b32 s63, 0", "={s63}"() #0
1776  %sgpr64 = tail call i32 asm sideeffect "s_mov_b32 s64, 0", "={s64}"() #0
1777  %sgpr65 = tail call i32 asm sideeffect "s_mov_b32 s65, 0", "={s65}"() #0
1778  %sgpr66 = tail call i32 asm sideeffect "s_mov_b32 s66, 0", "={s66}"() #0
1779  %sgpr67 = tail call i32 asm sideeffect "s_mov_b32 s67, 0", "={s67}"() #0
1780  %sgpr68 = tail call i32 asm sideeffect "s_mov_b32 s68, 0", "={s68}"() #0
1781  %sgpr69 = tail call i32 asm sideeffect "s_mov_b32 s69, 0", "={s69}"() #0
1782  %sgpr70 = tail call i32 asm sideeffect "s_mov_b32 s70, 0", "={s70}"() #0
1783  %sgpr71 = tail call i32 asm sideeffect "s_mov_b32 s71, 0", "={s71}"() #0
1784  %sgpr72 = tail call i32 asm sideeffect "s_mov_b32 s72, 0", "={s72}"() #0
1785  %sgpr73 = tail call i32 asm sideeffect "s_mov_b32 s73, 0", "={s73}"() #0
1786  %sgpr74 = tail call i32 asm sideeffect "s_mov_b32 s74, 0", "={s74}"() #0
1787  %sgpr75 = tail call i32 asm sideeffect "s_mov_b32 s75, 0", "={s75}"() #0
1788  %sgpr76 = tail call i32 asm sideeffect "s_mov_b32 s76, 0", "={s76}"() #0
1789  %sgpr77 = tail call i32 asm sideeffect "s_mov_b32 s77, 0", "={s77}"() #0
1790  %sgpr78 = tail call i32 asm sideeffect "s_mov_b32 s78, 0", "={s78}"() #0
1791  %sgpr79 = tail call i32 asm sideeffect "s_mov_b32 s79, 0", "={s79}"() #0
1792  %sgpr80 = tail call i32 asm sideeffect "s_mov_b32 s80, 0", "={s80}"() #0
1793  %sgpr81 = tail call i32 asm sideeffect "s_mov_b32 s81, 0", "={s81}"() #0
1794  %sgpr82 = tail call i32 asm sideeffect "s_mov_b32 s82, 0", "={s82}"() #0
1795  %sgpr83 = tail call i32 asm sideeffect "s_mov_b32 s83, 0", "={s83}"() #0
1796  %sgpr84 = tail call i32 asm sideeffect "s_mov_b32 s84, 0", "={s84}"() #0
1797  %sgpr85 = tail call i32 asm sideeffect "s_mov_b32 s85, 0", "={s85}"() #0
1798  %sgpr86 = tail call i32 asm sideeffect "s_mov_b32 s86, 0", "={s86}"() #0
1799  %sgpr87 = tail call i32 asm sideeffect "s_mov_b32 s87, 0", "={s87}"() #0
1800  %sgpr88 = tail call i32 asm sideeffect "s_mov_b32 s88, 0", "={s88}"() #0
1801  %sgpr89 = tail call i32 asm sideeffect "s_mov_b32 s89, 0", "={s89}"() #0
1802  %sgpr90 = tail call i32 asm sideeffect "s_mov_b32 s90, 0", "={s90}"() #0
1803  %sgpr91 = tail call i32 asm sideeffect "s_mov_b32 s91, 0", "={s91}"() #0
1804  %sgpr92 = tail call i32 asm sideeffect "s_mov_b32 s92, 0", "={s92}"() #0
1805  %sgpr93 = tail call i32 asm sideeffect "s_mov_b32 s93, 0", "={s93}"() #0
1806  %sgpr94 = tail call i32 asm sideeffect "s_mov_b32 s94, 0", "={s94}"() #0
1807  %sgpr95 = tail call i32 asm sideeffect "s_mov_b32 s95, 0", "={s95}"() #0
1808  %sgpr96 = tail call i32 asm sideeffect "s_mov_b32 s96, 0", "={s96}"() #0
1809  %sgpr97 = tail call i32 asm sideeffect "s_mov_b32 s97, 0", "={s97}"() #0
1810  %sgpr98 = tail call i32 asm sideeffect "s_mov_b32 s98, 0", "={s98}"() #0
1811  %sgpr99 = tail call i32 asm sideeffect "s_mov_b32 s99, 0", "={s99}"() #0
1812  %sgpr100 = tail call i32 asm sideeffect "s_mov_b32 s100, 0", "={s100}"() #0
1813  %sgpr101 = tail call i32 asm sideeffect "s_mov_b32 s101, 0", "={s101}"() #0
1814  %vcc_lo = tail call i32 asm sideeffect "s_mov_b32 $0, 0", "={vcc_lo}"() #0
1815  %vcc_hi = tail call i32 asm sideeffect "s_mov_b32 $0, 0", "={vcc_hi}"() #0
1816  %cmp = icmp eq i32 %cnd, 0
1817  br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
1818
1819bb2: ; 68 bytes
1820  ; 64 byte asm
1821  call void asm sideeffect
1822   "v_nop_e64
1823    v_nop_e64
1824    v_nop_e64
1825    v_nop_e64
1826    v_nop_e64
1827    v_nop_e64
1828    v_nop_e64
1829    v_nop_e64",""() #0
1830  br label %bb3
1831
1832bb3:
1833  tail call void asm sideeffect "; reg use $0", "{s0}"(i32 %sgpr0) #0
1834  tail call void asm sideeffect "; reg use $0", "{s1}"(i32 %sgpr1) #0
1835  tail call void asm sideeffect "; reg use $0", "{s2}"(i32 %sgpr2) #0
1836  tail call void asm sideeffect "; reg use $0", "{s3}"(i32 %sgpr3) #0
1837  tail call void asm sideeffect "; reg use $0", "{s4}"(i32 %sgpr4) #0
1838  tail call void asm sideeffect "; reg use $0", "{s5}"(i32 %sgpr5) #0
1839  tail call void asm sideeffect "; reg use $0", "{s6}"(i32 %sgpr6) #0
1840  tail call void asm sideeffect "; reg use $0", "{s7}"(i32 %sgpr7) #0
1841  tail call void asm sideeffect "; reg use $0", "{s8}"(i32 %sgpr8) #0
1842  tail call void asm sideeffect "; reg use $0", "{s9}"(i32 %sgpr9) #0
1843  tail call void asm sideeffect "; reg use $0", "{s10}"(i32 %sgpr10) #0
1844  tail call void asm sideeffect "; reg use $0", "{s11}"(i32 %sgpr11) #0
1845  tail call void asm sideeffect "; reg use $0", "{s12}"(i32 %sgpr12) #0
1846  tail call void asm sideeffect "; reg use $0", "{s13}"(i32 %sgpr13) #0
1847  tail call void asm sideeffect "; reg use $0", "{s14}"(i32 %sgpr14) #0
1848  tail call void asm sideeffect "; reg use $0", "{s15}"(i32 %sgpr15) #0
1849  tail call void asm sideeffect "; reg use $0", "{s16}"(i32 %sgpr16) #0
1850  tail call void asm sideeffect "; reg use $0", "{s17}"(i32 %sgpr17) #0
1851  tail call void asm sideeffect "; reg use $0", "{s18}"(i32 %sgpr18) #0
1852  tail call void asm sideeffect "; reg use $0", "{s19}"(i32 %sgpr19) #0
1853  tail call void asm sideeffect "; reg use $0", "{s20}"(i32 %sgpr20) #0
1854  tail call void asm sideeffect "; reg use $0", "{s21}"(i32 %sgpr21) #0
1855  tail call void asm sideeffect "; reg use $0", "{s22}"(i32 %sgpr22) #0
1856  tail call void asm sideeffect "; reg use $0", "{s23}"(i32 %sgpr23) #0
1857  tail call void asm sideeffect "; reg use $0", "{s24}"(i32 %sgpr24) #0
1858  tail call void asm sideeffect "; reg use $0", "{s25}"(i32 %sgpr25) #0
1859  tail call void asm sideeffect "; reg use $0", "{s26}"(i32 %sgpr26) #0
1860  tail call void asm sideeffect "; reg use $0", "{s27}"(i32 %sgpr27) #0
1861  tail call void asm sideeffect "; reg use $0", "{s28}"(i32 %sgpr28) #0
1862  tail call void asm sideeffect "; reg use $0", "{s29}"(i32 %sgpr29) #0
1863  tail call void asm sideeffect "; reg use $0", "{s30}"(i32 %sgpr30) #0
1864  tail call void asm sideeffect "; reg use $0", "{s31}"(i32 %sgpr31) #0
1865  tail call void asm sideeffect "; reg use $0", "{s32}"(i32 %sgpr32) #0
1866  tail call void asm sideeffect "; reg use $0", "{s33}"(i32 %sgpr33) #0
1867  tail call void asm sideeffect "; reg use $0", "{s34}"(i32 %sgpr34) #0
1868  tail call void asm sideeffect "; reg use $0", "{s35}"(i32 %sgpr35) #0
1869  tail call void asm sideeffect "; reg use $0", "{s36}"(i32 %sgpr36) #0
1870  tail call void asm sideeffect "; reg use $0", "{s37}"(i32 %sgpr37) #0
1871  tail call void asm sideeffect "; reg use $0", "{s38}"(i32 %sgpr38) #0
1872  tail call void asm sideeffect "; reg use $0", "{s39}"(i32 %sgpr39) #0
1873  tail call void asm sideeffect "; reg use $0", "{s40}"(i32 %sgpr40) #0
1874  tail call void asm sideeffect "; reg use $0", "{s41}"(i32 %sgpr41) #0
1875  tail call void asm sideeffect "; reg use $0", "{s42}"(i32 %sgpr42) #0
1876  tail call void asm sideeffect "; reg use $0", "{s43}"(i32 %sgpr43) #0
1877  tail call void asm sideeffect "; reg use $0", "{s44}"(i32 %sgpr44) #0
1878  tail call void asm sideeffect "; reg use $0", "{s45}"(i32 %sgpr45) #0
1879  tail call void asm sideeffect "; reg use $0", "{s46}"(i32 %sgpr46) #0
1880  tail call void asm sideeffect "; reg use $0", "{s47}"(i32 %sgpr47) #0
1881  tail call void asm sideeffect "; reg use $0", "{s48}"(i32 %sgpr48) #0
1882  tail call void asm sideeffect "; reg use $0", "{s49}"(i32 %sgpr49) #0
1883  tail call void asm sideeffect "; reg use $0", "{s50}"(i32 %sgpr50) #0
1884  tail call void asm sideeffect "; reg use $0", "{s51}"(i32 %sgpr51) #0
1885  tail call void asm sideeffect "; reg use $0", "{s52}"(i32 %sgpr52) #0
1886  tail call void asm sideeffect "; reg use $0", "{s53}"(i32 %sgpr53) #0
1887  tail call void asm sideeffect "; reg use $0", "{s54}"(i32 %sgpr54) #0
1888  tail call void asm sideeffect "; reg use $0", "{s55}"(i32 %sgpr55) #0
1889  tail call void asm sideeffect "; reg use $0", "{s56}"(i32 %sgpr56) #0
1890  tail call void asm sideeffect "; reg use $0", "{s57}"(i32 %sgpr57) #0
1891  tail call void asm sideeffect "; reg use $0", "{s58}"(i32 %sgpr58) #0
1892  tail call void asm sideeffect "; reg use $0", "{s59}"(i32 %sgpr59) #0
1893  tail call void asm sideeffect "; reg use $0", "{s60}"(i32 %sgpr60) #0
1894  tail call void asm sideeffect "; reg use $0", "{s61}"(i32 %sgpr61) #0
1895  tail call void asm sideeffect "; reg use $0", "{s62}"(i32 %sgpr62) #0
1896  tail call void asm sideeffect "; reg use $0", "{s63}"(i32 %sgpr63) #0
1897  tail call void asm sideeffect "; reg use $0", "{s64}"(i32 %sgpr64) #0
1898  tail call void asm sideeffect "; reg use $0", "{s65}"(i32 %sgpr65) #0
1899  tail call void asm sideeffect "; reg use $0", "{s66}"(i32 %sgpr66) #0
1900  tail call void asm sideeffect "; reg use $0", "{s67}"(i32 %sgpr67) #0
1901  tail call void asm sideeffect "; reg use $0", "{s68}"(i32 %sgpr68) #0
1902  tail call void asm sideeffect "; reg use $0", "{s69}"(i32 %sgpr69) #0
1903  tail call void asm sideeffect "; reg use $0", "{s70}"(i32 %sgpr70) #0
1904  tail call void asm sideeffect "; reg use $0", "{s71}"(i32 %sgpr71) #0
1905  tail call void asm sideeffect "; reg use $0", "{s72}"(i32 %sgpr72) #0
1906  tail call void asm sideeffect "; reg use $0", "{s73}"(i32 %sgpr73) #0
1907  tail call void asm sideeffect "; reg use $0", "{s74}"(i32 %sgpr74) #0
1908  tail call void asm sideeffect "; reg use $0", "{s75}"(i32 %sgpr75) #0
1909  tail call void asm sideeffect "; reg use $0", "{s76}"(i32 %sgpr76) #0
1910  tail call void asm sideeffect "; reg use $0", "{s77}"(i32 %sgpr77) #0
1911  tail call void asm sideeffect "; reg use $0", "{s78}"(i32 %sgpr78) #0
1912  tail call void asm sideeffect "; reg use $0", "{s79}"(i32 %sgpr79) #0
1913  tail call void asm sideeffect "; reg use $0", "{s80}"(i32 %sgpr80) #0
1914  tail call void asm sideeffect "; reg use $0", "{s81}"(i32 %sgpr81) #0
1915  tail call void asm sideeffect "; reg use $0", "{s82}"(i32 %sgpr82) #0
1916  tail call void asm sideeffect "; reg use $0", "{s83}"(i32 %sgpr83) #0
1917  tail call void asm sideeffect "; reg use $0", "{s84}"(i32 %sgpr84) #0
1918  tail call void asm sideeffect "; reg use $0", "{s85}"(i32 %sgpr85) #0
1919  tail call void asm sideeffect "; reg use $0", "{s86}"(i32 %sgpr86) #0
1920  tail call void asm sideeffect "; reg use $0", "{s87}"(i32 %sgpr87) #0
1921  tail call void asm sideeffect "; reg use $0", "{s88}"(i32 %sgpr88) #0
1922  tail call void asm sideeffect "; reg use $0", "{s89}"(i32 %sgpr89) #0
1923  tail call void asm sideeffect "; reg use $0", "{s90}"(i32 %sgpr90) #0
1924  tail call void asm sideeffect "; reg use $0", "{s91}"(i32 %sgpr91) #0
1925  tail call void asm sideeffect "; reg use $0", "{s92}"(i32 %sgpr92) #0
1926  tail call void asm sideeffect "; reg use $0", "{s93}"(i32 %sgpr93) #0
1927  tail call void asm sideeffect "; reg use $0", "{s94}"(i32 %sgpr94) #0
1928  tail call void asm sideeffect "; reg use $0", "{s95}"(i32 %sgpr95) #0
1929  tail call void asm sideeffect "; reg use $0", "{s96}"(i32 %sgpr96) #0
1930  tail call void asm sideeffect "; reg use $0", "{s97}"(i32 %sgpr97) #0
1931  tail call void asm sideeffect "; reg use $0", "{s98}"(i32 %sgpr98) #0
1932  tail call void asm sideeffect "; reg use $0", "{s99}"(i32 %sgpr99) #0
1933  tail call void asm sideeffect "; reg use $0", "{s100}"(i32 %sgpr100) #0
1934  tail call void asm sideeffect "; reg use $0", "{s101}"(i32 %sgpr101) #0
1935  tail call void asm sideeffect "; reg use $0", "{vcc_lo}"(i32 %vcc_lo) #0
1936  tail call void asm sideeffect "; reg use $0", "{vcc_hi}"(i32 %vcc_hi) #0
1937  ret void
1938}
1939
1940declare i32 @llvm.amdgcn.workgroup.id.x() #0
1941
1942attributes #0 = { nounwind }
1943