1; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 < %s | FileCheck -check-prefix=GCN %s 2 3; Restrict maximum branch to between +15 and -16 dwords 4 5; Instructions inside a bundle were collectively counted as 6; 0-bytes. Make sure this is accounted for when estimating branch 7; distances 8 9; Bundle used for address in call sequence: 20 bytes 10; s_getpc_b64 11; s_add_u32 12; s_addc_u32 13 14; plus additional overhead 15; s_setpc_b64 16; and some register copies 17 18declare void @func() #0 19 20; GCN-LABEL: {{^}}bundle_size: 21; GCN: s_cbranch_scc0 [[BB_EXPANSION:.LBB[0-9]+_[0-9]+]] 22; GCN: s_getpc_b64 23; GCN-NEXT: .Lpost_getpc{{[0-9]+}}:{{$}} 24; GCN-NEXT: s_add_u32 25; GCN-NEXT: s_addc_u32 26; GCN-NEXT: s_setpc_b64 27 28; GCN: {{^}}[[BB_EXPANSION]]: 29; GCN: s_getpc_b64 30; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, func@ 31; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, func@ 32; GCN: s_swappc_b64 33define amdgpu_kernel void @bundle_size(ptr addrspace(1) %arg, i32 %cnd) #0 { 34bb: 35 %cmp = icmp eq i32 %cnd, 0 36 br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch 37 38bb2: 39 call void @func() 40 call void asm sideeffect 41 "v_nop_e64 42 v_nop_e64 43 v_nop_e64 44 v_nop_e64 45 v_nop_e64", ""() #0 46 br label %bb3 47 48bb3: 49 store volatile i32 %cnd, ptr addrspace(1) %arg 50 ret void 51} 52 53attributes #0 = { nounwind } 54attributes #1 = { nounwind readnone } 55