1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s 3 4# Testcase variants from 5# liveout-implicit-def-subreg-redef-blender-verifier-error.mir which 6# hit other verifier errors after coalescing. 7 8# Same as previous, except the initial value isn't an implicit_def 9--- 10name: liveout_defined_register_redefine_sub0_implicit_def 11tracksRegLiveness: true 12body: | 13 ; CHECK-LABEL: name: liveout_defined_register_redefine_sub0_implicit_def 14 ; CHECK: bb.0: 15 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) 16 ; CHECK-NEXT: {{ $}} 17 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc 18 ; CHECK-NEXT: {{ $}} 19 ; CHECK-NEXT: bb.1: 20 ; CHECK-NEXT: successors: %bb.3(0x80000000) 21 ; CHECK-NEXT: {{ $}} 22 ; CHECK-NEXT: S_NOP 0, implicit-def %0 23 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0 24 ; CHECK-NEXT: S_BRANCH %bb.3 25 ; CHECK-NEXT: {{ $}} 26 ; CHECK-NEXT: bb.2: 27 ; CHECK-NEXT: successors: %bb.3(0x80000000) 28 ; CHECK-NEXT: {{ $}} 29 ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF 30 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = IMPLICIT_DEF 31 ; CHECK-NEXT: {{ $}} 32 ; CHECK-NEXT: bb.3: 33 ; CHECK-NEXT: S_NOP 0, implicit [[DEF]] 34 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub0 35 ; CHECK-NEXT: S_ENDPGM 0 36 bb.0: 37 S_CBRANCH_SCC0 %bb.2, implicit undef $scc 38 39 bb.1: 40 S_NOP 0, implicit-def %0:sgpr_128 41 %1:sgpr_32 = S_MOV_B32 0 42 S_BRANCH %bb.3 43 44 bb.2: 45 undef %0.sub0:sgpr_128 = IMPLICIT_DEF 46 %1:sgpr_32 = COPY %0.sub0 47 48 bb.3: 49 S_NOP 0, implicit %0 50 S_NOP 0, implicit %1 51 S_ENDPGM 0 52 53... 54 55# Compare with first 56--- 57name: second_def_is_real 58tracksRegLiveness: true 59body: | 60 ; CHECK-LABEL: name: second_def_is_real 61 ; CHECK: bb.0: 62 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) 63 ; CHECK-NEXT: {{ $}} 64 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc 65 ; CHECK-NEXT: {{ $}} 66 ; CHECK-NEXT: bb.1: 67 ; CHECK-NEXT: successors: %bb.3(0x80000000) 68 ; CHECK-NEXT: {{ $}} 69 ; CHECK-NEXT: S_NOP 0, implicit-def %0 70 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 71 ; CHECK-NEXT: S_BRANCH %bb.3 72 ; CHECK-NEXT: {{ $}} 73 ; CHECK-NEXT: bb.2: 74 ; CHECK-NEXT: successors: %bb.3(0x80000000) 75 ; CHECK-NEXT: {{ $}} 76 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 123 77 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 123 78 ; CHECK-NEXT: {{ $}} 79 ; CHECK-NEXT: bb.3: 80 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]] 81 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]] 82 ; CHECK-NEXT: S_ENDPGM 0 83 bb.0: 84 S_CBRANCH_SCC0 %bb.2, implicit undef $scc 85 86 bb.1: 87 S_NOP 0, implicit-def %0:sgpr_128 88 %1:sgpr_32 = S_MOV_B32 0 89 S_BRANCH %bb.3 90 91 bb.2: 92 undef %0.sub0:sgpr_128 = S_MOV_B32 123 93 %1:sgpr_32 = COPY %0.sub0 94 95 bb.3: 96 S_NOP 0, implicit %0 97 S_NOP 0, implicit %1 98 S_ENDPGM 0 99 100... 101