1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 3 4define amdgpu_kernel void @s_clear_msb(ptr addrspace(1) %out, i32 %in) { 5; SI-LABEL: s_clear_msb: 6; SI: ; %bb.0: 7; SI-NEXT: s_load_dword s6, s[4:5], 0xb 8; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 9; SI-NEXT: s_mov_b32 s3, 0xf000 10; SI-NEXT: s_mov_b32 s2, -1 11; SI-NEXT: s_waitcnt lgkmcnt(0) 12; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff 13; SI-NEXT: v_mov_b32_e32 v0, s4 14; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 15; SI-NEXT: s_endpgm 16 %x = and i32 %in, 2147483647 17 store i32 %x, ptr addrspace(1) %out 18 ret void 19} 20 21define amdgpu_kernel void @s_set_msb(ptr addrspace(1) %out, i32 %in) { 22; SI-LABEL: s_set_msb: 23; SI: ; %bb.0: 24; SI-NEXT: s_load_dword s6, s[4:5], 0xb 25; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 26; SI-NEXT: s_mov_b32 s3, 0xf000 27; SI-NEXT: s_mov_b32 s2, -1 28; SI-NEXT: s_waitcnt lgkmcnt(0) 29; SI-NEXT: s_or_b32 s4, s6, 0x80000000 30; SI-NEXT: v_mov_b32_e32 v0, s4 31; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 32; SI-NEXT: s_endpgm 33 %x = or i32 %in, 2147483648 34 store i32 %x, ptr addrspace(1) %out 35 ret void 36} 37 38define amdgpu_kernel void @s_clear_lsb(ptr addrspace(1) %out, i32 %in) { 39; SI-LABEL: s_clear_lsb: 40; SI: ; %bb.0: 41; SI-NEXT: s_load_dword s6, s[4:5], 0xb 42; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 43; SI-NEXT: s_mov_b32 s3, 0xf000 44; SI-NEXT: s_mov_b32 s2, -1 45; SI-NEXT: s_waitcnt lgkmcnt(0) 46; SI-NEXT: s_and_b32 s4, s6, -2 47; SI-NEXT: v_mov_b32_e32 v0, s4 48; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 49; SI-NEXT: s_endpgm 50 %x = and i32 %in, 4294967294 51 store i32 %x, ptr addrspace(1) %out 52 ret void 53} 54 55define amdgpu_kernel void @s_set_lsb(ptr addrspace(1) %out, i32 %in) { 56; SI-LABEL: s_set_lsb: 57; SI: ; %bb.0: 58; SI-NEXT: s_load_dword s6, s[4:5], 0xb 59; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 60; SI-NEXT: s_mov_b32 s3, 0xf000 61; SI-NEXT: s_mov_b32 s2, -1 62; SI-NEXT: s_waitcnt lgkmcnt(0) 63; SI-NEXT: s_or_b32 s4, s6, 1 64; SI-NEXT: v_mov_b32_e32 v0, s4 65; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 66; SI-NEXT: s_endpgm 67 %x = or i32 %in, 1 68 store i32 %x, ptr addrspace(1) %out 69 ret void 70} 71 72define amdgpu_kernel void @s_clear_midbit(ptr addrspace(1) %out, i32 %in) { 73; SI-LABEL: s_clear_midbit: 74; SI: ; %bb.0: 75; SI-NEXT: s_load_dword s6, s[4:5], 0xb 76; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 77; SI-NEXT: s_mov_b32 s3, 0xf000 78; SI-NEXT: s_mov_b32 s2, -1 79; SI-NEXT: s_waitcnt lgkmcnt(0) 80; SI-NEXT: s_and_b32 s4, s6, 0xfffffeff 81; SI-NEXT: v_mov_b32_e32 v0, s4 82; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 83; SI-NEXT: s_endpgm 84 %x = and i32 %in, 4294967039 85 store i32 %x, ptr addrspace(1) %out 86 ret void 87} 88 89define amdgpu_kernel void @s_set_midbit(ptr addrspace(1) %out, i32 %in) { 90; SI-LABEL: s_set_midbit: 91; SI: ; %bb.0: 92; SI-NEXT: s_load_dword s6, s[4:5], 0xb 93; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 94; SI-NEXT: s_mov_b32 s3, 0xf000 95; SI-NEXT: s_mov_b32 s2, -1 96; SI-NEXT: s_waitcnt lgkmcnt(0) 97; SI-NEXT: s_or_b32 s4, s6, 0x100 98; SI-NEXT: v_mov_b32_e32 v0, s4 99; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 100; SI-NEXT: s_endpgm 101 %x = or i32 %in, 256 102 store i32 %x, ptr addrspace(1) %out 103 ret void 104} 105 106@gv = external addrspace(1) global i32 107 108; Make sure there's no verifier error with an undef source. 109define void @bitset_verifier_error() local_unnamed_addr #0 { 110; SI-LABEL: bitset_verifier_error: 111; SI: ; %bb.0: ; %bb 112; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 113; SI-NEXT: s_getpc_b64 s[4:5] 114; SI-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4 115; SI-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12 116; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 117; SI-NEXT: s_mov_b32 s7, 0xf000 118; SI-NEXT: s_mov_b32 s6, -1 119; SI-NEXT: s_waitcnt lgkmcnt(0) 120; SI-NEXT: s_and_b32 s8, s4, 0x7fffffff 121; SI-NEXT: v_mov_b32_e32 v0, s8 122; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 123; SI-NEXT: s_waitcnt expcnt(0) 124; SI-NEXT: v_mov_b32_e32 v0, 0x3f7fbe77 125; SI-NEXT: v_cmp_ge_f32_e64 s[4:5], |s4|, v0 126; SI-NEXT: s_and_b64 vcc, exec, s[4:5] 127; SI-NEXT: s_cbranch_vccnz .LBB6_2 128; SI-NEXT: ; %bb.1: ; %bb5 129; SI-NEXT: .LBB6_2: ; %bb6 130bb: 131 %i = call float @llvm.fabs.f32(float undef) #0 132 %i1 = bitcast float %i to i32 133 store i32 %i1, ptr addrspace(1) @gv 134 br label %bb2 135 136bb2: 137 %i3 = call float @llvm.fabs.f32(float undef) #0 138 %i4 = fcmp fast ult float %i3, 0x3FEFF7CEE0000000 139 br i1 %i4, label %bb5, label %bb6 140 141bb5: 142 unreachable 143 144bb6: 145 unreachable 146} 147 148declare float @llvm.fabs.f32(float) #0 149 150attributes #0 = { nounwind readnone speculatable willreturn } 151