1; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s 2; RUN: llc -global-isel -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s 3 4; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s 5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s 6 7; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s 8 9; Legacy intrinsics that just read implicit parameters 10 11; FUNC-LABEL: {{^}}ngroups_x: 12; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x0 13; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x0 14; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 15; GCN-NOHSA: buffer_store_dword [[VVAL]] 16 17; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 18; EG: MOV {{\*? *}}[[VAL]], KC0[0].X 19define amdgpu_kernel void @ngroups_x (ptr addrspace(1) %out) { 20entry: 21 %0 = call i32 @llvm.r600.read.ngroups.x() #0 22 store i32 %0, ptr addrspace(1) %out 23 ret void 24} 25 26; FUNC-LABEL: {{^}}ngroups_y: 27; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x1 28; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x4 29; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 30; GCN-NOHSA: buffer_store_dword [[VVAL]] 31 32; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 33; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y 34define amdgpu_kernel void @ngroups_y (ptr addrspace(1) %out) { 35entry: 36 %0 = call i32 @llvm.r600.read.ngroups.y() #0 37 store i32 %0, ptr addrspace(1) %out 38 ret void 39} 40 41; FUNC-LABEL: {{^}}ngroups_z: 42; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x2 43; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x8 44; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 45; GCN-NOHSA: buffer_store_dword [[VVAL]] 46 47; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 48; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z 49define amdgpu_kernel void @ngroups_z (ptr addrspace(1) %out) { 50entry: 51 %0 = call i32 @llvm.r600.read.ngroups.z() #0 52 store i32 %0, ptr addrspace(1) %out 53 ret void 54} 55 56; FUNC-LABEL: {{^}}global_size_x: 57; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x3 58; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0xc 59; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 60; GCN-NOHSA: buffer_store_dword [[VVAL]] 61 62; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 63; EG: MOV {{\*? *}}[[VAL]], KC0[0].W 64define amdgpu_kernel void @global_size_x (ptr addrspace(1) %out) { 65entry: 66 %0 = call i32 @llvm.r600.read.global.size.x() #0 67 store i32 %0, ptr addrspace(1) %out 68 ret void 69} 70 71; FUNC-LABEL: {{^}}global_size_y: 72; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x4 73; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x10 74; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 75; GCN-NOHSA: buffer_store_dword [[VVAL]] 76 77; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 78; EG: MOV {{\*? *}}[[VAL]], KC0[1].X 79define amdgpu_kernel void @global_size_y (ptr addrspace(1) %out) { 80entry: 81 %0 = call i32 @llvm.r600.read.global.size.y() #0 82 store i32 %0, ptr addrspace(1) %out 83 ret void 84} 85 86; FUNC-LABEL: {{^}}global_size_z: 87; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x5 88; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x14 89; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 90; GCN-NOHSA: buffer_store_dword [[VVAL]] 91 92; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 93; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y 94define amdgpu_kernel void @global_size_z (ptr addrspace(1) %out) { 95entry: 96 %0 = call i32 @llvm.r600.read.global.size.z() #0 97 store i32 %0, ptr addrspace(1) %out 98 ret void 99} 100 101; FUNC-LABEL: {{^}}local_size_x: 102; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x6 103; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x18 104; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 105; GCN-NOHSA: buffer_store_dword [[VVAL]] 106 107; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 108; EG: MOV {{\*? *}}[[VAL]], KC0[1].Z 109define amdgpu_kernel void @local_size_x (ptr addrspace(1) %out) { 110entry: 111 %0 = call i32 @llvm.r600.read.local.size.x() #0 112 store i32 %0, ptr addrspace(1) %out 113 ret void 114} 115 116; FUNC-LABEL: {{^}}local_size_y: 117; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x7 118; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x1c 119; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 120; GCN-NOHSA: buffer_store_dword [[VVAL]] 121 122; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 123; EG: MOV {{\*? *}}[[VAL]], KC0[1].W 124define amdgpu_kernel void @local_size_y (ptr addrspace(1) %out) { 125entry: 126 %0 = call i32 @llvm.r600.read.local.size.y() #0 127 store i32 %0, ptr addrspace(1) %out 128 ret void 129} 130 131; FUNC-LABEL: {{^}}local_size_z: 132; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x8 133; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[4:5], 0x20 134; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 135; GCN-NOHSA: buffer_store_dword [[VVAL]] 136 137; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] 138; EG: MOV {{\*? *}}[[VAL]], KC0[2].X 139define amdgpu_kernel void @local_size_z (ptr addrspace(1) %out) { 140entry: 141 %0 = call i32 @llvm.r600.read.local.size.z() #0 142 store i32 %0, ptr addrspace(1) %out 143 ret void 144} 145 146declare i32 @llvm.r600.read.ngroups.x() #0 147declare i32 @llvm.r600.read.ngroups.y() #0 148declare i32 @llvm.r600.read.ngroups.z() #0 149 150declare i32 @llvm.r600.read.global.size.x() #0 151declare i32 @llvm.r600.read.global.size.y() #0 152declare i32 @llvm.r600.read.global.size.z() #0 153 154declare i32 @llvm.r600.read.local.size.x() #0 155declare i32 @llvm.r600.read.local.size.y() #0 156declare i32 @llvm.r600.read.local.size.z() #0 157 158attributes #0 = { readnone } 159