1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s 3 4target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" 5 6declare float @_Z4pownfi(float, i32) 7declare <2 x float> @_Z4pownDv2_fDv2_i(<2 x float>, <2 x i32>) 8declare <3 x float> @_Z4pownDv3_fDv3_i(<3 x float>, <3 x i32>) 9declare <4 x float> @_Z4pownDv4_fDv4_i(<4 x float>, <4 x i32>) 10declare <8 x float> @_Z4pownDv8_fDv8_i(<8 x float>, <8 x i32>) 11declare <16 x float> @_Z4pownDv16_fDv16_i(<16 x float>, <16 x i32>) 12declare double @_Z4powndi(double, i32) 13declare <2 x double> @_Z4pownDv2_dDv2_i(<2 x double>, <2 x i32>) 14declare <3 x double> @_Z4pownDv3_dDv3_i(<3 x double>, <3 x i32>) 15declare <4 x double> @_Z4pownDv4_dDv4_i(<4 x double>, <4 x i32>) 16declare <8 x double> @_Z4pownDv8_dDv8_i(<8 x double>, <8 x i32>) 17declare <16 x double> @_Z4pownDv16_dDv16_i(<16 x double>, <16 x i32>) 18declare half @_Z4pownDhi(half, i32) 19declare <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half>, <2 x i32>) 20declare <3 x half> @_Z4pownDv3_DhDv3_i(<3 x half>, <3 x i32>) 21declare <4 x half> @_Z4pownDv4_DhDv4_i(<4 x half>, <4 x i32>) 22declare <8 x half> @_Z4pownDv8_DhDv8_i(<8 x half>, <8 x i32>) 23declare <16 x half> @_Z4pownDv16_DhDv16_i(<16 x half>, <16 x i32>) 24 25define float @test_pown_f32(float %x, i32 %y) { 26; CHECK-LABEL: define float @test_pown_f32 27; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) { 28; CHECK-NEXT: entry: 29; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[Y]]) 30; CHECK-NEXT: ret float [[CALL]] 31; 32entry: 33 %call = tail call float @_Z4pownfi(float %x, i32 %y) 34 ret float %call 35} 36 37define <2 x float> @test_pown_v2f32(<2 x float> %x, <2 x i32> %y) { 38; CHECK-LABEL: define <2 x float> @test_pown_v2f32 39; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 40; CHECK-NEXT: entry: 41; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]]) 42; CHECK-NEXT: ret <2 x float> [[CALL]] 43; 44entry: 45 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y) 46 ret <2 x float> %call 47} 48 49define <3 x float> @test_pown_v3f32(<3 x float> %x, <3 x i32> %y) { 50; CHECK-LABEL: define <3 x float> @test_pown_v3f32 51; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) { 52; CHECK-NEXT: entry: 53; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]]) 54; CHECK-NEXT: ret <3 x float> [[CALL]] 55; 56entry: 57 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> %y) 58 ret <3 x float> %call 59} 60 61define <4 x float> @test_pown_v4f32(<4 x float> %x, <4 x i32> %y) { 62; CHECK-LABEL: define <4 x float> @test_pown_v4f32 63; CHECK-SAME: (<4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) { 64; CHECK-NEXT: entry: 65; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]]) 66; CHECK-NEXT: ret <4 x float> [[CALL]] 67; 68entry: 69 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> %y) 70 ret <4 x float> %call 71} 72 73define <8 x float> @test_pown_v8f32(<8 x float> %x, <8 x i32> %y) { 74; CHECK-LABEL: define <8 x float> @test_pown_v8f32 75; CHECK-SAME: (<8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) { 76; CHECK-NEXT: entry: 77; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]]) 78; CHECK-NEXT: ret <8 x float> [[CALL]] 79; 80entry: 81 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> %y) 82 ret <8 x float> %call 83} 84 85define <16 x float> @test_pown_v16f32(<16 x float> %x, <16 x i32> %y) { 86; CHECK-LABEL: define <16 x float> @test_pown_v16f32 87; CHECK-SAME: (<16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) { 88; CHECK-NEXT: entry: 89; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]]) 90; CHECK-NEXT: ret <16 x float> [[CALL]] 91; 92entry: 93 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> %y) 94 ret <16 x float> %call 95} 96 97define double @test_pown_f64(double %x, i32 %y) { 98; CHECK-LABEL: define double @test_pown_f64 99; CHECK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) { 100; CHECK-NEXT: entry: 101; CHECK-NEXT: [[CALL:%.*]] = tail call double @_Z4powndi(double [[X]], i32 [[Y]]) 102; CHECK-NEXT: ret double [[CALL]] 103; 104entry: 105 %call = tail call double @_Z4powndi(double %x, i32 %y) 106 ret double %call 107} 108 109define <2 x double> @test_pown_v2f64(<2 x double> %x, <2 x i32> %y) { 110; CHECK-LABEL: define <2 x double> @test_pown_v2f64 111; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 112; CHECK-NEXT: entry: 113; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]]) 114; CHECK-NEXT: ret <2 x double> [[CALL]] 115; 116entry: 117 %call = tail call <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y) 118 ret <2 x double> %call 119} 120 121define <3 x double> @test_pown_v3f64(<3 x double> %x, <3 x i32> %y) { 122; CHECK-LABEL: define <3 x double> @test_pown_v3f64 123; CHECK-SAME: (<3 x double> [[X:%.*]], <3 x i32> [[Y:%.*]]) { 124; CHECK-NEXT: entry: 125; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x double> @_Z4pownDv3_dDv3_i(<3 x double> [[X]], <3 x i32> [[Y]]) 126; CHECK-NEXT: ret <3 x double> [[CALL]] 127; 128entry: 129 %call = tail call <3 x double> @_Z4pownDv3_dDv3_i(<3 x double> %x, <3 x i32> %y) 130 ret <3 x double> %call 131} 132 133define <4 x double> @test_pown_v4f64(<4 x double> %x, <4 x i32> %y) { 134; CHECK-LABEL: define <4 x double> @test_pown_v4f64 135; CHECK-SAME: (<4 x double> [[X:%.*]], <4 x i32> [[Y:%.*]]) { 136; CHECK-NEXT: entry: 137; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x double> @_Z4pownDv4_dDv4_i(<4 x double> [[X]], <4 x i32> [[Y]]) 138; CHECK-NEXT: ret <4 x double> [[CALL]] 139; 140entry: 141 %call = tail call <4 x double> @_Z4pownDv4_dDv4_i(<4 x double> %x, <4 x i32> %y) 142 ret <4 x double> %call 143} 144 145define <8 x double> @test_pown_v8f64(<8 x double> %x, <8 x i32> %y) { 146; CHECK-LABEL: define <8 x double> @test_pown_v8f64 147; CHECK-SAME: (<8 x double> [[X:%.*]], <8 x i32> [[Y:%.*]]) { 148; CHECK-NEXT: entry: 149; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x double> @_Z4pownDv8_dDv8_i(<8 x double> [[X]], <8 x i32> [[Y]]) 150; CHECK-NEXT: ret <8 x double> [[CALL]] 151; 152entry: 153 %call = tail call <8 x double> @_Z4pownDv8_dDv8_i(<8 x double> %x, <8 x i32> %y) 154 ret <8 x double> %call 155} 156 157define <16 x double> @test_pown_v16f64(<16 x double> %x, <16 x i32> %y) { 158; CHECK-LABEL: define <16 x double> @test_pown_v16f64 159; CHECK-SAME: (<16 x double> [[X:%.*]], <16 x i32> [[Y:%.*]]) { 160; CHECK-NEXT: entry: 161; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x double> @_Z4pownDv16_dDv16_i(<16 x double> [[X]], <16 x i32> [[Y]]) 162; CHECK-NEXT: ret <16 x double> [[CALL]] 163; 164entry: 165 %call = tail call <16 x double> @_Z4pownDv16_dDv16_i(<16 x double> %x, <16 x i32> %y) 166 ret <16 x double> %call 167} 168 169define half @test_pown_f16(half %x, i32 %y) { 170; CHECK-LABEL: define half @test_pown_f16 171; CHECK-SAME: (half [[X:%.*]], i32 [[Y:%.*]]) { 172; CHECK-NEXT: entry: 173; CHECK-NEXT: [[CALL:%.*]] = tail call half @_Z4pownDhi(half [[X]], i32 [[Y]]) 174; CHECK-NEXT: ret half [[CALL]] 175; 176entry: 177 %call = tail call half @_Z4pownDhi(half %x, i32 %y) 178 ret half %call 179} 180 181define <2 x half> @test_pown_v2f16(<2 x half> %x, <2 x i32> %y) { 182; CHECK-LABEL: define <2 x half> @test_pown_v2f16 183; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 184; CHECK-NEXT: entry: 185; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]]) 186; CHECK-NEXT: ret <2 x half> [[CALL]] 187; 188entry: 189 %call = tail call <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y) 190 ret <2 x half> %call 191} 192 193define <3 x half> @test_pown_v3f16(<3 x half> %x, <3 x i32> %y) { 194; CHECK-LABEL: define <3 x half> @test_pown_v3f16 195; CHECK-SAME: (<3 x half> [[X:%.*]], <3 x i32> [[Y:%.*]]) { 196; CHECK-NEXT: entry: 197; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x half> @_Z4pownDv3_DhDv3_i(<3 x half> [[X]], <3 x i32> [[Y]]) 198; CHECK-NEXT: ret <3 x half> [[CALL]] 199; 200entry: 201 %call = tail call <3 x half> @_Z4pownDv3_DhDv3_i(<3 x half> %x, <3 x i32> %y) 202 ret <3 x half> %call 203} 204 205define <4 x half> @test_pown_v4f16(<4 x half> %x, <4 x i32> %y) { 206; CHECK-LABEL: define <4 x half> @test_pown_v4f16 207; CHECK-SAME: (<4 x half> [[X:%.*]], <4 x i32> [[Y:%.*]]) { 208; CHECK-NEXT: entry: 209; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x half> @_Z4pownDv4_DhDv4_i(<4 x half> [[X]], <4 x i32> [[Y]]) 210; CHECK-NEXT: ret <4 x half> [[CALL]] 211; 212entry: 213 %call = tail call <4 x half> @_Z4pownDv4_DhDv4_i(<4 x half> %x, <4 x i32> %y) 214 ret <4 x half> %call 215} 216 217define <8 x half> @test_pown_v8f16(<8 x half> %x, <8 x i32> %y) { 218; CHECK-LABEL: define <8 x half> @test_pown_v8f16 219; CHECK-SAME: (<8 x half> [[X:%.*]], <8 x i32> [[Y:%.*]]) { 220; CHECK-NEXT: entry: 221; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x half> @_Z4pownDv8_DhDv8_i(<8 x half> [[X]], <8 x i32> [[Y]]) 222; CHECK-NEXT: ret <8 x half> [[CALL]] 223; 224entry: 225 %call = tail call <8 x half> @_Z4pownDv8_DhDv8_i(<8 x half> %x, <8 x i32> %y) 226 ret <8 x half> %call 227} 228 229define <16 x half> @test_pown_v16f16(<16 x half> %x, <16 x i32> %y) { 230; CHECK-LABEL: define <16 x half> @test_pown_v16f16 231; CHECK-SAME: (<16 x half> [[X:%.*]], <16 x i32> [[Y:%.*]]) { 232; CHECK-NEXT: entry: 233; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x half> @_Z4pownDv16_DhDv16_i(<16 x half> [[X]], <16 x i32> [[Y]]) 234; CHECK-NEXT: ret <16 x half> [[CALL]] 235; 236entry: 237 %call = tail call <16 x half> @_Z4pownDv16_DhDv16_i(<16 x half> %x, <16 x i32> %y) 238 ret <16 x half> %call 239} 240 241define float @test_pown_f32__y_0(float %x) { 242; CHECK-LABEL: define float @test_pown_f32__y_0 243; CHECK-SAME: (float [[X:%.*]]) { 244; CHECK-NEXT: entry: 245; CHECK-NEXT: ret float 1.000000e+00 246; 247entry: 248 %call = tail call float @_Z4pownfi(float %x, i32 0) 249 ret float %call 250} 251 252define float @test_pown_f32__y_poison(float %x) { 253; CHECK-LABEL: define float @test_pown_f32__y_poison 254; CHECK-SAME: (float [[X:%.*]]) { 255; CHECK-NEXT: entry: 256; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 poison) 257; CHECK-NEXT: ret float [[CALL]] 258; 259entry: 260 %call = tail call float @_Z4pownfi(float %x, i32 poison) 261 ret float %call 262} 263 264define <2 x float> @test_pown_v2f32__y_poison(<2 x float> %x) { 265; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_poison 266; CHECK-SAME: (<2 x float> [[X:%.*]]) { 267; CHECK-NEXT: entry: 268; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> poison) 269; CHECK-NEXT: ret <2 x float> [[CALL]] 270; 271entry: 272 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> poison) 273 ret <2 x float> %call 274} 275 276define <2 x float> @test_pown_v2f32__y_0(<2 x float> %x) { 277; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_0 278; CHECK-SAME: (<2 x float> [[X:%.*]]) { 279; CHECK-NEXT: entry: 280; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00) 281; 282entry: 283 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> zeroinitializer) 284 ret <2 x float> %call 285} 286 287define <2 x float> @test_pown_v2f32__y_0_undef(<2 x float> %x) { 288; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_0_undef 289; CHECK-SAME: (<2 x float> [[X:%.*]]) { 290; CHECK-NEXT: entry: 291; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00) 292; 293entry: 294 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 0, i32 poison>) 295 ret <2 x float> %call 296} 297 298define <3 x float> @test_pown_v3f32__y_0(<3 x float> %x) { 299; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_0 300; CHECK-SAME: (<3 x float> [[X:%.*]]) { 301; CHECK-NEXT: entry: 302; CHECK-NEXT: ret <3 x float> splat (float 1.000000e+00) 303; 304entry: 305 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> zeroinitializer) 306 ret <3 x float> %call 307} 308 309define <4 x float> @test_pown_v4f32__y_0(<4 x float> %x) { 310; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_0 311; CHECK-SAME: (<4 x float> [[X:%.*]]) { 312; CHECK-NEXT: entry: 313; CHECK-NEXT: ret <4 x float> splat (float 1.000000e+00) 314; 315entry: 316 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> zeroinitializer) 317 ret <4 x float> %call 318} 319 320define <8 x float> @test_pown_v8f32__y_0(<8 x float> %x) { 321; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_0 322; CHECK-SAME: (<8 x float> [[X:%.*]]) { 323; CHECK-NEXT: entry: 324; CHECK-NEXT: ret <8 x float> splat (float 1.000000e+00) 325; 326entry: 327 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> zeroinitializer) 328 ret <8 x float> %call 329} 330 331define <16 x float> @test_pown_v16f32__y_0(<16 x float> %x) { 332; CHECK-LABEL: define <16 x float> @test_pown_v16f32__y_0 333; CHECK-SAME: (<16 x float> [[X:%.*]]) { 334; CHECK-NEXT: entry: 335; CHECK-NEXT: ret <16 x float> splat (float 1.000000e+00) 336; 337entry: 338 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> zeroinitializer) 339 ret <16 x float> %call 340} 341 342define float @test_pown_f32__y_1(float %x) { 343; CHECK-LABEL: define float @test_pown_f32__y_1 344; CHECK-SAME: (float [[X:%.*]]) { 345; CHECK-NEXT: entry: 346; CHECK-NEXT: ret float [[X]] 347; 348entry: 349 %call = tail call float @_Z4pownfi(float %x, i32 1) 350 ret float %call 351} 352 353define <2 x float> @test_pown_v2f32__y_1(<2 x float> %x) { 354; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_1 355; CHECK-SAME: (<2 x float> [[X:%.*]]) { 356; CHECK-NEXT: entry: 357; CHECK-NEXT: ret <2 x float> [[X]] 358; 359entry: 360 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 1, i32 1>) 361 ret <2 x float> %call 362} 363 364define <2 x float> @test_pown_v2f32__y_1_undef(<2 x float> %x) { 365; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_1_undef 366; CHECK-SAME: (<2 x float> [[X:%.*]]) { 367; CHECK-NEXT: entry: 368; CHECK-NEXT: ret <2 x float> [[X]] 369; 370entry: 371 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 1, i32 poison>) 372 ret <2 x float> %call 373} 374 375define <3 x float> @test_pown_v3f32__y_1(<3 x float> %x) { 376; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_1 377; CHECK-SAME: (<3 x float> [[X:%.*]]) { 378; CHECK-NEXT: entry: 379; CHECK-NEXT: ret <3 x float> [[X]] 380; 381entry: 382 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 1, i32 1, i32 1>) 383 ret <3 x float> %call 384} 385 386define <3 x float> @test_pown_v3f32__y_1_undef(<3 x float> %x) { 387; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_1_undef 388; CHECK-SAME: (<3 x float> [[X:%.*]]) { 389; CHECK-NEXT: entry: 390; CHECK-NEXT: ret <3 x float> [[X]] 391; 392entry: 393 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 1, i32 1, i32 poison>) 394 ret <3 x float> %call 395} 396 397define <4 x float> @test_pown_v4f32__y_1(<4 x float> %x) { 398; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_1 399; CHECK-SAME: (<4 x float> [[X:%.*]]) { 400; CHECK-NEXT: entry: 401; CHECK-NEXT: ret <4 x float> [[X]] 402; 403entry: 404 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) 405 ret <4 x float> %call 406} 407 408define <8 x float> @test_pown_v8f32__y_1(<8 x float> %x) { 409; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_1 410; CHECK-SAME: (<8 x float> [[X:%.*]]) { 411; CHECK-NEXT: entry: 412; CHECK-NEXT: ret <8 x float> [[X]] 413; 414entry: 415 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 416 ret <8 x float> %call 417} 418 419define <16 x float> @test_pown_v16f32__y_1(<16 x float> %x) { 420; CHECK-LABEL: define <16 x float> @test_pown_v16f32__y_1 421; CHECK-SAME: (<16 x float> [[X:%.*]]) { 422; CHECK-NEXT: entry: 423; CHECK-NEXT: ret <16 x float> [[X]] 424; 425entry: 426 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>) 427 ret <16 x float> %call 428} 429 430define float @test_pown_f32__y_2(float %x) { 431; CHECK-LABEL: define float @test_pown_f32__y_2 432; CHECK-SAME: (float [[X:%.*]]) { 433; CHECK-NEXT: entry: 434; CHECK-NEXT: [[__POW2:%.*]] = fmul float [[X]], [[X]] 435; CHECK-NEXT: ret float [[__POW2]] 436; 437entry: 438 %call = tail call float @_Z4pownfi(float %x, i32 2) 439 ret float %call 440} 441 442define <2 x float> @test_pown_v2f32__y_2(<2 x float> %x) { 443; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_2 444; CHECK-SAME: (<2 x float> [[X:%.*]]) { 445; CHECK-NEXT: entry: 446; CHECK-NEXT: [[__POW2:%.*]] = fmul <2 x float> [[X]], [[X]] 447; CHECK-NEXT: ret <2 x float> [[__POW2]] 448; 449entry: 450 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 2, i32 2>) 451 ret <2 x float> %call 452} 453 454define <3 x float> @test_pown_v3f32__y_2(<3 x float> %x) { 455; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_2 456; CHECK-SAME: (<3 x float> [[X:%.*]]) { 457; CHECK-NEXT: entry: 458; CHECK-NEXT: [[__POW2:%.*]] = fmul <3 x float> [[X]], [[X]] 459; CHECK-NEXT: ret <3 x float> [[__POW2]] 460; 461entry: 462 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 2, i32 2, i32 2>) 463 ret <3 x float> %call 464} 465 466define <3 x float> @test_pown_v3f32__y_2_undef(<3 x float> %x) { 467; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_2_undef 468; CHECK-SAME: (<3 x float> [[X:%.*]]) { 469; CHECK-NEXT: entry: 470; CHECK-NEXT: [[__POW2:%.*]] = fmul <3 x float> [[X]], [[X]] 471; CHECK-NEXT: ret <3 x float> [[__POW2]] 472; 473entry: 474 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 2, i32 poison, i32 2>) 475 ret <3 x float> %call 476} 477 478define <4 x float> @test_pown_v4f32__y_2(<4 x float> %x) { 479; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_2 480; CHECK-SAME: (<4 x float> [[X:%.*]]) { 481; CHECK-NEXT: entry: 482; CHECK-NEXT: [[__POW2:%.*]] = fmul <4 x float> [[X]], [[X]] 483; CHECK-NEXT: ret <4 x float> [[__POW2]] 484; 485entry: 486 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 2, i32 2, i32 2, i32 2>) 487 ret <4 x float> %call 488} 489 490define <8 x float> @test_pown_v8f32__y_2(<8 x float> %x) { 491; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_2 492; CHECK-SAME: (<8 x float> [[X:%.*]]) { 493; CHECK-NEXT: entry: 494; CHECK-NEXT: [[__POW2:%.*]] = fmul <8 x float> [[X]], [[X]] 495; CHECK-NEXT: ret <8 x float> [[__POW2]] 496; 497entry: 498 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>) 499 ret <8 x float> %call 500} 501 502define <16 x float> @test_pown_v26f32__y_2(<16 x float> %x) { 503; CHECK-LABEL: define <16 x float> @test_pown_v26f32__y_2 504; CHECK-SAME: (<16 x float> [[X:%.*]]) { 505; CHECK-NEXT: entry: 506; CHECK-NEXT: [[__POW2:%.*]] = fmul <16 x float> [[X]], [[X]] 507; CHECK-NEXT: ret <16 x float> [[__POW2]] 508; 509entry: 510 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>) 511 ret <16 x float> %call 512} 513 514define float @test_pown_f32__y_neg1(float %x) { 515; CHECK-LABEL: define float @test_pown_f32__y_neg1 516; CHECK-SAME: (float [[X:%.*]]) { 517; CHECK-NEXT: entry: 518; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv float 1.000000e+00, [[X]] 519; CHECK-NEXT: ret float [[__POWRECIP]] 520; 521entry: 522 %call = tail call float @_Z4pownfi(float %x, i32 -1) 523 ret float %call 524} 525 526define <2 x float> @test_pown_v2f32__y_neg1(<2 x float> %x) { 527; CHECK-LABEL: define <2 x float> @test_pown_v2f32__y_neg1 528; CHECK-SAME: (<2 x float> [[X:%.*]]) { 529; CHECK-NEXT: entry: 530; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <2 x float> splat (float 1.000000e+00), [[X]] 531; CHECK-NEXT: ret <2 x float> [[__POWRECIP]] 532; 533entry: 534 %call = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -1, i32 -1>) 535 ret <2 x float> %call 536} 537 538define <3 x float> @test_pown_v3f32__y_neg1(<3 x float> %x) { 539; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_neg1 540; CHECK-SAME: (<3 x float> [[X:%.*]]) { 541; CHECK-NEXT: entry: 542; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <3 x float> splat (float 1.000000e+00), [[X]] 543; CHECK-NEXT: ret <3 x float> [[__POWRECIP]] 544; 545entry: 546 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 -1, i32 -1, i32 -1>) 547 ret <3 x float> %call 548} 549 550define <3 x float> @test_pown_v3f32__y_neg1_undef(<3 x float> %x) { 551; CHECK-LABEL: define <3 x float> @test_pown_v3f32__y_neg1_undef 552; CHECK-SAME: (<3 x float> [[X:%.*]]) { 553; CHECK-NEXT: entry: 554; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <3 x float> splat (float 1.000000e+00), [[X]] 555; CHECK-NEXT: ret <3 x float> [[__POWRECIP]] 556; 557entry: 558 %call = tail call <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 -1, i32 -1, i32 poison>) 559 ret <3 x float> %call 560} 561 562define <4 x float> @test_pown_v4f32__y_neg1(<4 x float> %x) { 563; CHECK-LABEL: define <4 x float> @test_pown_v4f32__y_neg1 564; CHECK-SAME: (<4 x float> [[X:%.*]]) { 565; CHECK-NEXT: entry: 566; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <4 x float> splat (float 1.000000e+00), [[X]] 567; CHECK-NEXT: ret <4 x float> [[__POWRECIP]] 568; 569entry: 570 %call = tail call <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>) 571 ret <4 x float> %call 572} 573 574define <8 x float> @test_pown_v8f32__y_neg1(<8 x float> %x) { 575; CHECK-LABEL: define <8 x float> @test_pown_v8f32__y_neg1 576; CHECK-SAME: (<8 x float> [[X:%.*]]) { 577; CHECK-NEXT: entry: 578; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <8 x float> splat (float 1.000000e+00), [[X]] 579; CHECK-NEXT: ret <8 x float> [[__POWRECIP]] 580; 581entry: 582 %call = tail call <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>) 583 ret <8 x float> %call 584} 585 586define <16 x float> @test_pown_v16f32__y_neg1(<16 x float> %x) { 587; CHECK-LABEL: define <16 x float> @test_pown_v16f32__y_neg1 588; CHECK-SAME: (<16 x float> [[X:%.*]]) { 589; CHECK-NEXT: entry: 590; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv <16 x float> splat (float 1.000000e+00), [[X]] 591; CHECK-NEXT: ret <16 x float> [[__POWRECIP]] 592; 593entry: 594 %call = tail call <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>) 595 ret <16 x float> %call 596} 597 598define float @test_pown_afn_f32(float %x, i32 %y) { 599; CHECK-LABEL: define float @test_pown_afn_f32 600; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) { 601; CHECK-NEXT: entry: 602; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 [[Y]]) 603; CHECK-NEXT: ret float [[CALL]] 604; 605entry: 606 %call = tail call afn float @_Z4pownfi(float %x, i32 %y) 607 ret float %call 608} 609 610define <2 x float> @test_pown_afn_v2f32(<2 x float> %x, <2 x i32> %y) { 611; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32 612; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 613; CHECK-NEXT: entry: 614; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]]) 615; CHECK-NEXT: ret <2 x float> [[CALL]] 616; 617entry: 618 %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y) 619 ret <2 x float> %call 620} 621 622define double @test_pown_afn_f64(double %x, i32 %y) { 623; CHECK-LABEL: define double @test_pown_afn_f64 624; CHECK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) { 625; CHECK-NEXT: entry: 626; CHECK-NEXT: [[CALL:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 [[Y]]) 627; CHECK-NEXT: ret double [[CALL]] 628; 629entry: 630 %call = tail call afn double @_Z4powndi(double %x, i32 %y) 631 ret double %call 632} 633 634define <2 x double> @test_pown_afn_v2f64(<2 x double> %x, <2 x i32> %y) { 635; CHECK-LABEL: define <2 x double> @test_pown_afn_v2f64 636; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 637; CHECK-NEXT: entry: 638; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]]) 639; CHECK-NEXT: ret <2 x double> [[CALL]] 640; 641entry: 642 %call = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y) 643 ret <2 x double> %call 644} 645 646define half @test_pown_afn_f16(half %x, i32 %y) { 647; CHECK-LABEL: define half @test_pown_afn_f16 648; CHECK-SAME: (half [[X:%.*]], i32 [[Y:%.*]]) { 649; CHECK-NEXT: entry: 650; CHECK-NEXT: [[CALL:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 [[Y]]) 651; CHECK-NEXT: ret half [[CALL]] 652; 653entry: 654 %call = tail call afn half @_Z4pownDhi(half %x, i32 %y) 655 ret half %call 656} 657 658define <2 x half> @test_pown_afn_v2f16(<2 x half> %x, <2 x i32> %y) { 659; CHECK-LABEL: define <2 x half> @test_pown_afn_v2f16 660; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 661; CHECK-NEXT: entry: 662; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]]) 663; CHECK-NEXT: ret <2 x half> [[CALL]] 664; 665entry: 666 %call = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y) 667 ret <2 x half> %call 668} 669 670define float @test_pown_afn_nnan_ninf_f32(float %x, i32 %y) { 671; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32 672; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) { 673; CHECK-NEXT: entry: 674; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]]) 675; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) 676; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float 677; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] 678; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) 679; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31 680; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32 681; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] 682; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 683; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]] 684; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float 685; CHECK-NEXT: ret float [[TMP3]] 686; 687entry: 688 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 %y) 689 ret float %call 690} 691 692define <2 x float> @test_pown_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y) { 693; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32 694; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 695; CHECK-NEXT: entry: 696; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]]) 697; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]]) 698; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float> 699; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]] 700; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) 701; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[Y]], splat (i32 31) 702; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[X]] to <2 x i32> 703; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP0]] 704; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32> 705; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP1]] 706; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float> 707; CHECK-NEXT: ret <2 x float> [[TMP3]] 708; 709entry: 710 %call = tail call nnan ninf afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y) 711 ret <2 x float> %call 712} 713 714define double @test_pown_afn_nnan_ninf_f64(double %x, i32 %y) { 715; CHECK-LABEL: define double @test_pown_afn_nnan_ninf_f64 716; CHECK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) { 717; CHECK-NEXT: entry: 718; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn double @llvm.fabs.f64(double [[X]]) 719; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[__FABS]]) 720; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to double 721; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[__LOG2]], [[POWNI2F]] 722; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn double @_Z4exp2d(double [[__YLOGX]]) 723; CHECK-NEXT: [[__YTOU:%.*]] = zext i32 [[Y]] to i64 724; CHECK-NEXT: [[__YEVEN:%.*]] = shl i64 [[__YTOU]], 63 725; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[X]] to i64 726; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i64 [[__YEVEN]], [[TMP0]] 727; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[__EXP2]] to i64 728; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[__POW_SIGN]], [[TMP1]] 729; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to double 730; CHECK-NEXT: ret double [[TMP3]] 731; 732entry: 733 %call = tail call nnan ninf afn double @_Z4powndi(double %x, i32 %y) 734 ret double %call 735} 736 737define <2 x double> @test_pown_afn_nnan_ninf_v2f64(<2 x double> %x, <2 x i32> %y) { 738; CHECK-LABEL: define <2 x double> @test_pown_afn_nnan_ninf_v2f64 739; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 740; CHECK-NEXT: entry: 741; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[X]]) 742; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[__FABS]]) 743; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x double> 744; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[__LOG2]], [[POWNI2F]] 745; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]]) 746; CHECK-NEXT: [[__YTOU:%.*]] = zext <2 x i32> [[Y]] to <2 x i64> 747; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i64> [[__YTOU]], splat (i64 63) 748; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[X]] to <2 x i64> 749; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i64> [[__YEVEN]], [[TMP0]] 750; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[__EXP2]] to <2 x i64> 751; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[__POW_SIGN]], [[TMP1]] 752; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <2 x double> 753; CHECK-NEXT: ret <2 x double> [[TMP3]] 754; 755entry: 756 %call = tail call nnan ninf afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y) 757 ret <2 x double> %call 758} 759 760define half @test_pown_afn_nnan_ninf_f16(half %x, i32 %y) { 761; CHECK-LABEL: define half @test_pown_afn_nnan_ninf_f16 762; CHECK-SAME: (half [[X:%.*]], i32 [[Y:%.*]]) { 763; CHECK-NEXT: entry: 764; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn half @llvm.fabs.f16(half [[X]]) 765; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn half @llvm.log2.f16(half [[__FABS]]) 766; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to half 767; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn half [[__LOG2]], [[POWNI2F]] 768; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn half @llvm.exp2.f16(half [[__YLOGX]]) 769; CHECK-NEXT: [[__YTOU:%.*]] = trunc i32 [[Y]] to i16 770; CHECK-NEXT: [[__YEVEN:%.*]] = shl i16 [[__YTOU]], 15 771; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 772; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i16 [[__YEVEN]], [[TMP0]] 773; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[__EXP2]] to i16 774; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i16 [[__POW_SIGN]], [[TMP1]] 775; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP2]] to half 776; CHECK-NEXT: ret half [[TMP3]] 777; 778entry: 779 %call = tail call nnan ninf afn half @_Z4pownDhi(half %x, i32 %y) 780 ret half %call 781} 782 783define <2 x half> @test_pown_afn_nnan_ninf_v2f16(<2 x half> %x, <2 x i32> %y) { 784; CHECK-LABEL: define <2 x half> @test_pown_afn_nnan_ninf_v2f16 785; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) { 786; CHECK-NEXT: entry: 787; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x half> @llvm.fabs.v2f16(<2 x half> [[X]]) 788; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x half> @llvm.log2.v2f16(<2 x half> [[__FABS]]) 789; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x half> 790; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x half> [[__LOG2]], [[POWNI2F]] 791; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]]) 792; CHECK-NEXT: [[__YTOU:%.*]] = trunc <2 x i32> [[Y]] to <2 x i16> 793; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i16> [[__YTOU]], splat (i16 15) 794; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x half> [[X]] to <2 x i16> 795; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i16> [[__YEVEN]], [[TMP0]] 796; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[__EXP2]] to <2 x i16> 797; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i16> [[__POW_SIGN]], [[TMP1]] 798; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to <2 x half> 799; CHECK-NEXT: ret <2 x half> [[TMP3]] 800; 801entry: 802 %call = tail call nnan ninf afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y) 803 ret <2 x half> %call 804} 805 806define float @test_pown_fast_f32_nobuiltin(float %x, i32 %y) { 807; CHECK-LABEL: define float @test_pown_fast_f32_nobuiltin 808; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) { 809; CHECK-NEXT: entry: 810; CHECK-NEXT: [[CALL:%.*]] = tail call fast float @_Z4pownfi(float [[X]], i32 [[Y]]) #[[ATTR4:[0-9]+]] 811; CHECK-NEXT: ret float [[CALL]] 812; 813entry: 814 %call = tail call fast float @_Z4pownfi(float %x, i32 %y) #0 815 ret float %call 816} 817 818define float @test_pown_fast_f32_strictfp(float %x, i32 %y) #1 { 819; CHECK-LABEL: define float @test_pown_fast_f32_strictfp 820; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0:[0-9]+]] { 821; CHECK-NEXT: entry: 822; CHECK-NEXT: [[__FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]] 823; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]]) #[[ATTR0]] 824; CHECK-NEXT: [[POWNI2F:%.*]] = call fast float @llvm.experimental.constrained.sitofp.f32.i32(i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]] 825; CHECK-NEXT: [[__YLOGX:%.*]] = call fast float @llvm.experimental.constrained.fmul.f32(float [[POWNI2F]], float [[__LOG2]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]] 826; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) #[[ATTR0]] 827; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31 828; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32 829; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] 830; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 831; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]] 832; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float 833; CHECK-NEXT: ret float [[TMP3]] 834; 835entry: 836 %call = tail call fast float @_Z4pownfi(float %x, i32 %y) #1 837 ret float %call 838} 839 840define float @test_pown_fast_f32__y_poison(float %x) { 841; CHECK-LABEL: define float @test_pown_fast_f32__y_poison 842; CHECK-SAME: (float [[X:%.*]]) { 843; CHECK-NEXT: ret float poison 844; 845 %call = tail call fast float @_Z4pownfi(float %x, i32 poison) 846 ret float %call 847} 848 849define float @test_pown_afn_nnan_ninf_f32__y_3(float %x) { 850; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_3 851; CHECK-SAME: (float [[X:%.*]]) { 852; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 853; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]] 854; CHECK-NEXT: ret float [[__POWPROD]] 855; 856 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 3) 857 ret float %call 858} 859 860define float @test_pown_afn_nnan_ninf_f32__y_neg3(float %x) { 861; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg3 862; CHECK-SAME: (float [[X:%.*]]) { 863; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 864; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]] 865; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWPROD]] 866; CHECK-NEXT: ret float [[__1POWPROD]] 867; 868 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -3) 869 ret float %call 870} 871 872define float @test_pown_afn_nnan_ninf_f32__y_4(float %x) { 873; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_4 874; CHECK-SAME: (float [[X:%.*]]) { 875; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 876; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 877; CHECK-NEXT: ret float [[__POWX21]] 878; 879 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 4) 880 ret float %call 881} 882 883define float @test_pown_afn_nnan_ninf_f32__y_neg4(float %x) { 884; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg4 885; CHECK-SAME: (float [[X:%.*]]) { 886; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 887; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 888; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWX21]] 889; CHECK-NEXT: ret float [[__1POWPROD]] 890; 891 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -4) 892 ret float %call 893} 894 895define float @test_pown_afn_nnan_ninf_f32__y_5(float %x) { 896; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_5 897; CHECK-SAME: (float [[X:%.*]]) { 898; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 899; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 900; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX21]] 901; CHECK-NEXT: ret float [[__POWPROD]] 902; 903 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 5) 904 ret float %call 905} 906 907define float @test_pown_afn_nnan_ninf_f32__y_neg5(float %x) { 908; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg5 909; CHECK-SAME: (float [[X:%.*]]) { 910; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 911; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 912; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX21]] 913; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWPROD]] 914; CHECK-NEXT: ret float [[__1POWPROD]] 915; 916 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -5) 917 ret float %call 918} 919 920define float @test_pown_afn_nnan_ninf_f32__y_7(float %x) { 921; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_7 922; CHECK-SAME: (float [[X:%.*]]) { 923; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 924; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]] 925; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 926; CHECK-NEXT: [[__POWPROD2:%.*]] = fmul nnan ninf afn float [[__POWPROD]], [[__POWX21]] 927; CHECK-NEXT: ret float [[__POWPROD2]] 928; 929 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 7) 930 ret float %call 931} 932 933define float @test_pown_afn_nnan_ninf_f32__y_neg7(float %x) { 934; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg7 935; CHECK-SAME: (float [[X:%.*]]) { 936; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 937; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn float [[X]], [[__POWX2]] 938; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 939; CHECK-NEXT: [[__POWPROD2:%.*]] = fmul nnan ninf afn float [[__POWPROD]], [[__POWX21]] 940; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWPROD2]] 941; CHECK-NEXT: ret float [[__1POWPROD]] 942; 943 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -7) 944 ret float %call 945} 946 947define float @test_pown_afn_nnan_ninf_f32__y_8(float %x) { 948; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_8 949; CHECK-SAME: (float [[X:%.*]]) { 950; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 951; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 952; CHECK-NEXT: [[__POWX22:%.*]] = fmul nnan ninf afn float [[__POWX21]], [[__POWX21]] 953; CHECK-NEXT: ret float [[__POWX22]] 954; 955 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 8) 956 ret float %call 957} 958 959define float @test_pown_afn_nnan_ninf_f32__y_neg8(float %x) { 960; CHECK-LABEL: define float @test_pown_afn_nnan_ninf_f32__y_neg8 961; CHECK-SAME: (float [[X:%.*]]) { 962; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn float [[X]], [[X]] 963; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn float [[__POWX2]], [[__POWX2]] 964; CHECK-NEXT: [[__POWX22:%.*]] = fmul nnan ninf afn float [[__POWX21]], [[__POWX21]] 965; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[__POWX22]] 966; CHECK-NEXT: ret float [[__1POWPROD]] 967; 968 %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 -8) 969 ret float %call 970} 971 972define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_3(<2 x float> %x) { 973; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_3 974; CHECK-SAME: (<2 x float> [[X:%.*]]) { 975; CHECK-NEXT: entry: 976; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]] 977; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[__POWX2]] 978; CHECK-NEXT: ret <2 x float> [[__POWPROD]] 979; 980entry: 981 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 3, i32 3>) 982 ret <2 x float> %call 983} 984 985define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_4(<2 x float> %x) { 986; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_4 987; CHECK-SAME: (<2 x float> [[X:%.*]]) { 988; CHECK-NEXT: entry: 989; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]] 990; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn <2 x float> [[__POWX2]], [[__POWX2]] 991; CHECK-NEXT: ret <2 x float> [[__POWX21]] 992; 993entry: 994 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 4, i32 4>) 995 ret <2 x float> %call 996} 997 998define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg3(<2 x float> %x) { 999; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg3 1000; CHECK-SAME: (<2 x float> [[X:%.*]]) { 1001; CHECK-NEXT: entry: 1002; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]] 1003; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[__POWX2]] 1004; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn <2 x float> splat (float 1.000000e+00), [[__POWPROD]] 1005; CHECK-NEXT: ret <2 x float> [[__1POWPROD]] 1006; 1007entry: 1008 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -3, i32 -3>) 1009 ret <2 x float> %call 1010} 1011 1012define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg4(<2 x float> %x) { 1013; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_neg4 1014; CHECK-SAME: (<2 x float> [[X:%.*]]) { 1015; CHECK-NEXT: entry: 1016; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]] 1017; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn <2 x float> [[__POWX2]], [[__POWX2]] 1018; CHECK-NEXT: [[__1POWPROD:%.*]] = fdiv nnan ninf afn <2 x float> splat (float 1.000000e+00), [[__POWX21]] 1019; CHECK-NEXT: ret <2 x float> [[__1POWPROD]] 1020; 1021entry: 1022 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -4, i32 -4>) 1023 ret <2 x float> %call 1024} 1025 1026define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_5(<2 x float> %x) { 1027; CHECK-LABEL: define <2 x float> @test_pown_afn_nnan_ninf_v2f32__y_5 1028; CHECK-SAME: (<2 x float> [[X:%.*]]) { 1029; CHECK-NEXT: entry: 1030; CHECK-NEXT: [[__POWX2:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[X]] 1031; CHECK-NEXT: [[__POWX21:%.*]] = fmul nnan ninf afn <2 x float> [[__POWX2]], [[__POWX2]] 1032; CHECK-NEXT: [[__POWPROD:%.*]] = fmul nnan ninf afn <2 x float> [[X]], [[__POWX21]] 1033; CHECK-NEXT: ret <2 x float> [[__POWPROD]] 1034; 1035entry: 1036 %call = tail call afn nnan ninf <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 5, i32 5>) 1037 ret <2 x float> %call 1038} 1039 1040define float @test_pown_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) { 1041; CHECK-LABEL: define float @test_pown_f32__x_known_positive 1042; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) { 1043; CHECK-NEXT: entry: 1044; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[Y]]) 1045; CHECK-NEXT: ret float [[CALL]] 1046; 1047entry: 1048 %call = tail call float @_Z4pownfi(float %x, i32 %y) 1049 ret float %call 1050} 1051 1052define float @test_pown_afn_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) { 1053; CHECK-LABEL: define float @test_pown_afn_f32__x_known_positive 1054; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) { 1055; CHECK-NEXT: entry: 1056; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 [[Y]]) 1057; CHECK-NEXT: ret float [[CALL]] 1058; 1059entry: 1060 %call = tail call afn float @_Z4pownfi(float %x, i32 %y) 1061 ret float %call 1062} 1063 1064define float @test_pown_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) { 1065; CHECK-LABEL: define float @test_pown_afn_ninf_nnan_f32__x_known_positive 1066; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) { 1067; CHECK-NEXT: entry: 1068; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]]) 1069; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) 1070; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float 1071; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] 1072; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) 1073; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31 1074; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32 1075; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] 1076; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 1077; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]] 1078; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float 1079; CHECK-NEXT: ret float [[TMP3]] 1080; 1081entry: 1082 %call = tail call afn ninf nnan float @_Z4pownfi(float %x, i32 %y) 1083 ret float %call 1084} 1085 1086define float @test_pown_afn_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) { 1087; CHECK-LABEL: define float @test_pown_afn_f32__x_known_positive__y_4 1088; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) { 1089; CHECK-NEXT: entry: 1090; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 4) 1091; CHECK-NEXT: ret float [[CALL]] 1092; 1093entry: 1094 %call = tail call afn float @_Z4pownfi(float %x, i32 4) 1095 ret float %call 1096} 1097 1098define float @test_pown_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) { 1099; CHECK-LABEL: define float @test_pown_f32__x_known_positive__y_4 1100; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) { 1101; CHECK-NEXT: entry: 1102; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 4) 1103; CHECK-NEXT: ret float [[CALL]] 1104; 1105entry: 1106 %call = tail call float @_Z4pownfi(float %x, i32 4) 1107 ret float %call 1108} 1109 1110define float @test_pown_f32_y_known_even(float %x, i32 %y.arg) { 1111; CHECK-LABEL: define float @test_pown_f32_y_known_even 1112; CHECK-SAME: (float [[X:%.*]], i32 [[Y_ARG:%.*]]) { 1113; CHECK-NEXT: entry: 1114; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1 1115; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[Y]]) 1116; CHECK-NEXT: ret float [[CALL]] 1117; 1118entry: 1119 %y = shl i32 %y.arg, 1 1120 %call = tail call float @_Z4pownfi(float %x, i32 %y) 1121 ret float %call 1122} 1123 1124define float @test_fast_pown_f32_y_known_even(float %x, i32 %y.arg) { 1125; CHECK-LABEL: define float @test_fast_pown_f32_y_known_even 1126; CHECK-SAME: (float [[X:%.*]], i32 [[Y_ARG:%.*]]) { 1127; CHECK-NEXT: entry: 1128; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1 1129; CHECK-NEXT: [[__FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) 1130; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]]) 1131; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float 1132; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]] 1133; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) 1134; CHECK-NEXT: ret float [[__EXP2]] 1135; 1136entry: 1137 %y = shl i32 %y.arg, 1 1138 %call = tail call fast float @_Z4pownfi(float %x, i32 %y) 1139 ret float %call 1140} 1141 1142define float @test_fast_pown_f32_known_positive_y_known_even(float nofpclass(ninf nsub nnorm) %x, i32 %y.arg) { 1143; CHECK-LABEL: define float @test_fast_pown_f32_known_positive_y_known_even 1144; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y_ARG:%.*]]) { 1145; CHECK-NEXT: entry: 1146; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1 1147; CHECK-NEXT: [[__FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) 1148; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]]) 1149; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float 1150; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]] 1151; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) 1152; CHECK-NEXT: ret float [[__EXP2]] 1153; 1154entry: 1155 %y = shl i32 %y.arg, 1 1156 %call = tail call fast float @_Z4pownfi(float %x, i32 %y) 1157 ret float %call 1158} 1159 1160attributes #0 = { nobuiltin } 1161attributes #1 = { strictfp } 1162