1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s 3; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 -early-live-intervals -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s 4 5define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(ptr addrspace(1) %p) #4 { 6; GCN-LABEL: test_mul24_knownbits_kernel: 7; GCN: ; %bb.0: ; %entry 8; GCN-NEXT: v_and_b32_e32 v0, 3, v0 9; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 10; GCN-NEXT: v_mul_i32_i24_e32 v0, -5, v0 11; GCN-NEXT: v_and_b32_e32 v0, 0xffffffe0, v0 12; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 13; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] 14; GCN-NEXT: s_waitcnt lgkmcnt(0) 15; GCN-NEXT: v_mov_b32_e32 v2, s1 16; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 17; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc 18; GCN-NEXT: v_mov_b32_e32 v2, 0 19; GCN-NEXT: global_store_dword v[0:1], v2, off 20; GCN-NEXT: s_endpgm 21entry: 22 %0 = tail call i32 @llvm.amdgcn.workitem.id.x() #28, !range !4 23 %tid = and i32 %0, 3 24 %1 = mul nsw i32 %tid, -5 25 %v1 = and i32 %1, -32 26 %v2 = sext i32 %v1 to i64 27 %v3 = getelementptr inbounds float, ptr addrspace(1) %p, i64 %v2 28 store float 0.000, ptr addrspace(1) %v3, align 4 29 ret void 30} 31 32define i32 @f(i32 %x, i32 %y) { 33; GCN-LABEL: f: 34; GCN: ; %bb.0: 35; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 36; GCN-NEXT: v_or_b32_e32 v0, 0xffff80, v0 37; GCN-NEXT: v_or_b32_e32 v1, 0xffff80, v1 38; GCN-NEXT: v_mul_i32_i24_e32 v0, v0, v1 39; GCN-NEXT: v_lshrrev_b32_e32 v0, 14, v0 40; GCN-NEXT: s_setpc_b64 s[30:31] 41 %xx = or i32 %x, -128 ; 0xffffff80 42 %yy = or i32 %y, -128 ; 0xffffff80 43 %r = mul i32 %xx, %yy 44 %rr = lshr i32 %r, 14 45 ret i32 %rr 46} 47 48; Function Attrs: nounwind readnone speculatable 49declare i32 @llvm.amdgcn.workitem.id.x() #20 50 51!4 = !{i32 0, i32 1024} 52