1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefixes=GCN %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefixes=GCN %s 4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefixes=GCN %s 5 6; Test vector signed bitfield extract. 7define signext i8 @v_ashr_i8_i32(i32 %value) { 8; GCN-LABEL: v_ashr_i8_i32: 9; GCN: ; %bb.0: 10; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GCN-NEXT: v_bfe_i32 v0, v0, 4, 8 12; GCN-NEXT: s_setpc_b64 s[30:31] 13 %1 = ashr i32 %value, 4 14 %2 = trunc i32 %1 to i8 15 ret i8 %2 16} 17 18define signext i16 @v_ashr_i16_i32(i32 %value) { 19; GCN-LABEL: v_ashr_i16_i32: 20; GCN: ; %bb.0: 21; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 22; GCN-NEXT: v_bfe_i32 v0, v0, 9, 16 23; GCN-NEXT: s_setpc_b64 s[30:31] 24 %1 = ashr i32 %value, 9 25 %2 = trunc i32 %1 to i16 26 ret i16 %2 27} 28 29define signext i8 @v_lshr_i8_i32(i32 %value) { 30; GCN-LABEL: v_lshr_i8_i32: 31; GCN: ; %bb.0: 32; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 33; GCN-NEXT: v_bfe_i32 v0, v0, 4, 8 34; GCN-NEXT: s_setpc_b64 s[30:31] 35 %1 = lshr i32 %value, 4 36 %2 = trunc i32 %1 to i8 37 ret i8 %2 38} 39 40define signext i16 @v_lshr_i16_i32(i32 %value) { 41; GCN-LABEL: v_lshr_i16_i32: 42; GCN: ; %bb.0: 43; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 44; GCN-NEXT: v_bfe_i32 v0, v0, 9, 16 45; GCN-NEXT: s_setpc_b64 s[30:31] 46 %1 = lshr i32 %value, 9 47 %2 = trunc i32 %1 to i16 48 ret i16 %2 49} 50 51; Test vector bitfield extract for 64-bits. 52define i64 @v_ashr_i64(i64 %value) { 53; GCN-LABEL: v_ashr_i64: 54; GCN: ; %bb.0: 55; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 56; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1] 57; GCN-NEXT: v_bfe_i32 v0, v0, 0, 4 58; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 59; GCN-NEXT: s_setpc_b64 s[30:31] 60 %1 = ashr i64 %value, 10 61 %2 = shl i64 %1, 60 62 %3 = ashr i64 %2, 60 63 ret i64 %3 64} 65 66define i64 @v_lshr_i64(i64 %value) { 67; GCN-LABEL: v_lshr_i64: 68; GCN: ; %bb.0: 69; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 70; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1] 71; GCN-NEXT: v_bfe_i32 v0, v0, 0, 4 72; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 73; GCN-NEXT: s_setpc_b64 s[30:31] 74 %1 = lshr i64 %value, 10 75 %2 = shl i64 %1, 60 76 %3 = ashr i64 %2, 60 77 ret i64 %3 78} 79 80; Test scalar signed bitfield extract. 81define amdgpu_ps signext i8 @s_ashr_i8_i32(i32 inreg %value) { 82; GCN-LABEL: s_ashr_i8_i32: 83; GCN: ; %bb.0: 84; GCN-NEXT: s_bfe_i32 s0, s0, 0x80004 85; GCN-NEXT: ; return to shader part epilog 86 %1 = ashr i32 %value, 4 87 %2 = trunc i32 %1 to i8 88 ret i8 %2 89} 90 91define amdgpu_ps signext i16 @s_ashr_i16_i32(i32 inreg %value) { 92; GCN-LABEL: s_ashr_i16_i32: 93; GCN: ; %bb.0: 94; GCN-NEXT: s_bfe_i32 s0, s0, 0x100009 95; GCN-NEXT: ; return to shader part epilog 96 %1 = ashr i32 %value, 9 97 %2 = trunc i32 %1 to i16 98 ret i16 %2 99} 100 101define amdgpu_ps signext i8 @s_lshr_i8_i32(i32 inreg %value) { 102; GCN-LABEL: s_lshr_i8_i32: 103; GCN: ; %bb.0: 104; GCN-NEXT: s_bfe_i32 s0, s0, 0x80004 105; GCN-NEXT: ; return to shader part epilog 106 %1 = lshr i32 %value, 4 107 %2 = trunc i32 %1 to i8 108 ret i8 %2 109} 110 111define amdgpu_ps signext i16 @s_lshr_i16_i32(i32 inreg %value) { 112; GCN-LABEL: s_lshr_i16_i32: 113; GCN: ; %bb.0: 114; GCN-NEXT: s_bfe_i32 s0, s0, 0x100009 115; GCN-NEXT: ; return to shader part epilog 116 %1 = lshr i32 %value, 9 117 %2 = trunc i32 %1 to i16 118 ret i16 %2 119} 120 121; Test scalar bitfield extract for 64-bits. 122define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value) { 123; GCN-LABEL: s_ashr_i64: 124; GCN: ; %bb.0: 125; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x40001 126; GCN-NEXT: ; return to shader part epilog 127 %1 = ashr i64 %value, 1 128 %2 = shl i64 %1, 60 129 %3 = ashr i64 %2, 60 130 ret i64 %3 131} 132