1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s 3# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s 4 5--- 6name: v_s_exp_f32 7legalized: true 8body: | 9 bb.0: 10 liveins: $sgpr0 11 12 ; CHECK-LABEL: name: v_s_exp_f32 13 ; CHECK: liveins: $sgpr0 14 ; CHECK-NEXT: {{ $}} 15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 16 ; CHECK-NEXT: [[FEXP2_:%[0-9]+]]:sgpr(s32) = G_FEXP2 [[FEXP2_]] 17 ; CHECK-NEXT: $vgpr0 = COPY [[FEXP2_]](s32) 18 %0:_(s32) = COPY $sgpr0 19 %1:_(s32) = G_FEXP2 %1 20 $vgpr0 = COPY %1(s32) 21... 22--- 23name: v_s_exp_f16 24legalized: true 25body: | 26 bb.0: 27 liveins: $sgpr0 28 29 ; CHECK-LABEL: name: v_s_exp_f16 30 ; CHECK: liveins: $sgpr0 31 ; CHECK-NEXT: {{ $}} 32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 33 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 34 ; CHECK-NEXT: [[FEXP2_:%[0-9]+]]:sgpr(s16) = G_FEXP2 [[TRUNC]] 35 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[FEXP2_]](s16) 36 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 37 %0:_(s32) = COPY $sgpr0 38 %1:_(s16) = G_TRUNC %0(s32) 39 %2:_(s16) = G_FEXP2 %1 40 %3:_(s32) = G_ANYEXT %2(s16) 41 $vgpr0 = COPY %3(s32) 42 43... 44--- 45name: v_s_log_f32 46legalized: true 47body: | 48 bb.0: 49 liveins: $sgpr0 50 51 ; CHECK-LABEL: name: v_s_log_f32 52 ; CHECK: liveins: $sgpr0 53 ; CHECK-NEXT: {{ $}} 54 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 55 ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:sgpr(s32) = G_FLOG2 [[COPY]] 56 ; CHECK-NEXT: $vgpr0 = COPY [[FLOG2_]](s32) 57 %0:_(s32) = COPY $sgpr0 58 %1:_(s32) = G_FLOG2 %0 59 $vgpr0 = COPY %1(s32) 60 61... 62--- 63name: v_s_log_f16 64legalized: true 65body: | 66 bb.0: 67 liveins: $sgpr0 68 69 ; CHECK-LABEL: name: v_s_log_f16 70 ; CHECK: liveins: $sgpr0 71 ; CHECK-NEXT: {{ $}} 72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 73 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 74 ; CHECK-NEXT: [[FLOG2_:%[0-9]+]]:sgpr(s16) = G_FLOG2 [[TRUNC]] 75 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[FLOG2_]](s16) 76 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 77 %0:_(s32) = COPY $sgpr0 78 %1:_(s16) = G_TRUNC %0(s32) 79 %2:_(s16) = G_FLOG2 %1 80 %3:_(s32) = G_ANYEXT %2(s16) 81 $vgpr0 = COPY %3(s32) 82 83... 84--- 85name: v_s_rcp_f32 86legalized: true 87body: | 88 bb.0: 89 liveins: $sgpr0 90 91 ; CHECK-LABEL: name: v_s_rcp_f32 92 ; CHECK: liveins: $sgpr0 93 ; CHECK-NEXT: {{ $}} 94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 95 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY]](s32) 96 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) 97 %0:_(s32) = COPY $sgpr0 98 %1:_(s32) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0(s32) 99 $vgpr0 = COPY %1(s32) 100 101... 102--- 103name: v_s_rcp_f16 104legalized: true 105body: | 106 bb.0: 107 liveins: $sgpr0 108 109 ; CHECK-LABEL: name: v_s_rcp_f16 110 ; CHECK: liveins: $sgpr0 111 ; CHECK-NEXT: {{ $}} 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 113 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 114 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s16) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[TRUNC]](s16) 115 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[INT]](s16) 116 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 117 %0:_(s32) = COPY $sgpr0 118 %1:_(s16) = G_TRUNC %0(s32) 119 %2:_(s16) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1(s16) 120 %3:_(s32) = G_ANYEXT %2(s16) 121 $vgpr0 = COPY %3(s32) 122 123... 124--- 125name: v_s_rsq_f32 126legalized: true 127body: | 128 bb.0: 129 liveins: $sgpr0 130 131 ; CHECK-LABEL: name: v_s_rsq_f32 132 ; CHECK: liveins: $sgpr0 133 ; CHECK-NEXT: {{ $}} 134 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 135 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32) 136 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) 137 %0:_(s32) = COPY $sgpr0 138 %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0(s32) 139 $vgpr0 = COPY %1(s32) 140 141... 142--- 143name: v_s_rsq_f16 144legalized: true 145body: | 146 bb.0: 147 liveins: $sgpr0 148 149 ; CHECK-LABEL: name: v_s_rsq_f16 150 ; CHECK: liveins: $sgpr0 151 ; CHECK-NEXT: {{ $}} 152 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 153 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 154 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[TRUNC]](s16) 155 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[INT]](s16) 156 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 157 %0:_(s32) = COPY $sgpr0 158 %1:_(s16) = G_TRUNC %0(s32) 159 %2:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1(s16) 160 %3:_(s32) = G_ANYEXT %2(s16) 161 $vgpr0 = COPY %3(s32) 162 163... 164--- 165name: v_s_sqrt_f32 166legalized: true 167body: | 168 bb.0: 169 liveins: $sgpr0 170 171 ; CHECK-LABEL: name: v_s_sqrt_f32 172 ; CHECK: liveins: $sgpr0 173 ; CHECK-NEXT: {{ $}} 174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 175 ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:sgpr(s32) = G_FSQRT [[COPY]] 176 ; CHECK-NEXT: $vgpr0 = COPY [[FSQRT]](s32) 177 %0:_(s32) = COPY $sgpr0 178 %1:_(s32) = G_FSQRT %0 179 $vgpr0 = COPY %1(s32) 180 181... 182--- 183name: v_s_sqrt_f16 184legalized: true 185body: | 186 bb.0: 187 liveins: $sgpr0 188 189 ; CHECK-LABEL: name: v_s_sqrt_f16 190 ; CHECK: liveins: $sgpr0 191 ; CHECK-NEXT: {{ $}} 192 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 193 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 194 ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:sgpr(s16) = G_FSQRT [[TRUNC]] 195 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[FSQRT]](s16) 196 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 197 %0:_(s32) = COPY $sgpr0 198 %1:_(s16) = G_TRUNC %0(s32) 199 %2:_(s16) = G_FSQRT %1 200 %3:_(s32) = G_ANYEXT %2(s16) 201 $vgpr0 = COPY %3(s32) 202 203... 204--- 205name: v_amdgcn_sqrt_f32 206legalized: true 207body: | 208 bb.0: 209 liveins: $sgpr0 210 211 ; CHECK-LABEL: name: v_amdgcn_sqrt_f32 212 ; CHECK: liveins: $sgpr0 213 ; CHECK-NEXT: {{ $}} 214 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 215 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[COPY]](s32) 216 ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) 217 %0:_(s32) = COPY $sgpr0 218 %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0(s32) 219 $vgpr0 = COPY %1(s32) 220 221... 222--- 223name: v_amdgcn_sqrt_f16 224legalized: true 225body: | 226 bb.0: 227 liveins: $sgpr0 228 229 ; CHECK-LABEL: name: v_amdgcn_sqrt_f16 230 ; CHECK: liveins: $sgpr0 231 ; CHECK-NEXT: {{ $}} 232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 233 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) 234 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[TRUNC]](s16) 235 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[INT]](s16) 236 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 237 %0:_(s32) = COPY $sgpr0 238 %1:_(s16) = G_TRUNC %0(s32) 239 %2:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %1(s16) 240 %3:_(s32) = G_ANYEXT %2(s16) 241 $vgpr0 = COPY %3(s32) 242 243... 244