1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5name: test_min_max_ValK0_K1_f32 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9machineFunctionInfo: 10 mode: 11 ieee: true 12body: | 13 bb.1: 14 liveins: $vgpr0 15 16 ; CHECK-LABEL: name: test_min_max_ValK0_K1_f32 17 ; CHECK: liveins: $vgpr0 18 ; CHECK-NEXT: {{ $}} 19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 20 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 21 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 22 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 23 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 24 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY1]], [[COPY2]] 25 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32) 26 %0:vgpr(s32) = COPY $vgpr0 27 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 28 %7:vgpr(s32) = COPY %2(s32) 29 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7 30 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00 31 %8:vgpr(s32) = COPY %4(s32) 32 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8 33 $vgpr0 = COPY %5(s32) 34... 35 36--- 37name: test_min_max_K0Val_K1_f32 38legalized: true 39regBankSelected: true 40tracksRegLiveness: true 41machineFunctionInfo: 42 mode: 43 ieee: false 44body: | 45 bb.1: 46 liveins: $vgpr0 47 48 ; CHECK-LABEL: name: test_min_max_K0Val_K1_f32 49 ; CHECK: liveins: $vgpr0 50 ; CHECK-NEXT: {{ $}} 51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 52 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 53 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 54 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 55 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 56 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY1]], [[COPY2]] 57 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32) 58 %0:vgpr(s32) = COPY $vgpr0 59 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 60 %7:vgpr(s32) = COPY %2(s32) 61 %3:vgpr(s32) = nnan G_FMAXNUM %7, %0 62 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00 63 %8:vgpr(s32) = COPY %4(s32) 64 %5:vgpr(s32) = nnan G_FMINNUM %3, %8 65 $vgpr0 = COPY %5(s32) 66... 67 68--- 69name: test_min_K1max_ValK0_f16 70legalized: true 71regBankSelected: true 72tracksRegLiveness: true 73machineFunctionInfo: 74 mode: 75 ieee: true 76body: | 77 bb.1: 78 liveins: $vgpr0 79 80 ; CHECK-LABEL: name: test_min_K1max_ValK0_f16 81 ; CHECK: liveins: $vgpr0 82 ; CHECK-NEXT: {{ $}} 83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 84 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) 85 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 86 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[TRUNC]] 87 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16) 88 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400 89 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16) 90 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = G_AMDGPU_FMED3 [[FCANONICALIZE]], [[COPY1]], [[COPY2]] 91 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16) 92 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 93 %2:vgpr(s32) = COPY $vgpr0 94 %0:vgpr(s16) = G_TRUNC %2(s32) 95 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 96 %9:vgpr(s16) = G_FCANONICALIZE %0 97 %10:vgpr(s16) = COPY %3(s16) 98 %4:vgpr(s16) = G_FMAXNUM_IEEE %9, %10 99 %5:sgpr(s16) = G_FCONSTANT half 0xH4400 100 %11:vgpr(s16) = COPY %5(s16) 101 %6:vgpr(s16) = G_FMINNUM_IEEE %11, %4 102 %8:vgpr(s32) = G_ANYEXT %6(s16) 103 $vgpr0 = COPY %8(s32) 104 105... 106 107--- 108name: test_min_K1max_K0Val_f16 109legalized: true 110regBankSelected: true 111tracksRegLiveness: true 112machineFunctionInfo: 113 mode: 114 ieee: false 115body: | 116 bb.1: 117 liveins: $vgpr0, $sgpr30_sgpr31 118 119 ; CHECK-LABEL: name: test_min_K1max_K0Val_f16 120 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 121 ; CHECK-NEXT: {{ $}} 122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 123 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) 124 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 125 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16) 126 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400 127 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16) 128 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY1]], [[COPY2]] 129 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16) 130 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 131 %2:vgpr(s32) = COPY $vgpr0 132 %0:vgpr(s16) = G_TRUNC %2(s32) 133 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 134 %9:vgpr(s16) = COPY %3(s16) 135 %4:vgpr(s16) = nnan G_FMAXNUM %9, %0 136 %5:sgpr(s16) = G_FCONSTANT half 0xH4400 137 %10:vgpr(s16) = COPY %5(s16) 138 %6:vgpr(s16) = nnan G_FMINNUM %10, %4 139 %8:vgpr(s32) = G_ANYEXT %6(s16) 140 $vgpr0 = COPY %8(s32) 141... 142 143--- 144name: test_max_min_ValK1_K0_f32 145legalized: true 146regBankSelected: true 147tracksRegLiveness: true 148machineFunctionInfo: 149 mode: 150 ieee: true 151body: | 152 bb.1: 153 liveins: $vgpr0 154 155 ; CHECK-LABEL: name: test_max_min_ValK1_K0_f32 156 ; CHECK: liveins: $vgpr0 157 ; CHECK-NEXT: {{ $}} 158 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 159 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 160 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 161 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 162 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 163 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY2]], [[COPY1]] 164 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32) 165 %0:vgpr(s32) = COPY $vgpr0 166 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00 167 %7:vgpr(s32) = COPY %2(s32) 168 %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7 169 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00 170 %8:vgpr(s32) = COPY %4(s32) 171 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8 172 $vgpr0 = COPY %5(s32) 173... 174 175--- 176name: test_max_min_K1Val_K0_f32 177legalized: true 178regBankSelected: true 179tracksRegLiveness: true 180machineFunctionInfo: 181 mode: 182 ieee: false 183body: | 184 bb.1: 185 liveins: $vgpr0 186 187 ; CHECK-LABEL: name: test_max_min_K1Val_K0_f32 188 ; CHECK: liveins: $vgpr0 189 ; CHECK-NEXT: {{ $}} 190 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 191 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 192 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 193 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 194 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 195 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[COPY]], [[COPY2]], [[COPY1]] 196 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32) 197 %0:vgpr(s32) = COPY $vgpr0 198 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00 199 %7:vgpr(s32) = COPY %2(s32) 200 %3:vgpr(s32) = nnan G_FMINNUM %7, %0 201 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00 202 %8:vgpr(s32) = COPY %4(s32) 203 %5:vgpr(s32) = nnan G_FMAXNUM %3, %8 204 $vgpr0 = COPY %5(s32) 205... 206 207--- 208name: test_max_K0min_ValK1_f16 209legalized: true 210regBankSelected: true 211tracksRegLiveness: true 212machineFunctionInfo: 213 mode: 214 ieee: true 215body: | 216 bb.1: 217 liveins: $vgpr0 218 219 ; CHECK-LABEL: name: test_max_K0min_ValK1_f16 220 ; CHECK: liveins: $vgpr0 221 ; CHECK-NEXT: {{ $}} 222 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 223 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) 224 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400 225 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16) 226 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 227 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16) 228 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]] 229 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16) 230 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 231 %2:vgpr(s32) = COPY $vgpr0 232 %0:vgpr(s16) = G_TRUNC %2(s32) 233 %3:sgpr(s16) = G_FCONSTANT half 0xH4400 234 %9:vgpr(s16) = COPY %3(s16) 235 %4:vgpr(s16) = nnan G_FMINNUM_IEEE %0, %9 236 %5:sgpr(s16) = G_FCONSTANT half 0xH4000 237 %10:vgpr(s16) = COPY %5(s16) 238 %6:vgpr(s16) = nnan G_FMAXNUM_IEEE %10, %4 239 %8:vgpr(s32) = G_ANYEXT %6(s16) 240 $vgpr0 = COPY %8(s32) 241... 242 243--- 244name: test_max_K0min_K1Val_f16 245legalized: true 246regBankSelected: true 247tracksRegLiveness: true 248machineFunctionInfo: 249 mode: 250 ieee: false 251body: | 252 bb.1: 253 liveins: $vgpr0, $sgpr30_sgpr31 254 255 ; CHECK-LABEL: name: test_max_K0min_K1Val_f16 256 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 257 ; CHECK-NEXT: {{ $}} 258 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 259 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) 260 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400 261 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16) 262 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 263 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C1]](s16) 264 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_FMED3 [[TRUNC]], [[COPY2]], [[COPY1]] 265 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_FMED3_]](s16) 266 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 267 %2:vgpr(s32) = COPY $vgpr0 268 %0:vgpr(s16) = G_TRUNC %2(s32) 269 %3:sgpr(s16) = G_FCONSTANT half 0xH4400 270 %9:vgpr(s16) = COPY %3(s16) 271 %4:vgpr(s16) = nnan G_FMINNUM %9, %0 272 %5:sgpr(s16) = G_FCONSTANT half 0xH4000 273 %10:vgpr(s16) = COPY %5(s16) 274 %6:vgpr(s16) = nnan G_FMAXNUM %10, %4 275 %8:vgpr(s32) = G_ANYEXT %6(s16) 276 $vgpr0 = COPY %8(s32) 277... 278 279# FixMe: add tests with attributes #2 = {"no-nans-fp-math"="true"} 280 281--- 282name: test_min_max_K0_gt_K1 283legalized: true 284regBankSelected: true 285tracksRegLiveness: true 286machineFunctionInfo: 287 mode: 288 ieee: true 289body: | 290 bb.1: 291 liveins: $vgpr0 292 293 ; CHECK-LABEL: name: test_min_max_K0_gt_K1 294 ; CHECK: liveins: $vgpr0 295 ; CHECK-NEXT: {{ $}} 296 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 297 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 298 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 299 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]] 300 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 301 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 302 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]] 303 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) 304 %0:vgpr(s32) = COPY $vgpr0 305 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00 306 %7:vgpr(s32) = COPY %2(s32) 307 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7 308 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00 309 %8:vgpr(s32) = COPY %4(s32) 310 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8 311 $vgpr0 = COPY %5(s32) 312... 313 314--- 315name: test_max_min_K0_gt_K1 316legalized: true 317regBankSelected: true 318tracksRegLiveness: true 319machineFunctionInfo: 320 mode: 321 ieee: true 322body: | 323 bb.1: 324 liveins: $vgpr0 325 326 ; CHECK-LABEL: name: test_max_min_K0_gt_K1 327 ; CHECK: liveins: $vgpr0 328 ; CHECK-NEXT: {{ $}} 329 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 330 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 331 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 332 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] 333 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 334 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 335 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]] 336 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32) 337 %0:vgpr(s32) = COPY $vgpr0 338 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 339 %7:vgpr(s32) = COPY %2(s32) 340 %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7 341 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00 342 %8:vgpr(s32) = COPY %4(s32) 343 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8 344 $vgpr0 = COPY %5(s32) 345... 346 347--- 348name: test_min_max_non_inline_const 349legalized: true 350regBankSelected: true 351tracksRegLiveness: true 352machineFunctionInfo: 353 mode: 354 ieee: true 355body: | 356 bb.1: 357 liveins: $vgpr0 358 359 ; CHECK-LABEL: name: test_min_max_non_inline_const 360 ; CHECK: liveins: $vgpr0 361 ; CHECK-NEXT: {{ $}} 362 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 363 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 364 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 365 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]] 366 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 8.000000e+00 367 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 368 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]] 369 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) 370 %0:vgpr(s32) = COPY $vgpr0 371 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 372 %7:vgpr(s32) = COPY %2(s32) 373 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7 374 %4:sgpr(s32) = G_FCONSTANT float 8.000000e+00 375 %8:vgpr(s32) = COPY %4(s32) 376 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8 377 $vgpr0 = COPY %5(s32) 378... 379 380--- 381name: test_min_max_f64 382legalized: true 383regBankSelected: true 384tracksRegLiveness: true 385machineFunctionInfo: 386 mode: 387 ieee: true 388body: | 389 bb.1: 390 liveins: $vgpr0_vgpr1 391 392 ; CHECK-LABEL: name: test_min_max_f64 393 ; CHECK: liveins: $vgpr0_vgpr1 394 ; CHECK-NEXT: {{ $}} 395 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 396 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00 397 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64) 398 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]] 399 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 4.000000e+00 400 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[C1]](s64) 401 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s64) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]] 402 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMINNUM_IEEE]](s64) 403 %0:vgpr(s64) = COPY $vgpr0_vgpr1 404 %4:sgpr(s64) = G_FCONSTANT double 2.000000e+00 405 %11:vgpr(s64) = COPY %4(s64) 406 %5:vgpr(s64) = nnan G_FMAXNUM_IEEE %0, %11 407 %6:sgpr(s64) = G_FCONSTANT double 4.000000e+00 408 %12:vgpr(s64) = COPY %6(s64) 409 %7:vgpr(s64) = nnan G_FMINNUM_IEEE %5, %12 410 $vgpr0_vgpr1 = COPY %7(s64) 411... 412 413--- 414name: test_min_max_v2f16 415legalized: true 416regBankSelected: true 417tracksRegLiveness: true 418machineFunctionInfo: 419 mode: 420 ieee: true 421body: | 422 bb.1: 423 liveins: $vgpr0 424 425 ; CHECK-LABEL: name: test_min_max_v2f16 426 ; CHECK: liveins: $vgpr0 427 ; CHECK-NEXT: {{ $}} 428 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0 429 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 430 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16) 431 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32) 432 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4400 433 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C1]](s16) 434 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT1]](s32), [[ANYEXT1]](s32) 435 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) 436 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]] 437 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>) 438 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]] 439 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](<2 x s16>) 440 %0:vgpr(<2 x s16>) = COPY $vgpr0 441 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 442 %9:sgpr(s32) = G_ANYEXT %3(s16) 443 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32) 444 %6:sgpr(s16) = G_FCONSTANT half 0xH4400 445 %10:sgpr(s32) = G_ANYEXT %6(s16) 446 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32) 447 %11:vgpr(<2 x s16>) = COPY %2(<2 x s16>) 448 %4:vgpr(<2 x s16>) = nnan G_FMAXNUM_IEEE %0, %11 449 %12:vgpr(<2 x s16>) = COPY %5(<2 x s16>) 450 %7:vgpr(<2 x s16>) = nnan G_FMINNUM_IEEE %4, %12 451 $vgpr0 = COPY %7(<2 x s16>) 452... 453 454--- 455name: test_min_max_maybe_NaN_input_ieee_false 456legalized: true 457regBankSelected: true 458tracksRegLiveness: true 459machineFunctionInfo: 460 mode: 461 ieee: false 462body: | 463 bb.1: 464 liveins: $vgpr0 465 466 ; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_false 467 ; CHECK: liveins: $vgpr0 468 ; CHECK-NEXT: {{ $}} 469 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 470 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 471 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 472 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[COPY]], [[COPY1]] 473 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 474 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 475 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY2]] 476 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32) 477 %0:vgpr(s32) = COPY $vgpr0 478 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 479 %7:vgpr(s32) = COPY %2(s32) 480 %3:vgpr(s32) = G_FMAXNUM %0, %7 481 %4:sgpr(s32) = G_FCONSTANT float 4.000000e+00 482 %8:vgpr(s32) = COPY %4(s32) 483 %5:vgpr(s32) = G_FMINNUM %3, %8 484 $vgpr0 = COPY %5(s32) 485... 486 487--- 488name: test_max_min_maybe_NaN_input_ieee_false 489legalized: true 490regBankSelected: true 491tracksRegLiveness: true 492machineFunctionInfo: 493 mode: 494 ieee: false 495body: | 496 bb.1: 497 liveins: $vgpr0 498 499 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_false 500 ; CHECK: liveins: $vgpr0 501 ; CHECK-NEXT: {{ $}} 502 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 503 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 504 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 505 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[COPY]], [[COPY1]] 506 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 507 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 508 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY2]] 509 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32) 510 %0:vgpr(s32) = COPY $vgpr0 511 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00 512 %7:vgpr(s32) = COPY %2(s32) 513 %3:vgpr(s32) = G_FMINNUM %0, %7 514 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00 515 %8:vgpr(s32) = COPY %4(s32) 516 %5:vgpr(s32) = G_FMAXNUM %3, %8 517 $vgpr0 = COPY %5(s32) 518... 519 520--- 521name: test_max_min_maybe_NaN_input_ieee_true 522legalized: true 523regBankSelected: true 524tracksRegLiveness: true 525machineFunctionInfo: 526 mode: 527 ieee: true 528body: | 529 bb.1: 530 liveins: $vgpr0 531 532 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_true 533 ; CHECK: liveins: $vgpr0 534 ; CHECK-NEXT: {{ $}} 535 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 536 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 4.000000e+00 537 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]] 538 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 539 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]] 540 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 541 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 542 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]] 543 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32) 544 %0:vgpr(s32) = COPY $vgpr0 545 %2:sgpr(s32) = G_FCONSTANT float 4.000000e+00 546 %7:vgpr(s32) = G_FCANONICALIZE %0 547 %8:vgpr(s32) = COPY %2(s32) 548 %3:vgpr(s32) = G_FMINNUM_IEEE %7, %8 549 %4:sgpr(s32) = G_FCONSTANT float 2.000000e+00 550 %9:vgpr(s32) = COPY %4(s32) 551 %5:vgpr(s32) = G_FMAXNUM_IEEE %3, %9 552 $vgpr0 = COPY %5(s32) 553... 554