1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5name: test_min_max_ValK0_K1_f32 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9machineFunctionInfo: 10 mode: 11 ieee: true 12 dx10-clamp: true 13body: | 14 bb.1 : 15 liveins: $vgpr0 16 17 ; CHECK-LABEL: name: test_min_max_ValK0_K1_f32 18 ; CHECK: liveins: $vgpr0 19 ; CHECK-NEXT: {{ $}} 20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 21 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 22 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 23 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] 24 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]] 25 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) 26 %0:vgpr(s32) = COPY $vgpr0 27 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 28 %9:vgpr(s32) = COPY %2(s32) 29 %3:vgpr(s32) = G_FMUL %0, %9 30 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00 31 %10:vgpr(s32) = COPY %4(s32) 32 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %10 33 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00 34 %11:vgpr(s32) = COPY %6(s32) 35 %7:vgpr(s32) = nnan G_FMINNUM_IEEE %5, %11 36 $vgpr0 = COPY %7(s32) 37... 38 39--- 40name: test_min_max_K0Val_K1_f64 41legalized: true 42regBankSelected: true 43tracksRegLiveness: true 44machineFunctionInfo: 45 mode: 46 ieee: false 47 dx10-clamp: true 48body: | 49 bb.1 : 50 liveins: $vgpr0_vgpr1 51 52 ; CHECK-LABEL: name: test_min_max_K0Val_K1_f64 53 ; CHECK: liveins: $vgpr0_vgpr1 54 ; CHECK-NEXT: {{ $}} 55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 56 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00 57 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64) 58 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s64) = G_FMUL [[COPY]], [[COPY1]] 59 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s64) = nnan G_AMDGPU_CLAMP [[FMUL]] 60 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_CLAMP]](s64) 61 %0:vgpr(s64) = COPY $vgpr0_vgpr1 62 %4:sgpr(s64) = G_FCONSTANT double 2.000000e+00 63 %13:vgpr(s64) = COPY %4(s64) 64 %5:vgpr(s64) = G_FMUL %0, %13 65 %6:sgpr(s64) = G_FCONSTANT double 0.000000e+00 66 %14:vgpr(s64) = COPY %6(s64) 67 %7:vgpr(s64) = nnan G_FMAXNUM %14, %5 68 %8:sgpr(s64) = G_FCONSTANT double 1.000000e+00 69 %15:vgpr(s64) = COPY %8(s64) 70 %9:vgpr(s64) = nnan G_FMINNUM %7, %15 71 $vgpr0_vgpr1 = COPY %9(s64) 72... 73 74--- 75name: test_min_K1max_ValK0_f16 76legalized: true 77regBankSelected: true 78tracksRegLiveness: true 79machineFunctionInfo: 80 mode: 81 ieee: true 82 dx10-clamp: true 83body: | 84 bb.1 : 85 liveins: $vgpr0 86 87 ; CHECK-LABEL: name: test_min_K1max_ValK0_f16 88 ; CHECK: liveins: $vgpr0 89 ; CHECK-NEXT: {{ $}} 90 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 91 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) 92 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 93 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16) 94 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]] 95 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[FMUL]] 96 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = G_AMDGPU_CLAMP [[FCANONICALIZE]] 97 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16) 98 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 99 %2:vgpr(s32) = COPY $vgpr0 100 %0:vgpr(s16) = G_TRUNC %2(s32) 101 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 102 %12:vgpr(s16) = COPY %3(s16) 103 %4:vgpr(s16) = G_FMUL %0, %12 104 %5:sgpr(s16) = G_FCONSTANT half 0xH0000 105 %11:vgpr(s16) = G_FCANONICALIZE %4 106 %13:vgpr(s16) = COPY %5(s16) 107 %6:vgpr(s16) = G_FMAXNUM_IEEE %11, %13 108 %7:sgpr(s16) = G_FCONSTANT half 0xH3C00 109 %14:vgpr(s16) = COPY %7(s16) 110 %8:vgpr(s16) = G_FMINNUM_IEEE %14, %6 111 %10:vgpr(s32) = G_ANYEXT %8(s16) 112 $vgpr0 = COPY %10(s32) 113... 114 115--- 116name: test_min_K1max_K0Val_f16 117legalized: true 118regBankSelected: true 119tracksRegLiveness: true 120machineFunctionInfo: 121 mode: 122 ieee: false 123 dx10-clamp: true 124body: | 125 bb.1 : 126 liveins: $vgpr0 127 128 ; CHECK-LABEL: name: test_min_K1max_K0Val_f16 129 ; CHECK: liveins: $vgpr0 130 ; CHECK-NEXT: {{ $}} 131 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0 132 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 133 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16) 134 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32) 135 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) 136 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]] 137 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_AMDGPU_CLAMP [[FMUL]] 138 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>) 139 %0:vgpr(<2 x s16>) = COPY $vgpr0 140 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 141 %12:sgpr(s32) = G_ANYEXT %3(s16) 142 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %12(s32), %12(s32) 143 %6:sgpr(s16) = G_FCONSTANT half 0xH0000 144 %13:sgpr(s32) = G_ANYEXT %6(s16) 145 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %13(s32), %13(s32) 146 %9:sgpr(s16) = G_FCONSTANT half 0xH3C00 147 %14:sgpr(s32) = G_ANYEXT %9(s16) 148 %8:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %14(s32), %14(s32) 149 %15:vgpr(<2 x s16>) = COPY %2(<2 x s16>) 150 %4:vgpr(<2 x s16>) = G_FMUL %0, %15 151 %16:vgpr(<2 x s16>) = COPY %5(<2 x s16>) 152 %7:vgpr(<2 x s16>) = nnan G_FMAXNUM %16, %4 153 %17:vgpr(<2 x s16>) = COPY %8(<2 x s16>) 154 %10:vgpr(<2 x s16>) = nnan G_FMINNUM %17, %7 155 $vgpr0 = COPY %10(<2 x s16>) 156... 157 158--- 159name: test_min_max_splat_padded_with_undef 160legalized: true 161regBankSelected: true 162tracksRegLiveness: true 163machineFunctionInfo: 164 mode: 165 ieee: true 166 dx10-clamp: true 167body: | 168 bb.1 : 169 liveins: $vgpr0 170 171 ; CHECK-LABEL: name: test_min_max_splat_padded_with_undef 172 ; CHECK: liveins: $vgpr0 173 ; CHECK-NEXT: {{ $}} 174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0 175 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 176 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16) 177 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32) 178 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) 179 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]] 180 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(<2 x s16>) = G_FCANONICALIZE [[FMUL]] 181 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_CLAMP [[FCANONICALIZE]] 182 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>) 183 %0:vgpr(<2 x s16>) = COPY $vgpr0 184 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 185 %17:sgpr(s32) = G_ANYEXT %3(s16) 186 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %17(s32), %17(s32) 187 %6:sgpr(s16) = G_FCONSTANT half 0xH0000 188 %18:sgpr(s32) = G_ANYEXT %6(s16) 189 %19:sgpr(s32) = G_IMPLICIT_DEF 190 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %18(s32), %19(s32) 191 %10:sgpr(s16) = G_FCONSTANT half 0xH3C00 192 %20:sgpr(s32) = G_ANYEXT %10(s16) 193 %9:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %20(s32), %19(s32) 194 %21:vgpr(<2 x s16>) = COPY %2(<2 x s16>) 195 %4:vgpr(<2 x s16>) = G_FMUL %0, %21 196 %16:vgpr(<2 x s16>) = G_FCANONICALIZE %4 197 %22:vgpr(<2 x s16>) = COPY %5(<2 x s16>) 198 %8:vgpr(<2 x s16>) = G_FMAXNUM_IEEE %22, %16 199 %23:vgpr(<2 x s16>) = COPY %9(<2 x s16>) 200 %11:vgpr(<2 x s16>) = G_FMINNUM_IEEE %23, %8 201 $vgpr0 = COPY %11(<2 x s16>) 202... 203 204--- 205name: test_max_min_ValK1_K0_f32 206machineFunctionInfo: 207 mode: 208 ieee: true 209 dx10-clamp: true 210body: | 211 bb.1 : 212 liveins: $vgpr0 213 214 ; CHECK-LABEL: name: test_max_min_ValK1_K0_f32 215 ; CHECK: liveins: $vgpr0 216 ; CHECK-NEXT: {{ $}} 217 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 218 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 219 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 220 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] 221 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]] 222 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) 223 %0:vgpr(s32) = COPY $vgpr0 224 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 225 %9:vgpr(s32) = COPY %2(s32) 226 %3:vgpr(s32) = G_FMUL %0, %9 227 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00 228 %10:vgpr(s32) = COPY %4(s32) 229 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %10 230 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00 231 %11:vgpr(s32) = COPY %6(s32) 232 %7:vgpr(s32) = nnan G_FMAXNUM_IEEE %5, %11 233 $vgpr0 = COPY %7(s32) 234... 235 236--- 237name: test_max_min_K1Val_K0_f64 238legalized: true 239regBankSelected: true 240tracksRegLiveness: true 241machineFunctionInfo: 242 mode: 243 ieee: false 244 dx10-clamp: true 245body: | 246 bb.1 : 247 liveins: $vgpr0_vgpr1 248 249 ; CHECK-LABEL: name: test_max_min_K1Val_K0_f64 250 ; CHECK: liveins: $vgpr0_vgpr1 251 ; CHECK-NEXT: {{ $}} 252 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 253 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00 254 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64) 255 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s64) = G_FMUL [[COPY]], [[COPY1]] 256 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s64) = nnan G_AMDGPU_CLAMP [[FMUL]] 257 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_CLAMP]](s64) 258 %0:vgpr(s64) = COPY $vgpr0_vgpr1 259 %4:sgpr(s64) = G_FCONSTANT double 2.000000e+00 260 %13:vgpr(s64) = COPY %4(s64) 261 %5:vgpr(s64) = G_FMUL %0, %13 262 %6:sgpr(s64) = G_FCONSTANT double 1.000000e+00 263 %14:vgpr(s64) = COPY %6(s64) 264 %7:vgpr(s64) = nnan G_FMINNUM %14, %5 265 %8:sgpr(s64) = G_FCONSTANT double 0.000000e+00 266 %15:vgpr(s64) = COPY %8(s64) 267 %9:vgpr(s64) = nnan G_FMAXNUM %7, %15 268 $vgpr0_vgpr1 = COPY %9(s64) 269... 270 271--- 272name: test_max_K0min_ValK1_f16 273legalized: true 274regBankSelected: true 275tracksRegLiveness: true 276machineFunctionInfo: 277 mode: 278 ieee: true 279 dx10-clamp: true 280body: | 281 bb.1 : 282 liveins: $vgpr0 283 284 ; CHECK-LABEL: name: test_max_K0min_ValK1_f16 285 ; CHECK: liveins: $vgpr0 286 ; CHECK-NEXT: {{ $}} 287 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 288 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) 289 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 290 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16) 291 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]] 292 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]] 293 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16) 294 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) 295 %2:vgpr(s32) = COPY $vgpr0 296 %0:vgpr(s16) = G_TRUNC %2(s32) 297 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 298 %11:vgpr(s16) = COPY %3(s16) 299 %4:vgpr(s16) = G_FMUL %0, %11 300 %5:sgpr(s16) = G_FCONSTANT half 0xH3C00 301 %12:vgpr(s16) = COPY %5(s16) 302 %6:vgpr(s16) = nnan G_FMINNUM_IEEE %4, %12 303 %7:sgpr(s16) = G_FCONSTANT half 0xH0000 304 %13:vgpr(s16) = COPY %7(s16) 305 %8:vgpr(s16) = nnan G_FMAXNUM_IEEE %13, %6 306 %10:vgpr(s32) = G_ANYEXT %8(s16) 307 $vgpr0 = COPY %10(s32) 308... 309 310--- 311name: test_max_K0min_K1Val_v2f16 312legalized: true 313regBankSelected: true 314tracksRegLiveness: true 315machineFunctionInfo: 316 mode: 317 ieee: false 318 dx10-clamp: true 319body: | 320 bb.1 : 321 liveins: $vgpr0 322 323 ; CHECK-LABEL: name: test_max_K0min_K1Val_v2f16 324 ; CHECK: liveins: $vgpr0 325 ; CHECK-NEXT: {{ $}} 326 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0 327 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 328 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16) 329 ; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32) 330 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) 331 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]] 332 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_AMDGPU_CLAMP [[FMUL]] 333 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>) 334 %0:vgpr(<2 x s16>) = COPY $vgpr0 335 %3:sgpr(s16) = G_FCONSTANT half 0xH4000 336 %13:sgpr(s32) = G_ANYEXT %3(s16) 337 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %13(s32), %13(s32) 338 %6:sgpr(s16) = G_FCONSTANT half 0xH3C00 339 %14:sgpr(s32) = G_ANYEXT %6(s16) 340 %15:sgpr(s32) = G_IMPLICIT_DEF 341 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %14(s32), %15(s32) 342 %10:sgpr(s16) = G_FCONSTANT half 0xH0000 343 %16:sgpr(s32) = G_ANYEXT %10(s16) 344 %9:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %15(s32), %16(s32) 345 %17:vgpr(<2 x s16>) = COPY %2(<2 x s16>) 346 %4:vgpr(<2 x s16>) = G_FMUL %0, %17 347 %18:vgpr(<2 x s16>) = COPY %5(<2 x s16>) 348 %8:vgpr(<2 x s16>) = nnan G_FMINNUM %18, %4 349 %19:vgpr(<2 x s16>) = COPY %9(<2 x s16>) 350 %11:vgpr(<2 x s16>) = nnan G_FMAXNUM %19, %8 351 $vgpr0 = COPY %11(<2 x s16>) 352... 353 354# FixMe: add tests with attributes #3 = {"no-nans-fp-math"="true"} 355 356--- 357name: test_min_max_K0_gt_K1 358legalized: true 359regBankSelected: true 360tracksRegLiveness: true 361machineFunctionInfo: 362 mode: 363 ieee: true 364 dx10-clamp: true 365body: | 366 bb.1 : 367 liveins: $vgpr0 368 369 ; CHECK-LABEL: name: test_min_max_K0_gt_K1 370 ; CHECK: liveins: $vgpr0 371 ; CHECK-NEXT: {{ $}} 372 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 373 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00 374 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 375 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]] 376 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00 377 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 378 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]] 379 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) 380 %0:vgpr(s32) = COPY $vgpr0 381 %2:sgpr(s32) = G_FCONSTANT float 1.000000e+00 382 %7:vgpr(s32) = COPY %2(s32) 383 %3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7 384 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00 385 %8:vgpr(s32) = COPY %4(s32) 386 %5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8 387 $vgpr0 = COPY %5(s32) 388... 389 390--- 391name: test_max_min_K0_gt_K1 392legalized: true 393regBankSelected: true 394tracksRegLiveness: true 395machineFunctionInfo: 396 mode: 397 ieee: true 398 dx10-clamp: true 399body: | 400 bb.1 : 401 liveins: $vgpr0 402 403 ; CHECK-LABEL: name: test_max_min_K0_gt_K1 404 ; CHECK: liveins: $vgpr0 405 ; CHECK-NEXT: {{ $}} 406 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 407 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00 408 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 409 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] 410 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00 411 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 412 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]] 413 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32) 414 %0:vgpr(s32) = COPY $vgpr0 415 %2:sgpr(s32) = G_FCONSTANT float 0.000000e+00 416 %7:vgpr(s32) = COPY %2(s32) 417 %3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7 418 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00 419 %8:vgpr(s32) = COPY %4(s32) 420 %5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8 421 $vgpr0 = COPY %5(s32) 422... 423 424--- 425name: test_min_max_maybe_NaN_input_ieee_false 426legalized: true 427regBankSelected: true 428tracksRegLiveness: true 429machineFunctionInfo: 430 mode: 431 ieee: false 432 dx10-clamp: true 433body: | 434 bb.1 : 435 liveins: $vgpr0 436 437 ; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_false 438 ; CHECK: liveins: $vgpr0 439 ; CHECK-NEXT: {{ $}} 440 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 441 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 442 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 443 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] 444 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00 445 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 446 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMUL]], [[COPY2]] 447 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00 448 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32) 449 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY3]] 450 ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32) 451 %0:vgpr(s32) = COPY $vgpr0 452 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 453 %9:vgpr(s32) = COPY %2(s32) 454 %3:vgpr(s32) = G_FMUL %0, %9 455 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00 456 %10:vgpr(s32) = COPY %4(s32) 457 %5:vgpr(s32) = G_FMAXNUM %3, %10 458 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00 459 %11:vgpr(s32) = COPY %6(s32) 460 %7:vgpr(s32) = G_FMINNUM %5, %11 461 $vgpr0 = COPY %7(s32) 462... 463 464--- 465name: test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false 466legalized: true 467regBankSelected: true 468tracksRegLiveness: true 469machineFunctionInfo: 470 mode: 471 ieee: true 472 dx10-clamp: false 473body: | 474 bb.1 : 475 liveins: $vgpr0 476 477 ; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false 478 ; CHECK: liveins: $vgpr0 479 ; CHECK-NEXT: {{ $}} 480 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 481 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 482 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 483 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] 484 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00 485 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[FMUL]] 486 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 487 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00 488 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32) 489 ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FMED3 [[FCANONICALIZE]], [[COPY2]], [[COPY3]] 490 ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32) 491 %0:vgpr(s32) = COPY $vgpr0 492 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 493 %10:vgpr(s32) = COPY %2(s32) 494 %3:vgpr(s32) = G_FMUL %0, %10 495 %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00 496 %9:vgpr(s32) = G_FCANONICALIZE %3 497 %11:vgpr(s32) = COPY %4(s32) 498 %5:vgpr(s32) = G_FMAXNUM_IEEE %9, %11 499 %6:sgpr(s32) = G_FCONSTANT float 1.000000e+00 500 %12:vgpr(s32) = COPY %6(s32) 501 %7:vgpr(s32) = G_FMINNUM_IEEE %5, %12 502 $vgpr0 = COPY %7(s32) 503... 504 505--- 506name: test_max_min_maybe_NaN_input_ieee_true 507legalized: true 508regBankSelected: true 509tracksRegLiveness: true 510machineFunctionInfo: 511 mode: 512 ieee: true 513 dx10-clamp: true 514body: | 515 bb.1 : 516 liveins: $vgpr0 517 518 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_true 519 ; CHECK: liveins: $vgpr0 520 ; CHECK-NEXT: {{ $}} 521 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 522 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 523 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 524 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] 525 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00 526 ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[FMUL]] 527 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 528 ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY2]] 529 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00 530 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32) 531 ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY3]] 532 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32) 533 %0:vgpr(s32) = COPY $vgpr0 534 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 535 %10:vgpr(s32) = COPY %2(s32) 536 %3:vgpr(s32) = G_FMUL %0, %10 537 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00 538 %9:vgpr(s32) = G_FCANONICALIZE %3 539 %11:vgpr(s32) = COPY %4(s32) 540 %5:vgpr(s32) = G_FMINNUM_IEEE %9, %11 541 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00 542 %12:vgpr(s32) = COPY %6(s32) 543 %7:vgpr(s32) = G_FMAXNUM_IEEE %5, %12 544 $vgpr0 = COPY %7(s32) 545... 546 547--- 548name: test_max_min_maybe_NaN_input_ieee_false 549legalized: true 550regBankSelected: true 551tracksRegLiveness: true 552machineFunctionInfo: 553 mode: 554 ieee: false 555 dx10-clamp: true 556body: | 557 bb.1 : 558 liveins: $vgpr0 559 560 ; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_false 561 ; CHECK: liveins: $vgpr0 562 ; CHECK-NEXT: {{ $}} 563 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 564 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 565 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) 566 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] 567 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00 568 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) 569 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMUL]], [[COPY2]] 570 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00 571 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32) 572 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY3]] 573 ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32) 574 %0:vgpr(s32) = COPY $vgpr0 575 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 576 %9:vgpr(s32) = COPY %2(s32) 577 %3:vgpr(s32) = G_FMUL %0, %9 578 %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00 579 %10:vgpr(s32) = COPY %4(s32) 580 %5:vgpr(s32) = G_FMINNUM %3, %10 581 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00 582 %11:vgpr(s32) = COPY %6(s32) 583 %7:vgpr(s32) = G_FMAXNUM %5, %11 584 $vgpr0 = COPY %7(s32) 585... 586