xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir (revision 847bb26820b1fdd23ddeb1ee87149bceef45a724)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
3
4# Post-legalizer should not generate illegal extending loads
5---
6name: zextload_from_load_and_mask
7tracksRegLiveness: true
8legalized: true
9body: |
10  bb.0:
11    liveins: $vgpr0_vgpr1
12    ; CHECK-LABEL: name: zextload_from_load_and_mask
13    ; CHECK: liveins: $vgpr0_vgpr1
14    ; CHECK-NEXT: {{  $}}
15    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
16    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
17    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
18    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
19    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
20    %0:_(p1) = COPY $vgpr0_vgpr1
21    %1:_(s64) = G_CONSTANT i64 255
22    %2:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)
23    %3:_(s64) = G_AND %2, %1
24    $vgpr0_vgpr1 = COPY %3
25...
26