xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir (revision 1ee6ce9bad4d7d61e5c6d37ebd5bfa89b91096c6) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
3
4# Post-legalizer should not generate illegal extending loads
5---
6name: zextload_from_inreg
7tracksRegLiveness: true
8legalized: true
9body: |
10  bb.0:
11    liveins: $vgpr0_vgpr1
12    ; CHECK-LABEL: name: zextload_from_inreg
13    ; CHECK: liveins: $vgpr0_vgpr1
14    ; CHECK-NEXT: {{  $}}
15    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
16    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
17    ; CHECK-NEXT: %k:_(s64) = G_CONSTANT i64 4294967295
18    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], %k
19    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
20    %0:_(p1) = COPY $vgpr0_vgpr1
21    %1:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)
22    %k:_(s64) = G_CONSTANT i64 4294967295
23    %2:_(s64) = G_AND %1, %k
24    $vgpr0_vgpr1 = COPY %2
25...
26
27# Legal to fold into zextload
28---
29name: zext_inreg_8_zextload_s32
30tracksRegLiveness: true
31legalized: true
32body: |
33  bb.0:
34    liveins: $vgpr0_vgpr1
35    ; CHECK-LABEL: name: zext_inreg_8_zextload_s32
36    ; CHECK: liveins: $vgpr0_vgpr1
37    ; CHECK-NEXT: {{  $}}
38    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
39    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
40    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
41    %0:_(p1) = COPY $vgpr0_vgpr1
42    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
43    %k:_(s32) = G_CONSTANT i32 255
44    %2:_(s32) = G_AND %1, %k
45    $vgpr0 = COPY %2
46...
47
48---
49name: zext_inreg_7_zextload_s32
50tracksRegLiveness: true
51legalized: true
52body: |
53  bb.0:
54    liveins: $vgpr0_vgpr1
55    ; CHECK-LABEL: name: zext_inreg_7_zextload_s32
56    ; CHECK: liveins: $vgpr0_vgpr1
57    ; CHECK-NEXT: {{  $}}
58    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
59    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
60    ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 127
61    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
62    ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
63    %0:_(p1) = COPY $vgpr0_vgpr1
64    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
65    %k:_(s32) = G_CONSTANT i32 127
66    %2:_(s32) = G_AND %1, %k
67    $vgpr0 = COPY %2
68...
69
70---
71name: zext_inreg_9_zextload_s32
72tracksRegLiveness: true
73legalized: true
74body: |
75  bb.0:
76    liveins: $vgpr0_vgpr1
77    ; CHECK-LABEL: name: zext_inreg_9_zextload_s32
78    ; CHECK: liveins: $vgpr0_vgpr1
79    ; CHECK-NEXT: {{  $}}
80    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
81    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
82    ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 511
83    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
84    ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
85    %0:_(p1) = COPY $vgpr0_vgpr1
86    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
87    %k:_(s32) = G_CONSTANT i32 511
88    %2:_(s32) = G_AND %1, %k
89    $vgpr0 = COPY %2
90...
91
92# Legal to fold into zextload
93---
94name: zext_inreg_16_zextload_s32
95tracksRegLiveness: true
96legalized: true
97body: |
98  bb.0:
99    liveins: $vgpr0_vgpr1
100    ; CHECK-LABEL: name: zext_inreg_16_zextload_s32
101    ; CHECK: liveins: $vgpr0_vgpr1
102    ; CHECK-NEXT: {{  $}}
103    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
104    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
105    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
106    %0:_(p1) = COPY $vgpr0_vgpr1
107    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
108    %k:_(s32) = G_CONSTANT i32 65535
109    %2:_(s32) = G_AND %1, %k
110    $vgpr0 = COPY %2
111...
112
113---
114name: zext_inreg_8_zextload_s8
115tracksRegLiveness: true
116legalized: true
117body: |
118  bb.0:
119    liveins: $vgpr0_vgpr1
120    ; CHECK-LABEL: name: zext_inreg_8_zextload_s8
121    ; CHECK: liveins: $vgpr0_vgpr1
122    ; CHECK-NEXT: {{  $}}
123    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
124    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
125    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
126    %0:_(p1) = COPY $vgpr0_vgpr1
127    %1:_(s32) = G_LOAD %0 :: (load (s8), align 1, addrspace 1)
128    %k:_(s32) = G_CONSTANT i32 255
129    %2:_(s32) = G_AND %1, %k
130    $vgpr0 = COPY %2
131...
132
133---
134name: zext_inreg_8_zextload_s8_volatile
135tracksRegLiveness: true
136legalized: true
137body: |
138  bb.0:
139    liveins: $vgpr0_vgpr1
140    ; CHECK-LABEL: name: zext_inreg_8_zextload_s8_volatile
141    ; CHECK: liveins: $vgpr0_vgpr1
142    ; CHECK-NEXT: {{  $}}
143    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
144    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s8), addrspace 1)
145    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
146    %0:_(p1) = COPY $vgpr0_vgpr1
147    %1:_(s32) = G_LOAD %0 :: (volatile load (s8), align 1, addrspace 1)
148    %k:_(s32) = G_CONSTANT i32 255
149    %2:_(s32) = G_AND %1, %k
150    $vgpr0 = COPY %2
151...
152
153---
154name: zext_inreg_16_zextload_s16
155tracksRegLiveness: true
156legalized: true
157body: |
158  bb.0:
159    liveins: $vgpr0_vgpr1
160    ; CHECK-LABEL: name: zext_inreg_16_zextload_s16
161    ; CHECK: liveins: $vgpr0_vgpr1
162    ; CHECK-NEXT: {{  $}}
163    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
164    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
165    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
166    %0:_(p1) = COPY $vgpr0_vgpr1
167    %1:_(s32) = G_LOAD %0 :: (load (s16), align 2, addrspace 1)
168    %k:_(s32) = G_CONSTANT i32 65535
169    %2:_(s32) = G_AND %1, %k
170    $vgpr0 = COPY %2
171...
172
173---
174name: zext_inreg_16_zextload_s16_volatile
175tracksRegLiveness: true
176legalized: true
177body: |
178  bb.0:
179    liveins: $vgpr0_vgpr1
180    ; CHECK-LABEL: name: zext_inreg_16_zextload_s16_volatile
181    ; CHECK: liveins: $vgpr0_vgpr1
182    ; CHECK-NEXT: {{  $}}
183    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
184    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s16), addrspace 1)
185    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
186    %0:_(p1) = COPY $vgpr0_vgpr1
187    %1:_(s32) = G_LOAD %0 :: (volatile load (s16), align 2, addrspace 1)
188    %k:_(s32) = G_CONSTANT i32 65535
189    %2:_(s32) = G_AND %1, %k
190    $vgpr0 = COPY %2
191...
192