xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -global-isel=1 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
3
4---
5name:            v_mul_i64_no_zext
6body:             |
7  bb.0:
8    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
9
10    ; GFX10-LABEL: name: v_mul_i64_no_zext
11    ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
12    ; GFX10-NEXT: {{  $}}
13    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
14    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
15    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
16    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
17    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
18    ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C]]
19    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)
20    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
21    ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]
22    ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]
23    ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]]
24    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32)
25    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
26    %0:_(s64) = COPY $vgpr0_vgpr1
27    %1:_(s64) = COPY $vgpr2_vgpr3
28    %2:_(s64) = G_MUL %0, %1
29    $vgpr0_vgpr1 = COPY %2
30
31...
32---
33name:            v_mul_i64_zext_src1
34body:             |
35  bb.0:
36    liveins: $vgpr0_vgpr1, $vgpr2
37
38    ; GFX10-LABEL: name: v_mul_i64_zext_src1
39    ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
40    ; GFX10-NEXT: {{  $}}
41    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
42    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
43    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
44    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
45    ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[COPY1]], [[C]]
46    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)
47    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[COPY1]]
48    ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]
49    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)
50    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
51    %0:_(s64) = COPY $vgpr0_vgpr1
52    %1:_(s32) = COPY $vgpr2
53    %2:_(s64) = G_ZEXT %1(s32)
54    %3:_(s64) = G_MUL %0, %2
55    $vgpr0_vgpr1 = COPY %3
56
57...
58---
59name:            v_mul_i64_zext_src0
60body:             |
61  bb.0:
62    liveins: $vgpr0, $vgpr2_vgpr3
63
64    ; GFX10-LABEL: name: v_mul_i64_zext_src0
65    ; GFX10: liveins: $vgpr0, $vgpr2_vgpr3
66    ; GFX10-NEXT: {{  $}}
67    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
68    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
69    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
70    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
71    ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[COPY]](s32), [[UV2]], [[C]]
72    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)
73    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[UV3]]
74    ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]
75    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)
76    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
77    %0:_(s32) = COPY $vgpr0
78    %1:_(s64) = COPY $vgpr2_vgpr3
79    %2:_(s64) = G_ZEXT %0(s32)
80    %3:_(s64) = G_MUL %2, %1
81    $vgpr0_vgpr1 = COPY %3
82
83...
84---
85name:            v_mul_i64_zext_src0_src1
86body:             |
87  bb.0:
88    liveins: $vgpr0, $vgpr1
89
90    ; GFX10-LABEL: name: v_mul_i64_zext_src0_src1
91    ; GFX10: liveins: $vgpr0, $vgpr1
92    ; GFX10-NEXT: {{  $}}
93    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1
94    ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
95    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
96    %0:_(s32) = COPY $vgpr0
97    %1:_(s32) = COPY $vgpr1
98    %2:_(s64) = G_ZEXT %0(s32)
99    %3:_(s64) = G_ZEXT %1(s32)
100    %4:_(s64) = G_MUL %2, %3
101    $vgpr0_vgpr1 = COPY %3
102
103...
104---
105name:            v_mul_i64_masked_src0_hi
106body:             |
107  bb.0:
108    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
109
110    ; GFX10-LABEL: name: v_mul_i64_masked_src0_hi
111    ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
112    ; GFX10-NEXT: {{  $}}
113    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
114    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
115    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
116    ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
117    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
118    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
119    ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
120    ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C1]]
121    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)
122    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
123    ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]
124    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)
125    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
126    %0:_(s64) = COPY $vgpr0_vgpr1
127    %1:_(s64) = COPY $vgpr2_vgpr3
128    %2:_(s64) = G_CONSTANT i64 4294967295
129    %3:_(s64) = G_AND %0, %2
130    %4:_(s64) = G_MUL %3, %1
131    $vgpr0_vgpr1 = COPY %4
132...
133---
134name:            v_mul_i64_masked_src0_lo
135body:             |
136  bb.0:
137    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
138
139    ; GFX10-LABEL: name: v_mul_i64_masked_src0_lo
140    ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
141    ; GFX10-NEXT: {{  $}}
142    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
143    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
144    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
145    ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
146    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
147    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
148    ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
149    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
150    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]
151    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[MUL]](s32)
152    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
153    %0:_(s64) = COPY $vgpr0_vgpr1
154    %1:_(s64) = COPY $vgpr2_vgpr3
155    %2:_(s64) = G_CONSTANT i64 -4294967296
156    %3:_(s64) = G_AND %0, %2
157    %4:_(s64) = G_MUL %3, %1
158    $vgpr0_vgpr1 = COPY %4
159
160...
161---
162name:            v_mul_i64_masked_src1_lo
163body:             |
164  bb.0:
165    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
166
167    ; GFX10-LABEL: name: v_mul_i64_masked_src1_lo
168    ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
169    ; GFX10-NEXT: {{  $}}
170    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
171    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
172    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
173    ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
174    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
175    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
176    ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
177    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
178    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
179    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[MUL]](s32)
180    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
181    %0:_(s64) = COPY $vgpr0_vgpr1
182    %1:_(s64) = COPY $vgpr2_vgpr3
183    %2:_(s64) = G_CONSTANT i64 -4294967296
184    %3:_(s64) = G_AND %1, %2
185    %4:_(s64) = G_MUL %0, %3
186    $vgpr0_vgpr1 = COPY %4
187
188...
189---
190name:            v_mul_i64_masked_src0
191body:             |
192  bb.0:
193    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
194
195    ; GFX10-LABEL: name: v_mul_i64_masked_src0
196    ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
197    ; GFX10-NEXT: {{  $}}
198    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
199    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[C]](s64)
200    %0:_(s64) = COPY $vgpr0_vgpr1
201    %1:_(s64) = COPY $vgpr2_vgpr3
202    %2:_(s64) = G_CONSTANT i64 0
203    %3:_(s64) = G_AND %0, %2
204    %4:_(s64) = G_MUL %3, %1
205    $vgpr0_vgpr1 = COPY %4
206...
207---
208name:            v_mul_i64_partially_masked_src0
209body:             |
210  bb.0:
211    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
212
213    ; GFX10-LABEL: name: v_mul_i64_partially_masked_src0
214    ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
215    ; GFX10-NEXT: {{  $}}
216    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
217    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
218    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 263951509094400
219    ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
220    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
221    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
222    ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
223    ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C1]]
224    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)
225    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
226    ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]
227    ; GFX10-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]
228    ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[MUL1]]
229    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD1]](s32)
230    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
231    %0:_(s64) = COPY $vgpr0_vgpr1
232    %1:_(s64) = COPY $vgpr2_vgpr3
233    %2:_(s64) = G_CONSTANT i64 263951509094400
234    %3:_(s64) = G_AND %0, %2
235    %4:_(s64) = G_MUL %3, %1
236    $vgpr0_vgpr1 = COPY %4
237...
238---
239name:            v_mul_i64_constant_hi
240body:             |
241  bb.0:
242    liveins: $vgpr0_vgpr1
243
244    ; GFX10-LABEL: name: v_mul_i64_constant_hi
245    ; GFX10: liveins: $vgpr0_vgpr1
246    ; GFX10-NEXT: {{  $}}
247    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
248    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
249    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
250    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
251    ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
252    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
253    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
254    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[MUL]](s32)
255    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
256    %0:_(s64) = COPY $vgpr0_vgpr1
257    %1:_(s64) = G_CONSTANT i64 -4294967296
258    %2:_(s64) = G_MUL %0, %1
259    $vgpr0_vgpr1 = COPY %2
260...
261---
262name:            v_mul_i64_constant_lo
263body:             |
264  bb.0:
265    liveins: $vgpr0_vgpr1
266
267    ; GFX10-LABEL: name: v_mul_i64_constant_lo
268    ; GFX10: liveins: $vgpr0_vgpr1
269    ; GFX10-NEXT: {{  $}}
270    ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
271    ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
272    ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
273    ; GFX10-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
274    ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
275    ; GFX10-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:_(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:_(s1) = G_AMDGPU_MAD_U64_U32 [[UV]](s32), [[UV2]], [[C1]]
276    ; GFX10-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_MAD_U64_U32_]](s64)
277    ; GFX10-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV2]]
278    ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[MUL]]
279    ; GFX10-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[ADD]](s32)
280    ; GFX10-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
281    %0:_(s64) = COPY $vgpr0_vgpr1
282    %1:_(s64) = G_CONSTANT i64 4294967295
283    %2:_(s64) = G_MUL %0, %1
284    $vgpr0_vgpr1 = COPY %2
285...
286