1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4define amdgpu_ps float @softwqm_f32(float %val) { 5 ; GCN-LABEL: name: softwqm_f32 6 ; GCN: bb.1 (%ir-block.0): 7 ; GCN-NEXT: liveins: $vgpr0 8 ; GCN-NEXT: {{ $}} 9 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 10 ; GCN-NEXT: [[SOFT_WQM:%[0-9]+]]:vgpr_32 = SOFT_WQM [[COPY]], implicit $exec 11 ; GCN-NEXT: $vgpr0 = COPY [[SOFT_WQM]] 12 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 13 %ret = call float @llvm.amdgcn.softwqm.f32(float %val) 14 ret float %ret 15} 16 17define amdgpu_ps float @softwqm_v2f16(float %arg) { 18 ; GCN-LABEL: name: softwqm_v2f16 19 ; GCN: bb.1 (%ir-block.0): 20 ; GCN-NEXT: liveins: $vgpr0 21 ; GCN-NEXT: {{ $}} 22 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 23 ; GCN-NEXT: [[SOFT_WQM:%[0-9]+]]:vgpr_32 = SOFT_WQM [[COPY]], implicit $exec 24 ; GCN-NEXT: $vgpr0 = COPY [[SOFT_WQM]] 25 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 26 %val = bitcast float %arg to <2 x half> 27 %ret = call <2 x half> @llvm.amdgcn.softwqm.v2f16(<2 x half> %val) 28 %bc = bitcast <2 x half> %ret to float 29 ret float %bc 30} 31 32define amdgpu_ps <2 x float> @softwqm_f64(double %val) { 33 ; GCN-LABEL: name: softwqm_f64 34 ; GCN: bb.1 (%ir-block.0): 35 ; GCN-NEXT: liveins: $vgpr0, $vgpr1 36 ; GCN-NEXT: {{ $}} 37 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 38 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 39 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 40 ; GCN-NEXT: [[SOFT_WQM:%[0-9]+]]:vreg_64 = SOFT_WQM [[REG_SEQUENCE]], implicit $exec 41 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub0 42 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub1 43 ; GCN-NEXT: $vgpr0 = COPY [[COPY2]] 44 ; GCN-NEXT: $vgpr1 = COPY [[COPY3]] 45 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 46 %ret = call double @llvm.amdgcn.softwqm.f64(double %val) 47 %bitcast = bitcast double %ret to <2 x float> 48 ret <2 x float> %bitcast 49} 50 51; TODO 52; define amdgpu_ps float @softwqm_i1_vcc(float %val) { 53; %vcc = fcmp oeq float %val, 0.0 54; %ret = call i1 @llvm.amdgcn.softwqm.i1(i1 %vcc) 55; %select = select i1 %ret, float 1.0, float 0.0 56; ret float %select 57; } 58 59define amdgpu_ps <3 x float> @softwqm_v3f32(<3 x float> %val) { 60 ; GCN-LABEL: name: softwqm_v3f32 61 ; GCN: bb.1 (%ir-block.0): 62 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 63 ; GCN-NEXT: {{ $}} 64 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 65 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 66 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 67 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 68 ; GCN-NEXT: [[SOFT_WQM:%[0-9]+]]:vreg_96 = SOFT_WQM [[REG_SEQUENCE]], implicit $exec 69 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub0 70 ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub1 71 ; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[SOFT_WQM]].sub2 72 ; GCN-NEXT: $vgpr0 = COPY [[COPY3]] 73 ; GCN-NEXT: $vgpr1 = COPY [[COPY4]] 74 ; GCN-NEXT: $vgpr2 = COPY [[COPY5]] 75 ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 76 %ret = call <3 x float> @llvm.amdgcn.softwqm.v3f32(<3 x float> %val) 77 ret <3 x float> %ret 78} 79 80declare i1 @llvm.amdgcn.softwqm.i1(i1) #0 81declare float @llvm.amdgcn.softwqm.f32(float) #0 82declare <2 x half> @llvm.amdgcn.softwqm.v2f16(<2 x half>) #0 83declare <3 x float> @llvm.amdgcn.softwqm.v3f32(<3 x float>) #0 84declare double @llvm.amdgcn.softwqm.f64(double) #0 85 86attributes #0 = { nounwind readnone speculatable } 87