xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX906 %s
3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
5
6define i32 @v_sdot4(i32 %a, i32 %b, i32 %c) {
7; GFX906-LABEL: v_sdot4:
8; GFX906:       ; %bb.0:
9; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
11; GFX906-NEXT:    s_setpc_b64 s[30:31]
12;
13; GFX10-LABEL: v_sdot4:
14; GFX10:       ; %bb.0:
15; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16; GFX10-NEXT:    v_dot4c_i32_i8 v2, v0, v1
17; GFX10-NEXT:    v_mov_b32_e32 v0, v2
18; GFX10-NEXT:    s_setpc_b64 s[30:31]
19  %r = call i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 false)
20  ret i32 %r
21}
22
23define i32 @v_sdot4_clamp(i32 %a, i32 %b, i32 %c) {
24; GFX906-LABEL: v_sdot4_clamp:
25; GFX906:       ; %bb.0:
26; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2 clamp
28; GFX906-NEXT:    s_setpc_b64 s[30:31]
29;
30; GFX10-LABEL: v_sdot4_clamp:
31; GFX10:       ; %bb.0:
32; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33; GFX10-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2 clamp
34; GFX10-NEXT:    s_setpc_b64 s[30:31]
35  %r = call i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 true)
36  ret i32 %r
37}
38
39; FIXME: bitcast should not expand
40define i32 @v_sdot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) {
41; GFX906-LABEL: v_sdot4_cast_v4i8:
42; GFX906:       ; %bb.0:
43; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
44; GFX906-NEXT:    v_mov_b32_e32 v10, 8
45; GFX906-NEXT:    v_mov_b32_e32 v9, 0xff
46; GFX906-NEXT:    v_lshlrev_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
47; GFX906-NEXT:    v_and_or_b32 v0, v0, v9, v1
48; GFX906-NEXT:    v_and_b32_e32 v1, 0xff, v2
49; GFX906-NEXT:    v_and_b32_e32 v2, 0xff, v3
50; GFX906-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
51; GFX906-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
52; GFX906-NEXT:    v_or3_b32 v0, v0, v1, v2
53; GFX906-NEXT:    v_lshlrev_b32_sdwa v1, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
54; GFX906-NEXT:    v_and_b32_e32 v2, 0xff, v6
55; GFX906-NEXT:    v_and_b32_e32 v3, 0xff, v7
56; GFX906-NEXT:    v_and_or_b32 v1, v4, v9, v1
57; GFX906-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
58; GFX906-NEXT:    v_lshlrev_b32_e32 v3, 24, v3
59; GFX906-NEXT:    v_or3_b32 v1, v1, v2, v3
60; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v8
61; GFX906-NEXT:    s_setpc_b64 s[30:31]
62;
63; GFX10-LABEL: v_sdot4_cast_v4i8:
64; GFX10:       ; %bb.0:
65; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
66; GFX10-NEXT:    v_mov_b32_e32 v9, 8
67; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
68; GFX10-NEXT:    v_and_or_b32 v0, 0xff, v0, v1
69; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v2
70; GFX10-NEXT:    v_and_b32_e32 v2, 0xff, v3
71; GFX10-NEXT:    v_lshlrev_b32_sdwa v3, v9, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
72; GFX10-NEXT:    v_and_b32_e32 v5, 0xff, v6
73; GFX10-NEXT:    v_and_b32_e32 v6, 0xff, v7
74; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
75; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
76; GFX10-NEXT:    v_and_or_b32 v3, 0xff, v4, v3
77; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v5
78; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 24, v6
79; GFX10-NEXT:    v_or3_b32 v0, v0, v1, v2
80; GFX10-NEXT:    v_or3_b32 v1, v3, v4, v5
81; GFX10-NEXT:    v_dot4c_i32_i8 v8, v0, v1
82; GFX10-NEXT:    v_mov_b32_e32 v0, v8
83; GFX10-NEXT:    s_setpc_b64 s[30:31]
84  %a.cast = bitcast <4 x i8> %a to i32
85  %b.cast = bitcast <4 x i8> %b to i32
86  %r = call i32 @llvm.amdgcn.sdot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)
87  ret i32 %r
88}
89
90define i32 @v_sdot4_fnegf32_a(float %a, i32 %b, i32 %c) {
91; GFX906-LABEL: v_sdot4_fnegf32_a:
92; GFX906:       ; %bb.0:
93; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
94; GFX906-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
95; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
96; GFX906-NEXT:    s_setpc_b64 s[30:31]
97;
98; GFX10-LABEL: v_sdot4_fnegf32_a:
99; GFX10:       ; %bb.0:
100; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
101; GFX10-NEXT:    v_xor_b32_e32 v0, 0x80000000, v0
102; GFX10-NEXT:    v_dot4c_i32_i8 v2, v0, v1
103; GFX10-NEXT:    v_mov_b32_e32 v0, v2
104; GFX10-NEXT:    s_setpc_b64 s[30:31]
105  %neg.a = fneg float %a
106  %cast.neg.a = bitcast float %neg.a to i32
107  %r = call i32 @llvm.amdgcn.sdot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
108  ret i32 %r
109}
110
111define i32 @v_sdot4_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {
112; GFX906-LABEL: v_sdot4_fnegv2f16_a:
113; GFX906:       ; %bb.0:
114; GFX906-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
115; GFX906-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
116; GFX906-NEXT:    v_dot4_i32_i8 v0, v0, v1, v2
117; GFX906-NEXT:    s_setpc_b64 s[30:31]
118;
119; GFX10-LABEL: v_sdot4_fnegv2f16_a:
120; GFX10:       ; %bb.0:
121; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
122; GFX10-NEXT:    v_xor_b32_e32 v0, 0x80008000, v0
123; GFX10-NEXT:    v_dot4c_i32_i8 v2, v0, v1
124; GFX10-NEXT:    v_mov_b32_e32 v0, v2
125; GFX10-NEXT:    s_setpc_b64 s[30:31]
126  %neg.a = fneg <2 x half> %a
127  %cast.neg.a = bitcast <2 x half> %neg.a to i32
128  %r = call i32 @llvm.amdgcn.sdot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
129  ret i32 %r
130}
131
132declare i32 @llvm.amdgcn.sdot4(i32, i32, i32, i1 immarg) #0
133
134attributes #0 = { nounwind readnone speculatable }
135